JPH031828B2 - - Google Patents
Info
- Publication number
- JPH031828B2 JPH031828B2 JP22474483A JP22474483A JPH031828B2 JP H031828 B2 JPH031828 B2 JP H031828B2 JP 22474483 A JP22474483 A JP 22474483A JP 22474483 A JP22474483 A JP 22474483A JP H031828 B2 JPH031828 B2 JP H031828B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- semiconductor
- circuit board
- semiconductor element
- element chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 48
- 239000000843 powder Substances 0.000 claims description 17
- 229920005989 resin Polymers 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical group 0.000 claims description 3
- 229920005992 thermoplastic resin Polymers 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000003973 paint Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 3
- 229910001887 tin oxide Inorganic materials 0.000 description 3
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009472 formulation Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000088 plastic resin Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000011417 postcuring Methods 0.000 description 1
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
- H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体素子チツプの電極パツド部の構
造に係り、回路基板上へ容易に、信頼性良く最少
面積で実装できる半導体装置を提供するものであ
る。[Detailed Description of the Invention] Industrial Application Field The present invention relates to the structure of an electrode pad portion of a semiconductor element chip, and provides a semiconductor device that can be easily and reliably mounted on a circuit board with a minimum area. .
従来例の構成とその問題点
近年、電子機器の小形、軽量、薄形など、いわ
ゆる軽薄短小の動さが益々活発となつてきた。半
導体装置としてもこれらニーズに合せ高機能化、
小形下への対応をはかつている。半導体装置とし
ては従来、デユアルインラインパツケージ
（DIL）やフラツトパツケージ（FP）で代表され
るように樹脂モールドを施したものがほとんどで
ある。したがって電子機器の軽薄短小化への対応
がこれら半導体装置の形状では困難となってい
る。Conventional configurations and their problems In recent years, electronic devices have become increasingly compact, lightweight, and thin, so-called light, thin, and short. Semiconductor devices are also highly functional to meet these needs.
Efforts are being made to accommodate smaller sizes. Conventionally, most semiconductor devices have been resin-molded, such as dual in-line packages (DIL) and flat packages (FP). Therefore, it is difficult to respond to the trend toward lighter, thinner, and shorter electronic devices due to the shape of these semiconductor devices.
半導体装置を最も小さく回路基板に実装する手
段として半導体素子をチツプ状で取扱う方法が各
種考案されている。代表的な方法の一つとして、
フリツプチツプがある。これは半導体素子チツプ
の電極部、すなわちアルミパツド上に金属薄膜と
ハンダメツキにより突起電極を設け、この半導体
素子チツプを回路基板上へフエイスダウンで実装
するものである。この突起電極はバンプと呼ば
れ、半導体素子チツプのアルミパツドを含む素子
全面にチタンやクロムのようなアルミと密着性の
良好な金属をエレクトロンビーム蒸着または抵抗
加熱蒸着法によって第一の薄膜を形成、さらに第
二の薄膜として銅、パラジユーム、白金、金など
の金属を先と同じ蒸着によって形成する。次にア
ルミパツド部以外をレジストコートし、先の金属
膜を電極としてスズと鉛の電気メツキを適当な高
さ（厚み）にメツキした後、レジストを剥離す
る。次にスズと鉛の部分にレジストをかけて、第
一および第二の金属膜をエツチングで除去し、レ
ジストを剥離した後、還元雰囲気中または空気中
でスズと鉛のメツキ層を溶触させハンダとする。
このときハンダの表面張力により半球状のいわゆ
るハンダバンプが形成される。このようにして作
られた半導体装置は回路基板にフエイスダウンに
よって載置、加熱することによって回路基板上の
電極へハンダ付けされ、電気的接続が成される。
この方法によれば蒸着法による薄膜形成、電気メ
ツキによるハンダ形成、フオトリソによるエツチ
ング等の複雑な工程を必要とすることと、回路基
板上の電極を十分なハンダ付け強度を得るためハ
ンダ量を多く必要とし、パツド間隔も200〜300ミ
クロンが必要となる。以上のような半導体装置の
製造が複雑であることによるコストアツプとパツ
ド間隔が規制されることによる半導体素子チツプ
上のパツド数の限定など多くの問題を有する。ま
た、フリツプチツプは回路基板上へハンダ付けに
よって実装するもので回路基板、例えば液晶パネ
ルの如き金属酸化物透明電極（ITO）上へ直接実
装する場合などは先にITOをハンダ付けできるよ
うにメタライズしておかなければならず液晶パネ
ルの製造においても複雑となり、パネルコストの
アツプとなる。 Various methods have been devised for handling semiconductor elements in the form of chips as a means of packaging semiconductor devices on circuit boards in the smallest size possible. As one of the typical methods,
There is a flip chip. In this method, a protruding electrode is provided on the electrode portion of a semiconductor element chip, that is, an aluminum pad, by a metal thin film and solder plating, and this semiconductor element chip is mounted face-down on a circuit board. This protruding electrode is called a bump, and a first thin film of a metal such as titanium or chromium that has good adhesion to aluminum is formed on the entire surface of the semiconductor chip, including the aluminum pad, by electron beam evaporation or resistance heating evaporation. Furthermore, a metal such as copper, palladium, platinum, or gold is formed as a second thin film by the same vapor deposition as before. Next, the area other than the aluminum pad part is coated with resist, and after electroplating with tin and lead to an appropriate height (thickness) using the previous metal film as an electrode, the resist is peeled off. Next, a resist is applied to the tin and lead parts, the first and second metal films are removed by etching, and after the resist is peeled off, the tin and lead plating layers are melted in a reducing atmosphere or in the air and soldered. shall be.
At this time, a hemispherical so-called solder bump is formed due to the surface tension of the solder. The semiconductor device manufactured in this manner is mounted face-down on a circuit board and heated to be soldered to the electrodes on the circuit board to establish an electrical connection.
This method requires complicated processes such as thin film formation by vapor deposition, solder formation by electroplating, and etching by photolithography, and requires a large amount of solder to obtain sufficient soldering strength for the electrodes on the circuit board. The pad spacing also needs to be 200 to 300 microns. There are many problems, such as an increase in cost due to the complexity of manufacturing the semiconductor device as described above, and a limitation on the number of pads on a semiconductor element chip due to restrictions on pad spacing. Additionally, flip chips are mounted on a circuit board by soldering, and when mounting directly on a circuit board, such as a metal oxide transparent electrode (ITO) such as a liquid crystal panel, first metalize the ITO so that it can be soldered. This complicates the manufacturing of liquid crystal panels and increases panel costs.
発明の目的
本発明はチツプ状で回路基板に最小面積で実装
すること、およびコストの低減を目的とする半導
体装置に関するものである。OBJECTS OF THE INVENTION The present invention relates to a chip-shaped semiconductor device that can be mounted on a circuit board with a minimum area and that aims to reduce costs.
発明の構成
上記目的を達成するために本発明の半導体装置
はアルミ電極パツド部に光硬化性樹脂と導電粉か
らなる第一の等方導電層と、この第一の等方導電
層上もしくは半導体素子チツプの一主面に熱可塑
性樹脂と導電粉からなる第二の異方性導電層を形
成したことを特徴とするものである。Structure of the Invention In order to achieve the above object, a semiconductor device of the present invention includes a first isotropic conductive layer made of a photocurable resin and conductive powder on an aluminum electrode pad portion, and a semiconductor device on the first isotropic conductive layer or a semiconductor device. The device is characterized in that a second anisotropic conductive layer made of a thermoplastic resin and conductive powder is formed on one main surface of the element chip.
実施例の説明
以下、本発明の半導体装置の実施例について説
明する。DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the semiconductor device of the present invention will be described.
本発明は半導体素子チツプのアルミ電極パツド
部のバンプの構造に係り、二層のそれぞれ異なる
特性を持つ合成樹脂系の導電材をバンプとするも
ので、第一の等方導電層は感光性を有する樹脂、
例えばエポキシアクリレートオリゴマー、アクリ
レートモノマーやアクリレート化されたポリイミ
ド樹脂等が使用できる。この樹脂に導電粉として
透光性を有する金属酸化物粉、例えば酸化スズ、
酸化インジユウム等の微粉末を前記樹脂100重量
部に30〜70重量部加え均質に分散させた塗料とす
る。この塗料を半導体素子チツプの全面にコーテ
イングし、予備乾燥した後、マスクを介しアルミ
パツド部を露光する。未露光部は現像して除去
し、アルミパツド上に形成された第一の導電層は
ポストキユアし十分硬化させる。この第一の等方
導電層は半導体素子チツプの電極と回路基板の電
極との電気的結合させる目的のもので比抵抗は低
くする必要がある。またこの第一の等方導電層は
通常のバンプと同様に半導体素子チツプ表面から
必要な高さ（５〜50ミクロン）に形成し、半導体
素子チツプをフエイスダウンで実装したとき半導
体素子にチツプ表面が回路基板に当たらないよう
にする目的もある。第二の異方性導電層は半導体
素子チツプの能動素子面全面に形成し、回路基板
上の電極との接着固定と垂直方向の導電性を得る
目的で使用される。この第二の異方性導電層は熱
可塑性樹脂、熱硬可性樹脂またはその併用でも本
発明の目的は達成されるが、信頼性、半導体素子
チツプ上に形成した二層のポツトライフなどから
熱可塑性樹脂が有効である。導電粉は第一の層と
異なり光を透過させる必要がなく粒子径は大きく
ても良い。この第二の異方性導電層の最も大きな
特徴は異方性の導電性を付与することにある。垂
直方向に導電性を有し、水平方向、すなわち、半
導体素子チツプの面方向は絶縁となるものであ
る。第１図で本発明の作用について説明する。第
１図は半導体素子チツプのアルミパツド部分の断
面を示し、シリコン基板からなる半導体素子チツ
プ１の上面に形成したアルミパツド部３はパツシ
ベーシヨン膜２で一部覆われていてアルミパツド
部で形成され、さらに全面に第二の異方性導電層
５が形成される。この第二の異方性導電層５の中
に導電粉６が点在している。以上の構成におい
て、この半導体素子チツプ１を回路基板へ実装し
たときの状態を第２図に示す。回路基板７上に形
成された電極８に半導体素子チツプ１を載置し加
圧加熱することによって第二の異方性導電層５の
樹脂がメルトし回路基板７の電極８に接着すると
同時に第二の異方性導電層５の中に点在する導電
粉６が半導体素子チツプ１の第一の等方性導電層
４と電極８の間に狭み込まれ半導体素子チツプ１
と回路基板７の電極８とが電気的、機械的に結合
する。しかも加圧されない部分の導電粉６は粒子
間に樹脂が介在しており完全な絶縁膜となる。 The present invention relates to the structure of a bump on an aluminum electrode pad of a semiconductor chip, and the bump is made of two layers of synthetic resin-based conductive material each having different properties, and the first isotropic conductive layer is photosensitive. resin having,
For example, epoxy acrylate oligomers, acrylate monomers, acrylated polyimide resins, etc. can be used. A metal oxide powder having translucency, such as tin oxide, is added to this resin as a conductive powder.
A paint is prepared by adding 30 to 70 parts by weight of fine powder such as indium oxide to 100 parts by weight of the resin and homogeneously dispersing it. This paint is coated over the entire surface of the semiconductor chip, and after preliminary drying, the aluminum pad portion is exposed to light through a mask. The unexposed areas are removed by development, and the first conductive layer formed on the aluminum pad is post-cured and sufficiently hardened. This first isotropic conductive layer is intended to electrically connect the electrodes of the semiconductor element chip and the electrodes of the circuit board, and must have a low specific resistance. In addition, this first isotropic conductive layer is formed at the required height (5 to 50 microns) from the surface of the semiconductor element chip in the same way as a normal bump, and when the semiconductor element chip is mounted face-down, the surface of the semiconductor element is It also has the purpose of preventing it from hitting the circuit board. The second anisotropic conductive layer is formed on the entire surface of the active element of the semiconductor element chip, and is used for the purpose of adhesion and fixation with electrodes on the circuit board and to obtain vertical conductivity. Although the object of the present invention can be achieved by forming this second anisotropic conductive layer using thermoplastic resin, thermosetting resin, or a combination thereof, there are concerns about reliability and the pot life of the two layers formed on the semiconductor chip. Plastic resin is effective. Unlike the first layer, the conductive powder does not need to transmit light and may have a large particle size. The most significant feature of this second anisotropic conductive layer is that it provides anisotropic conductivity. It has conductivity in the vertical direction and is insulating in the horizontal direction, that is, in the surface direction of the semiconductor chip. The operation of the present invention will be explained with reference to FIG. FIG. 1 shows a cross section of an aluminum pad part of a semiconductor element chip. An aluminum pad part 3 formed on the upper surface of a semiconductor element chip 1 made of a silicon substrate is partially covered with a passivation film 2, which is formed of an aluminum pad part, and then the entire surface is covered with an aluminum pad part. A second anisotropic conductive layer 5 is formed thereon. Conductive powder 6 is scattered within this second anisotropic conductive layer 5. FIG. 2 shows a state in which the semiconductor element chip 1 having the above structure is mounted on a circuit board. By placing the semiconductor element chip 1 on the electrode 8 formed on the circuit board 7 and heating it under pressure, the resin of the second anisotropic conductive layer 5 melts and adheres to the electrode 8 of the circuit board 7, and at the same time The conductive powder 6 scattered in the second anisotropic conductive layer 5 is sandwiched between the first isotropic conductive layer 4 and the electrode 8 of the semiconductor element chip 1.
and the electrode 8 of the circuit board 7 are electrically and mechanically coupled. Furthermore, the portions of the conductive powder 6 that are not pressurized have resin interposed between the particles, forming a complete insulating film.
次に本発明の具体的な実施例について説明す
る。 Next, specific examples of the present invention will be described.
実施例
第一の等方導電層４の材料として以下の配合で
塗料化した。Example A paint was prepared using the following formulation as the material for the first isotropic conductive layer 4.
感光性樹脂〔東レ（株）の商品名：フォトニー
ス〕 ……100重量部
導電粉〔三菱金属（株）酸化スズ粉〕……
30重量部
溶剤〔Ｎ−メチル−２−ピロリドン関東化学〕
……５重量部
第二の異方性導電層５の材料として以下の配合
で塗料化した。Photosensitive resin [Product name of Toray Industries, Inc.: Photonice] ...100 parts by weight Conductive powder [Mitsubishi Metals Co., Ltd. tin oxide powder] ...
30 parts by weight of solvent [N-methyl-2-pyrrolidone Kanto Chemical]
...5 parts by weight A paint was prepared as a material for the second anisotropic conductive layer 5 using the following formulation.
ポリエステル樹脂〔東洋紡（株）の商品名：バイ
ロン〕 ……100重量部
導電粉〔三菱金属（株）酸化スズ粉〕
……３重量部
溶剤〔MEK 関東化学製〕 ……50重量部
それぞれの塗料をCMOSが形成された４イン
チウエハー上にスピナーでコーテイングし、第一
の等方導電層４は厚みが10ミクロンになるよう形
成し、80℃60分のポストキユア後アルミパツド部
のみ紫外線（120W／cm）で30秒露光して、現像
液にて未露光部を除去した。さらにポストキユア
として200℃30分、300℃30分、400℃30分のステ
ツプでキユアし第一の特方導電層４とした。さら
に第二の異方性導電層５として同様にスピナーで
厚みが10ミクロンになるように全面に塗布し、
110℃60分で乾燥させた。このウエハーを所定の
チツプ寸法にダイシングし完成品を得た。この半
導体素子チツプ１を回路基板（ガラス上に形成さ
れたITO回路基板）７に載置し半導体素子チツプ
１の裏面から150℃加熱ツールと30Kg／cm2の圧力
で押え接続させた。その後、回路基板７の電気的
特性をチエツクしたところ完全に所定の動作から
得られることを確認した。Polyester resin [Toyobo Co., Ltd. product name: Vylon] ...100 parts by weight conductive powder [Mitsubishi Metals Co., Ltd. tin oxide powder]
...3 parts by weight of solvent [MEK manufactured by Kanto Kagaku] ...50 parts by weight Each paint was coated on a 4-inch wafer on which CMOS was formed using a spinner, and the first isotropic conductive layer 4 was made to have a thickness of 10 microns. After post-curing at 80° C. for 60 minutes, only the aluminum pad portion was exposed to ultraviolet light (120 W/cm) for 30 seconds, and the unexposed portion was removed using a developer. Furthermore, the first special conductive layer 4 was cured in steps of 200°C for 30 minutes, 300°C for 30 minutes, and 400°C for 30 minutes as a post-cure. Furthermore, a second anisotropic conductive layer 5 was similarly applied to the entire surface using a spinner to a thickness of 10 microns.
It was dried at 110°C for 60 minutes. This wafer was diced into a predetermined chip size to obtain a finished product. This semiconductor element chip 1 was placed on a circuit board (ITO circuit board formed on glass) 7, and connected from the back side of the semiconductor element chip 1 to a 150° C. heating tool using a pressure of 30 kg/cm 2 . Thereafter, when the electrical characteristics of the circuit board 7 were checked, it was confirmed that the electrical characteristics could be obtained completely from the predetermined operation.
発明の効果
本発明はそれぞれ異なった二種類の導電層をバ
ンプとして半導体素子に形成することによって従
来のフリツプチツプのような複雑な工程を必要と
せず、しかも簡単な設備で製造が可能となった。
これはチツプコストの大巾な低減と従来半導体メ
ーカーしかできなかったバンプ技術を半導体ユー
ザー側でも作成できるようになることなど大きな
特徴を有するものである。また、本発明の二種類
の導電層はそれぞれの機能を有し、特に第二の異
方性導電層は、半導体素子チツプ全面に塗布され
ており、接着と垂直方向の導通を得るばかりでな
く、従来この種半導体素子チップで回路基板に実
装した場合は十分な保護が必要で特に湿度に対す
る保護は非常に困難とされていたが、この第二の
異方性導電層によってかなりの保護効果が達成さ
れる。以上のように本発明はチツプコストの大巾
な低減と、軽薄短小の市場ニーズにマツチングす
る最少の実装を可能とするものである。またユー
ザー側で製造することも可能となり今後の半導体
産業に寄与するものである。Effects of the Invention By forming two different types of conductive layers as bumps on a semiconductor element, the present invention does not require complicated processes unlike conventional flip chips, and can be manufactured using simple equipment.
This has major features such as a drastic reduction in chip cost and the ability for semiconductor users to create bump technology that was previously only available to semiconductor manufacturers. In addition, the two types of conductive layers of the present invention have their respective functions, and in particular, the second anisotropic conductive layer is coated on the entire surface of the semiconductor chip, which not only provides adhesion and vertical conduction. Conventionally, when this type of semiconductor element chip is mounted on a circuit board, sufficient protection is required, and protection against humidity in particular is considered to be extremely difficult, but this second anisotropic conductive layer provides a considerable protection effect. achieved. As described above, the present invention enables a significant reduction in chip cost and a minimum number of implementations that meet the market needs for lightness, thinness, shortness, and smallness. Furthermore, it will also be possible to manufacture it on the user side, which will contribute to the future semiconductor industry.
第１図は本発明の半導体装置の一実施例を示す
断面図、第２図は同半導体装置を実装した状態の
断面図である。
１……半導体素子チツプ、２……パツシベーシ
ヨン膜、３……アルミパツド、４……第一の等方
性導電層、５……第二の異方性導電層、６……導
電粉、７……回路基板、８……電極。
FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention, and FIG. 2 is a sectional view of the semiconductor device in a mounted state. DESCRIPTION OF SYMBOLS 1... Semiconductor element chip, 2... Passivation film, 3... Aluminum pad, 4... First isotropic conductive layer, 5... Second anisotropic conductive layer, 6... Conductive powder, 7... ...Circuit board, 8...electrode.
Claims (1)
性樹脂と導電粉からなる第一の等方導電層と、該
第一の導電層上、もしくは半導体素子チツプの一
主面に熱可塑性樹脂と導電粉からなる第二の異方
性導電層を形成したことを特徴とする半導体装
置。 ２ 導電粉が金属酸化物であることを特徴とする
特許請求の範囲第１項記載の半導体装置。[Scope of Claims] 1. A first isotropic conductive layer made of a photocurable resin and conductive powder on the electrode pad portion of the semiconductor element chip, and a layer on the first conductive layer or on one main surface of the semiconductor element chip. A semiconductor device characterized in that a second anisotropic conductive layer made of a thermoplastic resin and conductive powder is formed on the semiconductor device. 2. The semiconductor device according to claim 1, wherein the conductive powder is a metal oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22474483A JPS60116157A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22474483A JPS60116157A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60116157A JPS60116157A (en) | 1985-06-22 |
| JPH031828B2 true JPH031828B2 (en) | 1991-01-11 |
Family
ID=16818554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22474483A Granted JPS60116157A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60116157A (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6243138A (en) * | 1985-08-21 | 1987-02-25 | Seiko Instr & Electronics Ltd | Ic mounting structure of liquid crystal display apparatus |
| JPS6347942A (en) * | 1986-08-18 | 1988-02-29 | Fuji Xerox Co Ltd | Semiconductor device |
| EP0265077A3 (en) * | 1986-09-25 | 1989-03-08 | Sheldahl, Inc. | An anisotropic adhesive for bonding electrical components |
| FR2618254B1 (en) * | 1987-07-16 | 1990-01-05 | Thomson Semiconducteurs | METHOD AND STRUCTURE FOR TAKING CONTACT ON INTEGRATED CIRCUIT PLOTS. |
| JPH01132138A (en) * | 1987-08-13 | 1989-05-24 | Shin Etsu Polymer Co Ltd | Electrical connection method of ic chip, material for resin bump formation and liquid crystal display |
| JP2666299B2 (en) * | 1987-10-08 | 1997-10-22 | ソニー株式会社 | Solid-state imaging device |
| JPH0234951A (en) * | 1988-04-20 | 1990-02-05 | Seiko Epson Corp | Mounting structure for semiconductor device |
| JPH02199847A (en) * | 1989-01-27 | 1990-08-08 | Shin Etsu Polymer Co Ltd | Mounting of ic chip |
| US5136365A (en) * | 1990-09-27 | 1992-08-04 | Motorola, Inc. | Anisotropic conductive adhesive and encapsulant material |
| KR100218996B1 (en) * | 1995-03-24 | 1999-09-01 | 모기 쥰이찌 | Semiconductor device |
| CA2156941A1 (en) * | 1995-08-21 | 1997-02-22 | Jonathan H. Orchard-Webb | Method of making electrical connections to integrated circuit |
| JPH09199506A (en) * | 1995-11-15 | 1997-07-31 | Citizen Watch Co Ltd | Method for forming bump on semiconductor chip |
| US6396712B1 (en) * | 1998-02-12 | 2002-05-28 | Rose Research, L.L.C. | Method and apparatus for coupling circuit components |
| JP4761164B2 (en) * | 2006-03-31 | 2011-08-31 | ブラザー工業株式会社 | Connection structure and component mounting board |
-
1983
- 1983-11-29 JP JP22474483A patent/JPS60116157A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60116157A (en) | 1985-06-22 |
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