JPH07183327A - Semiconductor chip, formation of terminal thereon and bonding method thereof - Google Patents

Abstract

PURPOSE:To remarkably improve the solderability of input/output terminals of a semiconductor chip, its adhesion to boards and bondability, and make it possible to mount the semiconductor chip directly on a board by wireless bonding without forming any solder bump. CONSTITUTION:The input/output terminals of a semiconductor chip are formed by forming a nickel thin layer 3 and a noble metal thin layer 4 on a base metal layer of aluminum, for example, in this order. The surface of the base metal layer 2 is treated with palladium solution, such as palladium chloride solution, and thereafter the nickel thin layer 3 and the noble metal thin layer 4 are individually formed by electroless plating.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip having an input / output terminal with improved bondability and corrosion resistance. The present invention also relates to a method of forming such a terminal of a semiconductor chip and a method of joining with an electrode pad of a wiring board.

[0002]

2. Description of the Related Art Conventionally, as a method for mounting a semiconductor chip on a substrate, a wire bonding method, a wireless bonding method such as a gold bump method or a solder bump method has been adopted. High-density mounting of MCM (Multi-Chip M
The use of the solder bump method, which can reduce the mounting area of the semiconductor chip in the production of the module) and is advantageous in terms of mounting cost, is increasing.

By the way, the input / output terminals of the semiconductor chip are
Generally, it is composed of an aluminum-based metal such as aluminum or an aluminum alloy. However,
Since aluminum-based metal has low solderability, even if solder bumps are directly formed on the aluminum-based metal that constitutes the input / output terminals of the semiconductor chip and mounted on the board, the adhesiveness and bondability to the board are sufficient. Cannot be improved. In addition, the terminal made of only aluminum metal has low corrosion resistance. Therefore, the method of directly forming the solder bump on the terminal made of an aluminum-based metal is not suitable for manufacturing the MCM.

Therefore, as a method of forming a solder bump on an input / output terminal made of an aluminum-based metal, first, a barrier metal such as nickel, copper, or chromium is formed on the input / output terminal by a vacuum method, and then a barrier metal is formed thereon. In addition, a solder bump of several tens of μm is formed by a vacuum method.

[0005]

However, after the barrier metal is formed on the input / output terminals of the semiconductor chip by the vacuum method,
Further, in order to form the solder bumps by the vacuum method, a large-scale manufacturing facility is originally required, and the productivity is lowered, resulting in a problem that the mounting cost is increased. Further, when a plurality of bumps are formed, the height direction of the bumps tends to be non-uniform, which makes it difficult to secure bonding reliability for all the bumps when simultaneously connecting the plurality of bumps. There was also.

The present invention is intended to solve the problems of the prior art as described above, and greatly improves the solderability of the input / output terminals of the semiconductor chip, the adhesiveness to the substrate, and the bondability to form solder bumps. It is an object of the present invention to allow a semiconductor chip to be directly mounted on a substrate by wireless bonding without doing so, thereby enabling the semiconductor chip to be mounted on the substrate at a low cost and a high density.

[0007]

The inventor of the present invention first forms a thin nickel layer on an input / output terminal of a semiconductor chip, in particular, a terminal made of an aluminum-based metal, by an electroless plating method, and then the nickel thin layer. Forming a noble metal thin layer on the layer by electroless plating or the like dramatically improves solderability of terminals, adhesiveness to a substrate, bondability and corrosion resistance, and finds that the above objects can be achieved, and the present invention is achieved. It came to completion.

That is, the present invention provides a semiconductor chip characterized in that the input / output terminal comprises a base metal layer, and a nickel thin layer and a noble metal thin layer sequentially laminated thereon.

Further, according to the present invention, as a method of forming the input / output terminals of such a semiconductor chip, a thin nickel layer is formed by electroless plating on a base metal layer constituting the input / output terminals of the semiconductor chip. And a method of forming a precious metal thin layer on the nickel thin layer by an electroless plating method.

Further, as a method of mounting a semiconductor chip having such input / output terminals on a substrate, the input / output terminals of the semiconductor chip are overlapped with electrode pads of a wiring board on which the semiconductor chip is to be mounted, and they are overlapped. A method of joining the two by heating the parts is provided.

The present invention will be described in detail below.

In the semiconductor chip of the present invention, as shown in FIG. 1, a nickel thin layer 3 and a noble metal thin layer 4 are laminated on a base metal layer 2 which constitutes an input / output terminal of a silicon substrate 1 of the semiconductor chip. It is characterized by being. here,
A passivation layer 5 is formed on the side surface of the base metal layer 2.

As the base metal layer 2 constituting the input / output terminal, an aluminum-based metal such as aluminum or aluminum alloy conventionally used as a terminal material of a semiconductor chip can be preferably used.

The thickness of the nickel thin layer 3 on the base metal layer 2 varies depending on the heating means used for mounting the semiconductor chip on the wiring board, but is about 0.3 to 20.
μm, preferably about 1 to 10 μm. The thin nickel layer 3 may be formed of nickel alone, or may be formed by mixing other elements such as phosphorus, boron, cobalt, and palladium in addition to nickel.

Such a nickel thin layer 3 can be preferably formed by an electroless plating method. As a result, it becomes easy to form a thin nickel layer with a predetermined thickness on the plurality of input / output terminals without variation.

The electroless plating solution used in the electroless plating method and the plating conditions can be appropriately selected. For example, as a nickel plating bath, nickel sulfate 1 to 100
g / l, preferably 3 to 20 g / l, potassium acetate or potassium citrate 0.1 to 100 g / l, preferably 3
~ 20 g / l, and potassium hypophosphite 1-50 g /
1, preferably 3 to 30 g / l of nickel sulfate aqueous solution is used, pH 3 to 10, preferably pH 4 to 8,
The nickel thin layer 3 can be preferably formed by electroless plating under the condition that the bath temperature is 50 to 100 ° C, preferably 85 to 95 ° C. Further, 0.01 to 10 g / l, preferably 0.05 to 5 g / l of lead acetate is added to such a nickel plating solution in order to form a good plating layer.

Prior to the electroless nickel plating, the surface of the base metal layer 2 may be washed with an etching solution as needed to enhance the adhesion between the nickel thin layer 3 and the base metal layer 2, and palladium may be added. It is particularly preferable to perform the surface treatment with an aqueous solution.

In this case, the etchant used is 1 to 5% HNO _{3 in} terms of the adhesion between the input / output terminals made of an aluminum-based metal and the nickel thin layer and the mutual diffusion of both layers.
It is preferred to use an aqueous solution.

Further, the aqueous palladium solution for the undercoating has a composition which can selectively deposit palladium on the fine pattern base metal layer 2 and which does not etch or contaminate the semiconductor chip. To use. For example, a preferable palladium aqueous solution is 0.01 to 10 g / l of palladium chloride, preferably 0.1 to 3 g / l, and 0.01 to 50 ml / 35% hydrochloric acid.
An example is an aqueous solution of paradimium chloride consisting of 1, preferably 0.1 to 10 ml / l and potassium citrate, 1 to 100 g / l, preferably 3 to 50 g / l. Moreover, such a palladium chloride aqueous solution has a pH of 1 to 1.
1, preferably pH 3 to 9 and temperature 0 to 70 ° C., preferably 5 to 50 ° C.

In addition to the above-mentioned aqueous paradymium chloride solution, an organic acid palladium solution such as palladium citrate, palladium malate, palladium succinate, etc. can be used as the aqueous paradimium solution.

As the noble metal thin layer 4 formed on the nickel thin layer 3, a thin layer made of gold, palladium, platinum or the like can be used. In particular, a thin gold layer is preferable from the viewpoint of corrosion resistance, and Pd-Pb-P and Pd-Pb- from the viewpoint of solderability, stress, melting point, and diffusibility.
B, Pd-Pb-In, Pd-Pb-Sn-P, Pd-
Pb-Sn-B, Pd-Sn-P, Pd-Sn-B, P
d-Sn-In, Ni-Pd, Pd-Ni-Sn, Pd
It is preferable to form -Pb-In-P or Pd-Pb-Sn-In-P.

The thickness of the noble metal thin layer 4 varies depending on the heating means used for mounting the semiconductor chip on the wiring board, but is about 0.005 to 50 μm, preferably about 0.01.
˜30 μm, more preferably about 0.01 to 5 μm.

Such a noble metal thin layer 4 can be preferably formed by an electroless plating method, and the electroless plating solution used and the plating conditions can be appropriately selected. For example, as a gold plating solution, KAu (CN) ₂₀ .
1 to 30 g / l, preferably 0.5 to 10 g / l, potassium or ammonium citrate 0.5 to 200 g / l
1, preferably 5 to 50 g / l, and optionally KO
H 0.1 to 20 g / l, preferably 0.5 to 5 g / l or ammonium hypophosphite 1 to 100 g / l, preferably an aqueous solution of potassium gold cyanide consisting of 3 to 50 g / l, pH 2 to 10 , Preferably pH 3-8, bath temperature 3
The noble metal thin layer 4 can be preferably formed by electroless plating under the conditions of 0 to 100 ° C., preferably 60 to 95 ° C.

In the semiconductor chip of the present invention in which the terminals are thus formed, the input / output terminals are superposed on the electrode pads of the wiring board on which the semiconductor chip is to be mounted, and the overlapping portions are infrared rays and ultrasonic waves. It is possible to bond the input / output terminal of the semiconductor chip and the electrode pad of the wiring board by heating by heating means such as a heating element, and preferably applying pressure simultaneously. For example, when a solder layer is formed on the surface of the electrode pad of the wiring board, the input / output terminals of the semiconductor chip are directly overlapped with the solder layer to form about 200 to 3
It can be directly mounted on the wiring board by thermocompression bonding at a temperature of 00 ° C.

[0025]

In the semiconductor chip of the present invention, its input / output terminals are
It consists of a base metal layer such as aluminum and a nickel thin layer and a noble metal thin layer that are sequentially laminated on top of it with good adhesion, so that the solderability of terminals, adhesion to substrates, bondability and corrosion resistance are dramatically improved. It will be improved. In particular, the base metal layer of the input / output terminal is preliminarily treated with an aqueous palladium solution, a thin nickel layer is formed thereon by electroless plating, and Pd is further formed thereon by electroless plating.
-Pb-P, Pd-Pb-B, Pd-Pb-In, Pd
-Pb-Sn-P, Pd-Pb-Sn-B, Pd-Sn
-P, Pd-Sn-B, Pd-Sn-In, Ni-P
d, Ni-Sn, Pd-Pb-In-P or Pd-Pb
When a noble metal thin layer such as -Sn-In-P is formed,
The adhesion of each layer on the input / output terminals is improved, resulting in a highly reliable terminal. Therefore, it is possible to directly mount the semiconductor bare chip on the wiring board without wires. Therefore, by using the semiconductor chip of the present invention, the productivity of MCM can be greatly improved.

Further, in this case, since the nickel thin layer and the noble metal thin layer can be uniformly formed to have a predetermined thickness on the plurality of input / output terminals, the connection reliability of all the plurality of terminals can be improved in the manufacture of the MCM. Can be secured.

[0027]

【Example】

Example 1 An aluminum terminal having a thickness of 2 μm, which is an input / output terminal of a C-MOS, was first washed with a neutral solvent at 30 ° C. for 2 minutes and then with pure water. Further, in order to remove aluminum oxide, it was treated with 1% HNO ₃ for 30 seconds and washed with pure water.

Next, as a palladium undercoating liquid, palladium chloride 0.1 g / l, 35% hydrochloric acid 0.1 ml / l
And an aqueous solution of palladium chloride containing 2 g / l of potassium citrate are prepared.
H4.2, the surface treatment was performed by immersing at 10 ° C. for 40 seconds. By this base treatment, an extremely thin palladium film was formed on the surface of the aluminum terminal.

Next, as an electroless nickel plating solution, nickel sulfate 10 g / l, potassium citrate 20 g / l,
An aqueous solution of nickel sulfate containing 10 g / l of sodium hypophosphite was prepared, and this aqueous solution was used at a pH of 5.0 at 90 ° C. for an aluminum terminal subjected to a base treatment.
Electroless nickel plating was performed under the condition of minutes. As a result, an electroless nickel plating layer having a thickness of 5 μm was formed.

Next, as an electroless gold plating solution, KAu is used.
(CN) ₂ 10 g / l, potassium citrate 10 g / l and KOH 1 g / l potassium gold cyanide aqueous solution was prepared, and this aqueous solution was used for an aluminum terminal having an electroless nickel plating layer formed on its surface. On the other hand, pH
Gold plating was performed under the conditions of 5 and 90 ° C. for 10 minutes.
As a result, an electroless gold plating layer having a thickness of 0.1 μm was formed. This was washed with pure water and dried to obtain the semiconductor chip of the present invention.

The semiconductor chip thus obtained is C
It was mounted on a wiring board by OB technology. That is, the input / output terminal portions of the semiconductor chip were aligned with the solder electrode pads of the rigid glass epoxy wiring board on which the semiconductor chip is to be mounted, and the two were joined by thermocompression bonding at 260 ° C. As a result, the connection space required for mounting the semiconductor chip is about 1/10 of that when the same semiconductor chip is mounted on the wiring board by wire bonding, and the mounting cost is also about 1
Since the wiring distance required for mounting the semiconductor chip is shortened, the response speed can be shortened to about 1/3.

Example 2 As in Example 1, the aluminum terminal of the C-MOS was
A semiconductor chip of the present invention was obtained by performing a palladium chloride undercoating treatment and further laminating an electroless nickel plating layer having a thickness of 5 μm and an electroless gold plating layer having a thickness of 0.1 μm.

Next, the obtained semiconductor chip is placed on a flexible wiring board on which solder electrode pads are formed in advance 260
Bare chip bonding was performed by thermocompression bonding at ℃. As a result, the mounting cost is about 1/50 of that when the same semiconductor chip is mounted on the wiring board by the solder bump method.
The time required was also reduced to about 1/100. Further, the adhesiveness and conductivity of the semiconductor chip mounted on the wiring board were excellent as in the case of mounting by the solder bump method.

Example 3 As in Example 1, the aluminum terminal of the C-MOS was
Palladium chloride base treatment was performed, and an electroless nickel plating layer having a thickness of 3 μm was further formed. Next, in order to form a palladium alloy layer as a noble metal thin layer, palladium chloride plating bath was used as palladium chloride 4 g / l, lead chloride 1
0 g / l, stannous chloride 10 g / l, potassium citrate 5
An aqueous solution containing 0 g / l and 50 g / l of sodium hypophosphite was prepared, and citric acid was further added to this to obtain a pH of 4.
Adjusted to 5. Using this plating bath, electroless plating is performed at 80 ° C. for 2 hours, and a palladium alloy layer having a thickness of 10 μm (alloy composition: Pd 50%, Pb 30%, Sn 15%, P
5%) was formed.

This C-MOS chip was mounted on a ceramic wiring board by COB technology. As a result, the mounting cost is reduced to about 1/15, and the time required for mounting including bump formation is reduced to 1/100, compared to the case where the same semiconductor chip is mounted by forming solder bumps. I was able to. Further, the C-MOS chip of the example after being mounted on the ceramic wiring board had excellent adhesion and conductivity.

[0036]

According to the semiconductor chip of the present invention, the solderability of the input / output terminals, the adhesiveness to the wiring substrate, and the bonding property are greatly improved, and the semiconductor chip is wireless bonded to the substrate without forming solder bumps. It is possible to implement directly at low cost.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip of the present invention.

[Explanation of symbols]

 1 Silicon Substrate 2 Base Metal Layer 3 Nickel Thin Layer 4 Noble Metal Thin Layer 5 Passivation Layer

Claims (8)

[Claims] 1. A semiconductor chip, wherein the input / output terminal comprises a base metal layer and a nickel thin layer and a noble metal thin layer sequentially laminated thereon. 2. The semiconductor chip according to claim 1, wherein the base metal layer is made of an aluminum-based metal. 3. The semiconductor chip according to claim 1, wherein the surface of the base metal layer is surface-treated with an aqueous palladium solution. 4. The thin precious metal layer is Au, Pt, Pd, Pd.
-Pb-P, Pd-Pb-B, Pd-Pb-In, Pd
-Pb-Sn-P, Pd-Pb-Sn-B, Pd-Sn
-P, Pd-Sn-B, Pd-Sn-In, Ni-P
d, Pd-Ni-Sn, Pd-Pb-In-P or Pd
The semiconductor chip according to claim 1, comprising -Pb-Sn-In-P. 5. A thin nickel layer is formed by an electroless plating method on a base metal layer constituting an input / output terminal of a semiconductor chip, and a noble metal thin layer is further formed on the nickel thin layer by an electroless plating method. The method for forming a terminal of a semiconductor chip according to any one of claims 1 to 4, wherein: 6. The method according to claim 5, wherein after the surface of the base metal layer is pretreated with an aqueous palladium solution, a thin nickel layer is formed thereon by electroless plating. 7. The forming method according to claim 6, wherein the surface of the base metal layer is washed with an etching solution, and then ground treatment is performed with an aqueous palladium solution. 8. An input / output terminal of the semiconductor chip according to claim 1 is overlapped with an electrode pad of a wiring board on which the semiconductor chip is to be mounted, and the overlapped portion is heated so that both of them are combined. A method for joining semiconductor chips, which comprises joining.