JP2570123B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP2570123B2
JP2570123B2 JP5195544A JP19554493A JP2570123B2 JP 2570123 B2 JP2570123 B2 JP 2570123B2 JP 5195544 A JP5195544 A JP 5195544A JP 19554493 A JP19554493 A JP 19554493A JP 2570123 B2 JP2570123 B2 JP 2570123B2
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor element
resin
wire
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5195544A
Other languages
Japanese (ja)
Other versions
JPH0729931A (en
Inventor
浩樹 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5195544A priority Critical patent/JP2570123B2/en
Publication of JPH0729931A publication Critical patent/JPH0729931A/en
Application granted granted Critical
Publication of JP2570123B2 publication Critical patent/JP2570123B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
にワイヤーボンディングによって電気的に接続を行う薄
型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a thin semiconductor device electrically connected by wire bonding.

【０００２】[0002]

【従来の技術】従来の半導体装置において、半導体素子
と外部電極とを電気的に接合させる方法は、ＴＡＢ方
式、ワイヤーボンディング方式等がある。ＴＡＢ方式に
よる場合は、半導体素子上に設けられたバンプとＴＡＢ
テープのインナーリードを接合することで導通を実現さ
せている。ワイヤーボンディング方式による半導体装置
には、図５、図６に示すものがある。図５においてＴＡ
Ｂテープ７は、デバイスホールの片側をＩＣ固定用接着
材層９を介して、シート８で覆われている。半導体素子
１は、デバイスホールの中央にダイボンディングされ、
Ａｕワイヤー２でワイヤーボンディングされている。ま
た、ＴＡＢテープ７には、導体パターン固定接着層１０
導体パターン１５を有している。そして、移送成型法に
より、樹脂封止されている。さらに別の例である図６に
おいて、ＴＡＢテープ７は凹型に成型されており、凹部
は中央に半導体素子１を固着し、Ａｕワイヤー２でワイ
ヤーボンディングされている。封止樹脂３は凹部及びそ
の周辺をポッティング法により樹脂封止している。2. Description of the Related Art In a conventional semiconductor device, a method for electrically connecting a semiconductor element to an external electrode includes a TAB method, a wire bonding method, and the like. In the case of the TAB method, the bump provided on the semiconductor element and the TAB
Conduction is realized by joining the inner leads of the tape. Semiconductor devices using the wire bonding method include those shown in FIGS. In FIG. 5, TA
The B tape 7 has one side of the device hole covered with a sheet 8 via an IC fixing adhesive layer 9. The semiconductor element 1 is die-bonded to the center of the device hole,
Wire bonding is performed with Au wire 2. Further, the TAB tape 7 includes a conductor pattern fixing adhesive layer 10.
It has a conductor pattern 15. And it is resin-sealed by the transfer molding method. In FIG. 6, which is another example, the TAB tape 7 is formed in a concave shape, and the concave portion fixes the semiconductor element 1 at the center and is wire-bonded with the Au wire 2. The sealing resin 3 seals the concave portion and its periphery with a potting method.

【０００３】[0003]

【発明が解決しようとする課題】この従来のＴＡＢ方式
による半導体装置では、半導体素子上、あるいはインナ
ーリード部に、バンプを形成しなければならず、そのた
めには、高度な技術が必要であり、高価な設備を導入し
なければならない。図５、図６に示すワイヤーボンディ
ング方式による半導体装置は、技術的に容易で、高価な
設備も必要としない。しかし、図５に示す半導体装置で
は、移送成型法により樹脂封止を行っており、その封止
樹脂には、成型完了後、成型用金型から封止樹脂が離型
しやすい様にワックス等の離型材が添加されている。そ
のため封止樹脂と半導体素子、Ａｕワイヤー、外部電極
との密着力が低下し、耐湿性試験において短時間で腐食
がおきやすい。また図６に示す半導体装置では凹部を熱
プレスによって成型しており、ＴＡＢテープの導体パタ
ーンの近傍まで熱プレスにより凹形に成型される為、導
体パターンの位置精度を一定の範囲内に保つのが困難で
ある。また、熱プレスにより凹形に成型されたＴＡＢテ
ープの底面は、わん曲した形状になりやすく、ダイボン
ディング、ワイヤーボンディング性が劣化しやすいとい
う欠点を有している。In the conventional TAB type semiconductor device, bumps must be formed on a semiconductor element or an inner lead portion, and for this purpose, advanced technology is required. Expensive equipment must be introduced. The semiconductor device using the wire bonding method shown in FIGS. 5 and 6 is technically easy and does not require expensive equipment. However, in the semiconductor device shown in FIG. 5, resin sealing is performed by a transfer molding method, and the sealing resin is made of wax or the like after the completion of molding so that the sealing resin is easily released from the molding die. Release material is added. Therefore, the adhesive strength between the sealing resin and the semiconductor element, the Au wire, and the external electrode is reduced, and corrosion is likely to occur in a short time in the moisture resistance test. In the semiconductor device shown in FIG. 6, the concave portion is formed by hot pressing, and the concave portion is formed by hot pressing up to the vicinity of the conductor pattern of the TAB tape, so that the positional accuracy of the conductor pattern is kept within a certain range. Is difficult. Further, the bottom surface of a TAB tape formed into a concave shape by hot pressing tends to have a curved shape, and has a disadvantage that die bonding and wire bonding properties are easily deteriorated.

【０００４】[0004]

【課題を解決するための手段】本発明の半導体装置は、
有機系絶縁性基板上に搭載された半導体素子と、前記有
機系絶縁性基板に貼付され、ＴＡＢテープを主構成部材
とする外部電極と、前記半導体素子の電極部と前記外部
電極とをボンディングするＡｕワイヤーとを含む半導体
装置であって、少なくとも前記半導体素子と前記Ａｕワ
イヤーとがスクリーン印刷樹脂部材で樹脂封止されてい
ることを特徴とするものである。また、有機系絶縁性基
板の表面に絶縁ペーストを塗付し、Ｐｄメッキ付ＴＡＢ
テープを貼り付け、また半導体素子をボンディングし、
次いで半導体素子の電極部とＰｄメッキ付一層ＴＡＢの
導体パターンとをＡｕワイヤーでボンディングし、これ
をスクリーン印刷によって樹脂封止することを特徴とす
る上記の半導体装置の製造方法である。According to the present invention, there is provided a semiconductor device comprising:
A semiconductor element mounted on an organic insulating substrate, an external electrode attached to the organic insulating substrate and having a TAB tape as a main component, and bonding an electrode portion of the semiconductor element to the external electrode; A semiconductor device including an Au wire, wherein at least the semiconductor element and the Au wire are resin-sealed with a screen printing resin member. An insulating paste is applied to the surface of an organic insulating substrate, and TAB with Pd plating is applied.
Paste the tape, bond the semiconductor element,
Then, the electrode portion of the semiconductor element and the conductor pattern of the Pd-plated one-layer TAB are bonded with Au wires, and this is resin-sealed by screen printing.

【０００５】[0005]

【作用】本発明においては、有機系絶縁性基板上に搭載
された半導体基板と有機系絶縁性基板に貼付されＴＡＢ
テープを主構成部材とする外部電極と半導体基板と外部
電極とをボンディングするＡｕワイヤーとを含む半導体
装置で、少なくとも前記半導体素子と前記ワイヤーとが
スクリーン印刷樹脂部材で樹脂封止されているもので、
薄型にでき、また、離型剤の添加を必要とせず、封止樹
脂と半導体素子、ワイヤー、リードとの密着力が低下す
ることもないので、高密着となり、高い耐湿性をえるこ
とができるものである。具体的には、半導体素子と半導
体素子を固着するための、絶縁ペーストを塗布した有機
系絶縁性基板に、半導体素子を囲む様に固着された、パ
ラジウムメッキ付一層ＴＡＢと、Ａｕワイヤーボンディ
ングにより電気的に接続された、半導体素子とパラジウ
ムメッキ付一層ＴＡＢをスクリーン印刷法により、樹脂
封止した樹脂成型部材を備えているので、薄型にでき、
また、離型剤の添加を必要とせず、封止樹脂と半導体素
子、Ａｕワイヤー、リードとの密着力が低下することも
ないので、高密着となり、高い耐湿性をえることができ
るものである。According to the present invention, a semiconductor substrate mounted on an organic insulating substrate and a TAB attached to the organic insulating substrate are attached.
A semiconductor device including an external electrode having a tape as a main component, and an Au wire for bonding a semiconductor substrate and an external electrode, wherein at least the semiconductor element and the wire are resin-sealed by a screen printing resin member. ,
It can be made thin, does not require the addition of a release agent, and does not reduce the adhesive force between the sealing resin and the semiconductor element, wire, and lead, so that high adhesion and high moisture resistance can be obtained. Things. Specifically, a palladium-plated single-layer TAB fixed around a semiconductor element on an organic insulating substrate coated with an insulating paste for fixing the semiconductor element to each other, and electrically connected by Au wire bonding. Since the semiconductor device and the palladium-plated layer TAB are resin-sealed by a screen printing method, the resin element can be made thin,
In addition, since there is no need to add a release agent, and the adhesion between the sealing resin and the semiconductor element, the Au wire, and the lead does not decrease, high adhesion and high moisture resistance can be obtained. .

【０００６】[0006]

【実施例】次に本発明の実施例について図面を参照して
説明する。図１は、本発明の一実施例の半導体装置の断
面図である。また図２は本発明の一実施例の半導体装置
の製造過程を示す概略図であり、製造過程順に説明す
る。まず、図２（ａ）の様に、エポキシ系で主に一液性
の樹脂を、絶縁ペースト６として有機系絶縁性基板５の
表面に一定の高さに塗布する。塗布はスクリーン印刷法
で行う。次に図２（ｂ）の様に、絶縁ペースト６を塗布
した有機系絶縁性基板５に、Ｐｄメッキ付ＴＡＢテープ
４を貼り付ける。その後図２（ｃ）の様に半導体素子１
を絶縁ペースト６に塗布した有機系絶縁性基板５の中央
にボンディングさせる。この状態の半完成品の半導体装
置を約１２０℃の恒温に保たれたベーク炉に３時間入れ
て、半導体素子と、Ｐｄメッキ付ＴＡＢテープ４とガラ
エポ基板を固着させる。続いて、図２（ｄ）の様にＡｕ
ワイヤーで、半導体素子１の電極部とＰｄメッキ付一層
ＴＡＢ４の導体パターンをワイヤーボンディングする。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 2 is a schematic view showing a manufacturing process of the semiconductor device according to one embodiment of the present invention, which will be described in the order of the manufacturing process. First, as shown in FIG. 2A, an epoxy-based one-component resin is applied as an insulating paste 6 to the surface of the organic insulating substrate 5 at a predetermined height. The coating is performed by a screen printing method. Next, as shown in FIG. 2B, a TAB tape 4 with Pd plating is attached to the organic insulating substrate 5 to which the insulating paste 6 has been applied. Then, as shown in FIG.
Is bonded to the center of the organic insulating substrate 5 applied to the insulating paste 6. The semi-finished product semiconductor device in this state is placed in a baking furnace maintained at a constant temperature of about 120 ° C. for 3 hours to fix the semiconductor element, the TAB tape 4 with Pd plating, and the glass epoxy substrate. Then, as shown in FIG.
An electrode portion of the semiconductor element 1 is wire-bonded to the conductor pattern of the Pd-plated single layer TAB4 with a wire.

【０００７】最後に、図２（ｅ）の様に有機性絶縁性基
板５より上方をスクリーン印刷法により、主に、一液性
エポキシ樹脂である封止樹脂３を印刷し、９５℃の恒温
に保たれたベーク炉に１０時間入れて、封止樹脂３を固
着させる。ここで有機系絶縁基板５の厚さは２００μ
ｍ、絶縁ペーストの厚さは３０μｍ、Ｐｄメッキ付一層
ＴＡＢテープ厚は７０μｍ、封止樹脂厚は３００μｍで
半導体装置の全体厚は６００μｍになる。図３は、スク
リーン印刷法による樹脂封止の概略図である。ここで
は、封止樹脂３を用いてボンディング済の半完成品の半
導体装置について説明する。ボンディング済半完成品の
半導体装置をテーブル１６にセットし、バキュームで固
定する。次にエポキシ系の一液性樹脂１３をスクリーン
上にのせ、スキージ１１を強く下方に押しながら、右か
ら左に移動させる。この時、樹脂１３がスクリーンメッ
シュ１２を必要量通過して半完成品の半導体装置を封止
する。スクリーン１７は、樹脂で作られており、スクリ
ーンの厚さの分だけ樹脂１３を塗布する。図４は、本発
明の第２の実施例の半導体装置の断面図である。ここで
は絶縁ペースト６を塗布した有機系絶縁基板５にパラジ
ウムメッキ付リードフレーム１８を貼り付けている。Finally, as shown in FIG. 2E, the sealing resin 3 which is a one-part epoxy resin is mainly printed on the upper part of the organic insulating substrate 5 by a screen printing method, and the temperature is kept at 95 ° C. For 10 hours in a baking furnace maintained under the above conditions to fix the sealing resin 3. Here, the thickness of the organic insulating substrate 5 is 200 μm.
m, the thickness of the insulating paste is 30 μm, the thickness of the TAB tape with Pd plating is 70 μm, the thickness of the sealing resin is 300 μm, and the total thickness of the semiconductor device is 600 μm. FIG. 3 is a schematic diagram of resin sealing by a screen printing method. Here, a semi-finished semiconductor device that has been bonded using the sealing resin 3 will be described. The semi-finished semiconductor device after bonding is set on the table 16 and fixed by vacuum. Next, the epoxy-based one-component resin 13 is placed on the screen, and the squeegee 11 is moved from right to left while pressing it down strongly. At this time, the resin 13 passes through the required amount of the screen mesh 12 to seal the semi-finished semiconductor device. The screen 17 is made of a resin, and the resin 13 is applied by the thickness of the screen. FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention. Here, a lead frame 18 with palladium plating is attached to the organic insulating substrate 5 to which the insulating paste 6 has been applied.

【０００８】[0008]

【発明の効果】以上説明したように、本発明の半導体装
置によれば、ワイヤーボンディングにより接続を行うに
もかかわらず薄型にできる。また、樹脂封止はスクリー
ン印刷法によって行うので、離型剤の添加を必要とせ
ず、封止樹脂と半導体素子、Ａｕワイヤー、リードとの
密着力が低下することはないので、高密着となり、高い
耐湿性を得ることができる。さらに、ＴＡＢテープを熱
プレス等で成形する必要がないので、ダイボンィング、
ワイヤーボンィング性が安定して実現できるという効果
を奏するものである。As described above, according to the semiconductor device of the present invention, it is possible to make the semiconductor device thin even though connection is performed by wire bonding. In addition, since the resin sealing is performed by a screen printing method, it does not require the addition of a release agent, and the adhesion between the sealing resin and the semiconductor element, the Au wire, and the lead does not decrease. High moisture resistance can be obtained. Furthermore, since there is no need to mold the TAB tape by hot pressing or the like, die bonding,
This has the effect of stably realizing wire bonding properties.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例の断面図FIG. 1 is a cross-sectional view of one embodiment of the present invention.

【図２】本発明の一実施例の半導体装置の製造過程を示
す概略図FIG. 2 is a schematic view showing a manufacturing process of the semiconductor device according to one embodiment of the present invention;

【図３】スクリーン印刷法による樹脂封止の概略図FIG. 3 is a schematic diagram of resin sealing by a screen printing method.

【図４】本発明の第２の実施例の断面図FIG. 4 is a sectional view of a second embodiment of the present invention.

【図５】従来の半導体装置の例を示す図FIG. 5 is a diagram showing an example of a conventional semiconductor device.

【図６】従来の半導体装置の例を示す図FIG. 6 illustrates an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 半導体素子 ２ Ａｕワイヤー ３ 封止樹脂 ４ パラジウムメッキ付一層ＴＡＢテープ ５ 有機系絶縁基板 ６ 絶縁ペースト ７ ＴＡＢテープ ８ シート ９ ＩＣ固定接着層 １０ 導体パターン固定接着層 １１ スキージ １２ スクリーンメッシュ １３ 樹脂 １４ 吸着穴 １５ 導体パターン １６ テーブル DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Au wire 3 Sealing resin 4 Single layer TAB tape with palladium plating 5 Organic insulating substrate 6 Insulating paste 7 TAB tape 8 Sheet 9 IC fixing adhesive layer 10 Conductive pattern fixing adhesive layer 11 Squeegee 12 Screen mesh 13 Resin 14 Adsorption Hole 15 Conductor pattern 16 Table

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】有機系絶縁性基板上に搭載された半導体素
子と、前記有機系絶縁性基板に貼付され、ＴＡＢテープ
を主構成部材とする外部電極と、前記半導体素子の電極
部と前記外部電極とをボンディングするＡｕワイヤーと
を含む半導体装置であって、少なくとも前記半導体素子
と前記Ａｕワイヤーとがスクリーン印刷樹脂部材で樹脂
封止されていることを特徴とする半導体装置。1. A semiconductor element mounted on an organic insulating substrate, an external electrode attached to the organic insulating substrate and having a TAB tape as a main component, an electrode portion of the semiconductor element and the external electrode. A semiconductor device including an Au wire for bonding an electrode, wherein at least the semiconductor element and the Au wire are resin-sealed with a screen printing resin member. 【請求項２】有機系絶縁性基板の表面に絶縁ペーストを
塗付し、Ｐｄメッキ付ＴＡＢテープを貼り付け、また半
導体素子をボンディングし、次いで半導体素子の電極部
とＰｄメッキ付一層ＴＡＢの導体パターンとをＡｕワイ
ヤーでボンディングし、これをスクリーン印刷によって
樹脂封止することを特徴とする請求項１に記載の半導体
装置の製造方法。2. An insulating paste is applied to the surface of an organic insulating substrate, a TAB tape with Pd plating is attached, and a semiconductor element is bonded. Then, an electrode portion of the semiconductor element and a single-layer TAB conductor with Pd plating are bonded. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the pattern is bonded with an Au wire, and the resin is sealed by screen printing.
JP5195544A 1993-07-13 1993-07-13 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2570123B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5195544A JP2570123B2 (en) 1993-07-13 1993-07-13 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5195544A JP2570123B2 (en) 1993-07-13 1993-07-13 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0729931A JPH0729931A (en) 1995-01-31
JP2570123B2 true JP2570123B2 (en) 1997-01-08

Family

ID=16342869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5195544A Expired - Fee Related JP2570123B2 (en) 1993-07-13 1993-07-13 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2570123B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2666788B2 (en) * 1995-10-19 1997-10-22 日本電気株式会社 Manufacturing method of chip size semiconductor device

Also Published As

Publication number Publication date
JPH0729931A (en) 1995-01-31

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