JPH04277636A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPH04277636A JPH04277636A JP3063988A JP6398891A JPH04277636A JP H04277636 A JPH04277636 A JP H04277636A JP 3063988 A JP3063988 A JP 3063988A JP 6398891 A JP6398891 A JP 6398891A JP H04277636 A JPH04277636 A JP H04277636A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- conductor pattern
- manufacturing
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 239000011347 resin Substances 0.000 claims abstract description 43
- 229920005989 resin Polymers 0.000 claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 claims abstract description 41
- 239000004020 conductor Substances 0.000 claims abstract description 37
- 238000004381 surface treatment Methods 0.000 claims abstract description 16
- 238000007747 plating Methods 0.000 claims abstract description 10
- 238000007789 sealing Methods 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 21
- 239000011253 protective coating Substances 0.000 claims description 8
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 238000010292 electrical insulation Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.
【０００２】0002
【従来の技術】半導体チップを搭載するリードフレーム
は半導体チップの高集積化とともに、ますます高密度化
が進んでいる。プレス加工あるいはエッチング加工によ
ってリードフレームを製造する場合は、使用するリード
フレームの材厚によってリードフレームピッチの加工限
界が規定されるから、ファインピッチのリードフレーム
を製造する場合にはより薄厚の材料を使わなければなら
ない。最近では０．１ｍｍ 程度の材厚の材料も用いら
れるようになっている。2. Description of the Related Art Lead frames on which semiconductor chips are mounted are becoming increasingly dense as semiconductor chips become more highly integrated. When manufacturing lead frames by stamping or etching, the processing limit for lead frame pitch is determined by the thickness of the lead frame material used, so when manufacturing fine-pitch lead frames, thinner materials must be used. must be used. Recently, materials with a thickness of about 0.1 mm have also been used.
【０００３】ところで、材厚が薄くなるとそれに伴って
リードの強度が低下するから、加工後の取り扱い時にリ
ードの変形が生じたりしやすくなるといった問題点があ
る。そこで、ファインピッチを可能とするため薄厚の導
体材料として銅箔を用い、この銅箔を剥離性の接着剤で
キャリアフィルムに貼着し、その後、エッチング加工し
てリードを形成している。[0003] However, as the thickness of the material decreases, the strength of the lead decreases, resulting in the problem that the lead is more likely to be deformed during handling after processing. Therefore, in order to make fine pitch possible, copper foil is used as a thin conductor material, and this copper foil is attached to a carrier film with a releasable adhesive, and then etched to form leads.
【０００４】0004
【発明が解決しようとする課題】しかしながら、上記の
従来方法では薄厚の銅箔をキャリアフィルムで支持した
接合体に対してエッチング等の処理を施さなければなら
ず、ワイヤボンディング性を向上させるためにボンディ
ング部にめっきを施したりする場合もこの接合体に対し
てめっき処理をしなければならず、製造工程が厄介であ
るという問題点がある。上記のキャリアフィルム上に導
体パターンを形成した接合体は、図１（ｅ） に示すよ
うな半導体装置（樹脂封止部２の半導体チップ３０搭載
側の外面に接続端子４をグリッド状に配置したもの）の
製造に利用できるが、このような半導体装置を製造する
場合も、樹脂封止を行って接続端子を形成するためキャ
リアフィルムをエッチングした後、接続端子を形成する
部位にめっき処理を施したりしなければならず、製造工
程がやはり厄介であるという問題点があった。[Problems to be Solved by the Invention] However, in the above conventional method, it is necessary to perform a treatment such as etching on a bonded body in which thin copper foil is supported by a carrier film, and in order to improve wire bonding properties, Even when plating is applied to the bonding portion, the bonded body must be subjected to plating treatment, which poses a problem in that the manufacturing process is complicated. The above-mentioned bonded body in which a conductor pattern is formed on the carrier film is a semiconductor device as shown in FIG. However, when manufacturing such semiconductor devices, the carrier film is sealed with resin and etched to form the connection terminals, and then the parts where the connection terminals are to be formed are plated. However, there was a problem in that the manufacturing process was still complicated.
【０００５】なお、上記の図１（ｅ） に示す半導体装
置は、半導体チップ３０の搭載面とは逆側の樹脂封止部
２の外面に接続端子４を設けたものである。このように
樹脂封止部２の片面側に接続端子４を設けた半導体装置
は高密度実装にきわめて有効である。本発明はこのよう
な樹脂封止部に導体パターンが埋没して封止され、樹脂
封止部の外面側に接続端子が設置されるタイプの半導体
装置の製造方法に関するものであり、リードパターンが
高密度に形成でき、かつ、上記の半導体装置の製造にあ
たって製造が容易にでき、それによって製造コストを効
果的に下げることができる半導体装置の製造方法を提供
することを目的とする。The semiconductor device shown in FIG. 1E is provided with connection terminals 4 on the outer surface of the resin sealing portion 2 on the side opposite to the surface on which the semiconductor chip 30 is mounted. A semiconductor device in which the connection terminal 4 is provided on one side of the resin sealing portion 2 in this manner is extremely effective for high-density packaging. The present invention relates to a method for manufacturing a semiconductor device of the type in which a conductor pattern is buried and sealed in such a resin sealing part and a connecting terminal is installed on the outer surface of the resin sealing part. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be formed at high density and that can be easily manufactured in manufacturing the above-described semiconductor device, thereby effectively reducing manufacturing costs.
【０００６】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、半導体チップを
樹脂封止すると共に導体パターン部の半導体チップ搭載
面側を樹脂内に埋没させて樹脂封止した半導体装置の製
造方法において、パッド部および導体パターン部等の所
定パターンを有すると共にボンディング部、接続端子形
成部等の所要部位にめっき等の表面処理を施したリード
フレームを形成し、該リードフレームの半導体チップ搭
載面と反対側の面に電気的絶縁性を有するキャリアフィ
ルムを貼着して接合体を形成し、該接合体の前記パッド
部に半導体チップを搭載して半導体チップとリードフレ
ームとを接続し、前記接合体の半導体チップ搭載側の片
面を樹脂封止し、該樹脂封止体の前記キャリアフィルム
側に前記導体パターン部と接続する接続端子を設けるこ
とを特徴とする。また、前記リードフレームに貼着する
キャリアフィルムとして、接続端子を形成する位置にあ
らかじめ透孔を形成したフィルムを用い、樹脂封止後に
前記透孔部に接続端子としてのバンプを形成することを
特徴とする。また、半導体チップを搭載して樹脂封止し
た後、キャリアフィルムをエッチングして接続端子を形
成するための孔加工を施し、該孔内に接続端子としての
バンプを形成することを特徴とする。また、半導体チッ
プを樹脂封止すると共に導体パターン部の半導体チップ
搭載面側を樹脂内に埋没させて樹脂封止した半導体装置
の製造方法において、パッド部および導体パターン部等
の所定パターンを有すると共にボンディング部、接続端
子形成部等にめっき等の表面処理を施したリードフレー
ムを作成し、該リードフレームに電気的絶縁性を有する
と共に剥離性接着剤を塗布した転写フィルムを貼着して
接合体を形成し、該接合体の前記パッド部に半導体チッ
プを接合して半導体チップと前記導体パターン部とを接
続し、前記接合体の半導体チップ搭載側の片面を樹脂封
止し、前記転写フィルムを剥離除去し、樹脂封止体の導
体パターン部の露出面に保護コーティングを施すと共に
、導体パターン部と接続する接続端子を形成することを
特徴とする。また、樹脂封止後に導体パターン部のアウ
ターリードをフォーミング加工等することによって接続
端子を形成することを特徴とする。Means for Solving the Problems The present invention has the following configuration to achieve the above object. That is, in a method of manufacturing a semiconductor device in which a semiconductor chip is sealed with a resin and the semiconductor chip mounting surface side of a conductive pattern part is buried in the resin and sealed with a resin, the semiconductor device has a predetermined pattern such as a pad part and a conductive pattern part, and A lead frame is formed with surface treatment such as plating on the required parts such as bonding parts and connection terminal forming parts, and a carrier film having electrical insulation properties is pasted on the surface of the lead frame opposite to the semiconductor chip mounting surface. A semiconductor chip is mounted on the pad portion of the bonded body to connect the semiconductor chip and a lead frame, one surface of the bonded body on the side where the semiconductor chip is mounted is sealed with a resin, and the semiconductor chip is sealed with a resin. A connecting terminal connected to the conductor pattern portion is provided on the carrier film side of the resin sealing body. Further, the carrier film to be attached to the lead frame is a film in which through holes are formed in advance at positions where connecting terminals are to be formed, and bumps as connecting terminals are formed in the through holes after resin sealing. shall be. Further, after the semiconductor chip is mounted and sealed with resin, the carrier film is etched to form holes for forming connection terminals, and bumps as connection terminals are formed in the holes. In addition, in a method of manufacturing a semiconductor device in which a semiconductor chip is sealed with a resin and the semiconductor chip mounting surface side of a conductor pattern part is buried in the resin and sealed with a resin, the semiconductor device has a predetermined pattern such as a pad part and a conductor pattern part, and A lead frame is created with surface treatment such as plating applied to the bonding area, connection terminal forming area, etc., and a transfer film coated with an electrically insulating and peelable adhesive is attached to the lead frame to form a bonded body. A semiconductor chip is bonded to the pad portion of the bonded body to connect the semiconductor chip and the conductor pattern portion, one side of the bonded body on which the semiconductor chip is mounted is sealed with a resin, and the transfer film is bonded to the pad portion of the bonded body. It is characterized in that it is peeled off, a protective coating is applied to the exposed surface of the conductor pattern portion of the resin sealing body, and a connection terminal is formed to connect to the conductor pattern portion. Another feature is that the connection terminals are formed by performing forming processing or the like on the outer leads of the conductor pattern portion after resin sealing.
【０００７】[0007]
【実施例】以下、本発明の好適な実施例を添付図面に基
づいて詳細に説明する。本発明に係る半導体装置の製造
方法は、半導体チップを接合するパッド部や導体パター
ン部が形成される導体部とこの導体部を支持するキャリ
アフィルムとをあらかじめ別体で形成した後、たがいに
貼着して樹脂封止等の加工を施すことを特徴とする。図
１は半導体装置の製造方法の第１の実施例を示す。本実
施例ではまず、図１（ａ） に示すように、薄厚の導体
材料にエッチング加工あるいはプレス加工を施して所定
パターンを有するリードフレーム１０を形成すると共に
、リードフレーム１０と別体にリードフレーム１０に貼
着するためのキャリアフィルム２０を形成する。リード
フレーム１０には半導体チップを接合するためのパッド
部１２および導体パターン部１４等の所定パターンを形
成する。また、リードフレーム１０にはワイヤボンディ
ングの際にボンディング部となる部位に金めっき等を施
したり、接続端子としてバンプを形成する部位にめっき
等の所要の表面処理を施す。また、キャリアフィルム２
０には接続端子を形成する部位にあらかじめ透孔２２を
形成しておく。DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the method for manufacturing a semiconductor device according to the present invention, a conductor part on which a pad part for joining a semiconductor chip and a conductor pattern part are formed, and a carrier film supporting this conductor part are separately formed in advance, and then they are pasted together. It is characterized by applying processing such as resin sealing. FIG. 1 shows a first embodiment of a method for manufacturing a semiconductor device. In this embodiment, first, as shown in FIG. 1(a), a lead frame 10 having a predetermined pattern is formed by etching or pressing a thin conductive material, and a lead frame 10 is formed separately from the lead frame 10. A carrier film 20 to be attached to 10 is formed. Predetermined patterns such as a pad portion 12 and a conductive pattern portion 14 for bonding a semiconductor chip are formed on the lead frame 10 . Further, the lead frame 10 is subjected to gold plating or the like on a portion that will become a bonding portion during wire bonding, or is subjected to necessary surface treatment such as plating on a portion where a bump is to be formed as a connection terminal. In addition, carrier film 2
0, a through hole 22 is formed in advance at a portion where a connecting terminal is to be formed.
【０００８】次に、上記のリードフレーム１０とキャリ
アフィルム２０とを位置合わせして接着する（図１（ｂ
） ）。この接合体に対し、上記パッド部１２に半導体
チップ３０を接合し、ワイヤボンディングによって半導
体チップ３０と導体パターン部１４とを接続する（図１
（ｃ） ）。次いで、半導体チップ３０を樹脂封止する
。このときの樹脂封止は上記の接合体で半導体チップ３
０を搭載する片面側のみ樹脂封止するもので、キャリア
フィルム２０は樹脂封止部２の外面に露出するようにす
る。
キャリアフィルム２０にはあらかじめ透孔２２が形成さ
れているから、透孔２２部分の内底面に導体パターン部
１４が露出する。導体パターン部１４の透孔２２部分に
はあらかじめ表面処理が施してあるから、そのままはん
だを盛ることによってバンプ状の接続端子４を形成する
ことができる。Next, the lead frame 10 and the carrier film 20 are aligned and bonded (see FIG. 1(b)).
) ). To this assembled body, a semiconductor chip 30 is bonded to the pad portion 12, and the semiconductor chip 30 and the conductor pattern portion 14 are connected by wire bonding (FIG.
(c) ). Next, the semiconductor chip 30 is sealed with resin. At this time, the semiconductor chip 3 is sealed with the above bonded body.
0 is mounted, and the carrier film 20 is exposed to the outer surface of the resin sealing part 2. Since the carrier film 20 has the through holes 22 formed in advance, the conductor pattern portion 14 is exposed on the inner bottom surface of the through holes 22 portion. Since the through hole 22 portion of the conductor pattern portion 14 has been surface-treated in advance, the bump-shaped connection terminal 4 can be formed by directly applying solder thereon.
【０００９】上記実施例の半導体装置の製造方法は、リ
ードフレーム１０に導体パターン部１４等の所要のパタ
ーンを形成するとともに、必要な表面処理をあらかじめ
施した後にキャリアフィルム２０を貼着するから、後工
程で表面処理を施したりする必要がなく、後工程側での
処理が非常に簡単になるという利点がある。また、リー
ドフレーム１０の製造にあたっては、従来のエッチング
加工等の製造方法やめっき等の表面処理方法がそのまま
利用できるから製造も容易である。そして、リードフレ
ーム１０の取り扱いにおいてはキャリアフィルム２０を
リードフレーム１０に貼着して導体パターン部１４等を
支持することで、より薄厚の導体材料を用いることがで
き導体パターンの高密度化にも有効に対処することがで
きるという利点がある。[0009] The method for manufacturing a semiconductor device according to the above embodiment involves forming required patterns such as the conductor pattern portion 14 on the lead frame 10, and pasting the carrier film 20 after performing necessary surface treatment in advance. It has the advantage that there is no need to perform surface treatment in the post-process, and the processing in the post-process is extremely simple. Further, in manufacturing the lead frame 10, conventional manufacturing methods such as etching processing and surface treatment methods such as plating can be used as they are, so manufacturing is easy. When handling the lead frame 10, by attaching the carrier film 20 to the lead frame 10 to support the conductor pattern portion 14, etc., it is possible to use a thinner conductor material and to increase the density of the conductor pattern. It has the advantage of being able to be dealt with effectively.
【００１０】上記実施例においては、リードフレーム１
０に貼着するキャリアフィルム２０としてあらかじめ透
孔２２等の加工を施したフィルムを用いたが、リードフ
レーム１０に貼着する際には単にシート状のキャリアフ
ィルムを用い、樹脂封止後にキャリアフィルム２０にエ
ッチング等の処理を施して透孔２２等を形成するように
してもよい。上記例ではキャリアフィルム２０に透孔２
２を形成して透孔２２部分に接続端子としてバンプを形
成したが、外部接続用として導体パターン部１４から樹
脂封止部２の外方にアウターリードを延設するようにし
てもよい。この場合はキャリアフィルム２０に透孔２２
を形成する必要はなく、樹脂封止後にアウターリードの
カットおよびフォーミング加工を行う。図１（ａ）での
リードフレーム１０を形成する際にアウターリードに所
要の表面処理を施しておくことによって後工程で表面処
理を行う必要がなくなり、そのまま実装可能となる。In the above embodiment, the lead frame 1
As the carrier film 20 to be attached to the lead frame 10, a film with holes 22, etc. processed in advance was used, but when attached to the lead frame 10, a sheet-like carrier film was simply used, and the carrier film was sealed after resin sealing. The through holes 22 and the like may be formed by performing a process such as etching on the substrate 20. In the above example, the carrier film 20 has two through holes.
2 and a bump was formed as a connection terminal in the through hole 22 portion, however, an outer lead may be extended from the conductive pattern portion 14 to the outside of the resin sealing portion 2 for external connection. In this case, the carrier film 20 has through holes 22.
It is not necessary to form the outer leads, and the outer leads are cut and formed after resin sealing. By subjecting the outer leads to the required surface treatment when forming the lead frame 10 in FIG. 1A, there is no need to perform surface treatment in a subsequent process, and the lead frame 10 can be mounted as is.
【００１１】図２は上記の半導体装置の製造方法の他の
実施例として、剥離性の接着剤を塗布した転写フィルム
を用いた製造方法を示す説明図である。本実施例では、
まずリードフレーム１０に前記転写フィルム４０を接着
した接合体を形成する。リードフレーム１０は上記実施
例と同様にパッド部１２および導体パターン部１４を形
成すると共に必要な表面処理を施したものである（図２
（ａ） ）。次に、この接合体に半導体チップ３０を接
合し、ワイヤボンディングによって半導体チップ３０と
導体パターン部１４とを接続する（図２（ｂ） ）。次
いで、半導体チップ３０を樹脂封止する。この樹脂封止
も図２（ｃ）に示すように片面の樹脂封止である。次に
、樹脂封止部２から上記の転写フィルム４０を剥離除去
する。転写フィルム４０は剥離性接着剤によって接着さ
れているから簡単に剥離できる。図２（ｄ）は転写フィ
ルム４０を剥離した状態である。転写フィルム４０を剥
離することによって導体パターン部１４が露出するから
、導体パターン部１４を保護するための保護コーティン
グ５０を施す。保護コーティング５０はスクリーン印刷
法でソルダーレジストを塗布する方法等が利用できる。
バンプで接続端子を形成する場合は接続端子を形成する
部位を除いて保護コーティング５０を施すようにする。
保護コーティング５０を施したら、はんだバンプ等によ
って接続端子４を形成する。図２（ｅ） は保護コーテ
ィング５０を施して接続端子４を形成した状態を示して
いる。FIG. 2 is an explanatory view showing a manufacturing method using a transfer film coated with a releasable adhesive as another embodiment of the above-described semiconductor device manufacturing method. In this example,
First, a bonded body is formed by bonding the transfer film 40 to the lead frame 10. The lead frame 10 has a pad portion 12 and a conductive pattern portion 14 formed thereon as well as the necessary surface treatment as in the above embodiment (see FIG. 2).
(a) ). Next, the semiconductor chip 30 is bonded to this bonded body, and the semiconductor chip 30 and the conductor pattern portion 14 are connected by wire bonding (FIG. 2(b)). Next, the semiconductor chip 30 is sealed with resin. This resin sealing is also one-sided resin sealing as shown in FIG. 2(c). Next, the above-mentioned transfer film 40 is peeled off and removed from the resin sealing part 2. Since the transfer film 40 is bonded with a releasable adhesive, it can be easily peeled off. FIG. 2(d) shows a state in which the transfer film 40 has been peeled off. Since the conductive pattern portion 14 is exposed by peeling off the transfer film 40, a protective coating 50 is applied to protect the conductive pattern portion 14. The protective coating 50 can be formed by applying a solder resist using a screen printing method. When forming a connection terminal with a bump, a protective coating 50 is applied to the area other than the area where the connection terminal is to be formed. Once the protective coating 50 has been applied, the connection terminals 4 are formed by solder bumps or the like. FIG. 2(e) shows a state in which the protective coating 50 is applied to form the connection terminal 4.
【００１２】本実施例の半導体装置の製造方法の場合も
転写フィルム４０に接着するリードフレーム１０に導体
パターン部１４等の所要パターンを形成するとともに、
あらかじめ所要の表面処理を施すから、後工程において
リードの表面処理等を行う必要がなくなり、製造工程に
おける困難さが解消でき容易に製造することが可能にな
る。また、これらの表面処理等は従来のリードフレーム
の製造工程において従来行っている処理内容であり、従
来方法がそのまま利用できて確実な製造が可能であり、
かつ製造コストを低減させることができる。In the method of manufacturing a semiconductor device of this embodiment as well, required patterns such as the conductor pattern portion 14 are formed on the lead frame 10 to be adhered to the transfer film 40, and
Since the required surface treatment is performed in advance, there is no need to perform surface treatment of the leads in the subsequent process, and difficulties in the manufacturing process can be resolved and manufacturing can be facilitated. In addition, these surface treatments are conventionally performed in the manufacturing process of conventional lead frames, and the conventional methods can be used as they are, allowing reliable manufacturing.
Moreover, manufacturing costs can be reduced.
【００１３】なお、上記実施例においては半導体チップ
３０と導体パターン部１４とはワイヤボンディングによ
って接続したが、半導体チップ３０の接続方法はとくに
問わない。バンプによって半導体チップをじかに導体パ
ターン部に接続する方法であってもかまわない。また、
外部接続用の接続端子の配置なども装置に応じて適宜設
定することができる。In the above embodiment, the semiconductor chip 30 and the conductor pattern portion 14 are connected by wire bonding, but the method of connecting the semiconductor chip 30 is not particularly limited. A method may also be used in which the semiconductor chip is directly connected to the conductive pattern portion using bumps. Also,
The arrangement of connection terminals for external connections can also be set as appropriate depending on the device.
【００１４】[0014]
【発明の効果】本発明に係る半導体装置の製造方法によ
れば、上述したように、従来のリードフレームの製造方
法がそのまま利用でき、かつ樹脂封止後に表面処理を施
す等の加工上の困難さが解消できて、容易に製造するこ
とが可能になり、製造コストを下げることができる等の
著効を奏する。Effects of the Invention According to the method for manufacturing a semiconductor device according to the present invention, as described above, the conventional lead frame manufacturing method can be used as is, and processing difficulties such as surface treatment after resin sealing can be used. It has remarkable effects such as being able to eliminate problems, making it easy to manufacture, and reducing manufacturing costs.
【図面の簡単な説明】[Brief explanation of the drawing]
【図１】半導体装置の製造方法の一実施例を示す説明図
である。FIG. 1 is an explanatory diagram showing an example of a method for manufacturing a semiconductor device.
【図２】半導体装置の製造方法の他の実施例を示す説明
図である。FIG. 2 is an explanatory diagram showing another example of a method for manufacturing a semiconductor device.
２ 樹脂封止部 ４ 接続端子 １０ リードフレーム １２ パッド部 １４ 導体パターン部 ２０ キャリアフィルム ２２ 透孔 ３０ 半導体チップ ４０ 転写フィルム ５０ 保護コーティング 2 Resin sealing part 4 Connection terminal 10 Lead frame 12 Pad part 14 Conductor pattern part 20 Carrier film 22 Through hole 30 Semiconductor chip 40 Transfer film 50 Protective coating
Claims (5)
体パターン部の半導体チップ搭載面側を樹脂内に埋没さ
せて樹脂封止した半導体装置の製造方法において、パッ
ド部および導体パターン部等の所定パターンを有すると
共にボンディング部、接続端子形成部等の所要部位にめ
っき等の表面処理を施したリードフレームを形成し、該
リードフレームの半導体チップ搭載面と反対側の面に電
気的絶縁性を有するキャリアフィルムを貼着して接合体
を形成し、該接合体の前記パッド部に半導体チップを搭
載して半導体チップとリードフレームとを接続し、前記
接合体の半導体チップ搭載側の片面を樹脂封止し、該樹
脂封止体の前記キャリアフィルム側に前記導体パターン
部と接続する接続端子を設けることを特徴とする半導体
装置の製造方法。1. A method for manufacturing a semiconductor device in which a semiconductor chip is sealed with a resin and the semiconductor chip mounting surface side of a conductor pattern part is buried in the resin, wherein a predetermined pattern of a pad part, a conductor pattern part, etc. A carrier in which a lead frame is formed with surface treatment such as plating on required parts such as bonding parts and connection terminal forming parts, and the surface of the lead frame opposite to the semiconductor chip mounting surface has electrical insulation properties. A film is attached to form a bonded body, a semiconductor chip is mounted on the pad portion of the bonded body, the semiconductor chip and a lead frame are connected, and one side of the bonded body on which the semiconductor chip is mounted is sealed with a resin. A method of manufacturing a semiconductor device, characterized in that a connecting terminal connected to the conductor pattern portion is provided on the carrier film side of the resin sealing body.
ィルムとして、接続端子を形成する位置にあらかじめ透
孔を形成したフィルムを用い、樹脂封止後に前記透孔部
に接続端子としてのバンプを形成することを特徴とする
請求項１記載の半導体装置の製造方法。2. As a carrier film to be adhered to the lead frame, a film in which through holes are formed in advance at positions where connecting terminals are to be formed is used, and bumps as connecting terminals are formed in the through holes after resin sealing. The method for manufacturing a semiconductor device according to claim 1, characterized in that:
後、キャリアフィルムをエッチングして接続端子を形成
するための孔加工を施し、該孔内に接続端子としてのバ
ンプを形成することを特徴とする請求項１記載の半導体
装置の製造方法。3. After mounting the semiconductor chip and sealing it with resin, the carrier film is etched to form holes for forming connection terminals, and bumps as connection terminals are formed in the holes. 2. The method of manufacturing a semiconductor device according to claim 1.
体パターン部の半導体チップ搭載面側を樹脂内に埋没さ
せて樹脂封止した半導体装置の製造方法において、パッ
ド部および導体パターン部等の所定パターンを有すると
共にボンディング部、接続端子形成部等にめっき等の表
面処理を施したリードフレームを作成し、該リードフレ
ームに電気的絶縁性を有すると共に剥離性接着剤を塗布
した転写フィルムを貼着して接合体を形成し、該接合体
の前記パッド部に半導体チップを接合して半導体チップ
と前記導体パターン部とを接続し、前記接合体の半導体
チップ搭載側の片面を樹脂封止し、前記転写フィルムを
剥離除去し、樹脂封止体の導体パターン部の露出面に保
護コーティングを施すと共に、導体パターン部と接続す
る接続端子を形成することを特徴とする半導体装置の製
造方法。4. A method for manufacturing a semiconductor device in which a semiconductor chip is sealed with a resin and the semiconductor chip mounting surface side of a conductor pattern portion is buried in the resin, wherein a predetermined pattern of a pad portion, a conductor pattern portion, etc. A lead frame is prepared with surface treatment such as plating on the bonding part, connection terminal forming part, etc., and a transfer film coated with an electrically insulating and peelable adhesive is attached to the lead frame. to form a bonded body, bond a semiconductor chip to the pad portion of the bonded body to connect the semiconductor chip and the conductor pattern portion, seal one side of the bonded body on the side where the semiconductor chip is mounted with a resin, and A method for manufacturing a semiconductor device, which comprises peeling off a transfer film, applying a protective coating to an exposed surface of a conductor pattern portion of a resin sealing body, and forming a connecting terminal to be connected to the conductor pattern portion.
ーリードをフォーミング加工等することによって接続端
子を形成することを特徴とする請求項１または２記載の
半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein the connecting terminals are formed by forming the outer leads of the conductor pattern portion after resin sealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6398891A JP2962586B2 (en) | 1991-03-05 | 1991-03-05 | Semiconductor device, method of manufacturing the same, and joined body used therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6398891A JP2962586B2 (en) | 1991-03-05 | 1991-03-05 | Semiconductor device, method of manufacturing the same, and joined body used therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04277636A true JPH04277636A (en) | 1992-10-02 |
| JP2962586B2 JP2962586B2 (en) | 1999-10-12 |
Family
ID=13245176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6398891A Expired - Lifetime JP2962586B2 (en) | 1991-03-05 | 1991-03-05 | Semiconductor device, method of manufacturing the same, and joined body used therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2962586B2 (en) |
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|---|---|
| JP2962586B2 (en) | 1999-10-12 |
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