JP3783648B2 - Wiring board and method of manufacturing semiconductor device using the same - Google Patents

Wiring board and method of manufacturing semiconductor device using the same Download PDF

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Publication number
JP3783648B2
JP3783648B2 JP2002108000A JP2002108000A JP3783648B2 JP 3783648 B2 JP3783648 B2 JP 3783648B2 JP 2002108000 A JP2002108000 A JP 2002108000A JP 2002108000 A JP2002108000 A JP 2002108000A JP 3783648 B2 JP3783648 B2 JP 3783648B2
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Prior art keywords
wiring
substrate
semiconductor device
wiring board
semiconductor chip
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JP2003303920A (en
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聡 珍田
亮 松浦
護 御田
崇之 吉和
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、配線板及びその製造方法、ならびに配線板を用いた半導体装置に関し、特に、外部接続端子が表面に露出した状態の半導体装置を製造するための配線板に適用して有効な技術に関するものである。
【0002】
【従来の技術】
従来、LGA(Land Grid Array)型の半導体装置を製造するときには、例えば、ポリイミドテープなどの絶縁基板の両面に配線を設けた配線板が用いられている。
【0003】
前記配線板は、例えば、前記絶縁基板の第1主面に、半導体チップの外部電極と接続される配線が設けられている。また、前記絶縁基板の前記第1主面の裏面(第2主面)には、実装基板の配線(端子)と接続するための外部接続端子(ランド)が設けられている。このとき、前記絶縁基板の第1主面の配線と第2主面のランドとは、例えば、ビアにより電気的に接続されている。
【0004】
しかしながら、前記絶縁基板の両面に配線を形成する場合、製造コストがかかる。また、前記配線板が厚くなり、半導体装置の小型化が難しい。
【0005】
そこで、近年では、図10(a)及び図10(b)に示すように、テープ状の基板1の表面に配線2を設けた配線板を用いて、前記LGA型の半導体装置を製造する方法が提案されている。
【0006】
このとき、前記基板1は、例えば、QFN(Quad Flat Non-leaded package)型の半導体装置を製造するときに、封止用絶縁体の漏れを防ぐために用いられる基板であり、例えば、図11に示すように、ポリイミドテープなどの絶縁基材101の表面に再剥離材102が設けられている。ここで、前記再剥離剤102は、例えば、熱可塑性接着剤のように、後の工程で前記配線2をはがすことができる接着材料である。また、前記配線2の表面には、例えば、錫めっき、錫合金めっき、金めっきなどの第1機能めっき401が設けられている。
【0007】
またこのとき、前記配線2の外部接続端子2Aは、例えば、図10(a)のようにアレイ状に配置されており、前記配線2の一端は、半導体チップが搭載される領域AR1の外周を囲むように配置されている。
【0008】
また、前記基板1は、テープキャリアパッケージ(TCP)に用いられる配線板の絶縁基板と同様に、一方向に長尺なテープ状であり、図10(a)に示したような領域AR2内のパターンが繰り返し設けられている。
【0009】
図10(a)及び図10(b)に示したような配線板は、例えば、前記基板1上に、銅箔などの導体膜を接着した後、前記導体膜をパターニングして前記配線2を形成する。その後、必要に応じて前記配線2の表面に前記第1機能めっき401を形成する。
【0010】
図10(a)及び図10(b)に示したような配線板を用いて半導体装置を製造するときには、まず、図12(a)に示すように、前記配線板の配線2上に、例えば、熱硬化性樹脂からなる熱硬化性接着剤5を用いて半導体チップ6を接着する。そして、前記半導体チップ6の外部電極601と前記配線2をボンディングワイヤ7で接続する。
【0011】
次に、図12(b)に示すように、前記半導体チップ6、前記配線2、及び前記ボンディングワイヤ7の周囲を封止用絶縁体8で封止する。このとき、前記封止用絶縁体8は、例えば、トランスファモールドで形成する。
【0012】
次に、例えば、前記基板1を加熱して、前記再剥離材102の接着力を低下させた状態で前記基板1をはがすと、図13(a)に示したように、前記配線2が、前記熱硬化性接着剤5及び前記封止用絶縁体8の表面に露出した状態の半導体装置を得ることができる。このとき、前記再剥離材102の種類によっては、前記基板1を加熱しなくてもはがすことができる。
【0013】
このとき、前記半導体装置は、図13(a)に示したように、前記配線2が露出した状態になっている。そのため、必要に応じて、図13(b)に示すように、前記配線2の露出した面に、接合材などの第2機能めっき402を形成する。前記第2機能めっき402は、例えば、錫めっき、錫合金めっき、金めっきなどで形成する。このとき、前記第2機能めっき402は、前記第1機能めっき401と同じ材料で形成してもよいし、異なる材料で形成してもよい。
【0014】
【発明が解決しようとする課題】
しかしながら、前記従来の技術では、前記半導体装置を実装基板に実装したときに、図14に示すように、前記半導体装置の配線2と前記実装基板9の配線(端子)901との接続部の高さhが低い。そのため、前記半導体装置と前記実装基板の隙間SPが狭く、前記隙間SPに封止樹脂を流し込むのが難しいという問題があった。
【0015】
また、前記半導体装置と前記実装基板の隙間SPに封止樹脂を流し込むのが難しいので、前記半導体装置の配線2と前記実装基板9の配線(端子)901との接続部を封止せずに、空気中に露出させた状態にすることが多い。そのため、前記半導体装置の配線2と前記実装基板9の配線(端子)901との接続部の酸化、あるいは空気中の水分による腐食などで、前記接続部の接続信頼性や電気的特性が劣化しやすいという問題があった。
【0016】
本発明の目的は、基板の表面に配線が設けられた配線板を用い、前記配線上に半導体チップを実装した後、前記基板をはがして前記配線を露出させた半導体装置において、前記半導体装置を実装基板に実装したときに、前記半導体装置と前記実装基板の間を絶縁体で封止しやすくすることが可能な技術を提供することにある。
【0017】
本発明の目的は、基板の表面に配線が設けられた配線板を用い、前記配線上に半導体チップを実装した後、前記基板をはがして前記配線を露出させた半導体装置において、前記半導体装置を実装基板に実装するときの接続信頼性や電気的特性の劣化を防ぐことが可能な技術を提供することにある。
【0018】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。
【0019】
【課題を解決するための手段】
本発明において開示される発明の概要を説明すれば、以下の通りである。
【0020】
(1)基板の表面に配線(導体パターン)が設けられており、前記基板の前記配線が設けられた面に半導体チップを実装した後、前記基板をはがして半導体装置を形成するための配線板であって、前記基板は、前記配線の一部と重なる領域が開口しており、前記開口部内に、突起状の導体(バンプ)が設けられている配線板である。
【0021】
前記(1)の手段によれば、前記基板の開口部内に、前記突起状の導体が設けられていることにより、前記配線板上に半導体チップを実装し、封止した後、前記基板をはがしたときに、前記配線の露出面に前記突起状の導体が設けられた半導体装置を得ることができる。そのため、前記配線板を用いて形成した半導体装置を実装基板に実装するときに、前記突起状の導体の高さ分だけ、前記半導体装置と前記実装基板の隙間を広くすることができる。このとき、前記突起状の導体は、例えば、銅、ニッケル、金、銀、錫、もしくはこれらの合金を用いて設けることが好ましい。
【0022】
またこのとき、前記突起状の導体の表面に接合材が設けられていると、前記配線板を用いて半導体装置を形成したときに、前記基板をはがした後、前記配線の露出面に接合材を形成する工程が省略することができる。このとき、前記接合材としては、例えば、錫めっき、錫合金めっき、金めっきを設けることが好ましい。
【0023】
また、前記基板として、例えば、特定の条件のもとで、前記配線との接着力が低下する材料を用いると、前記配線板を形成する工程及び前記半導体チップを実装する工程、ならびにその間の搬送工程などで前記配線が前記基板からはがれるのを防ぐことができる。また、特定の条件のもとで、前記配線との接着力を低下させた状態で前記基板をはがすことができるので、前記基板をはがした後、前記配線の表面に前記基板の残りが生じるのを防ぐことができる。
【0024】
このとき、前記基板としては、例えば、加熱することにより軟化し、接着力が低下する熱可塑性樹脂を用いた基板が挙げられる。また、例えば、光を照射することにより接着力が変化する材料を用いた基板を用いることも可能である。
【0025】
またこのとき、前記基板は、単一の材料である必要はなく、例えば、平板状の基材の表面に熱可塑性樹脂を設けたものを用い、前記基板の前記熱可塑性樹脂上に前記配線を設けてもよい。
【0026】
(2)基板の表面に配線(導体パターン)が形成された配線板上に半導体チップを接着し、前記半導体チップの外部電極と前記配線とを電気的に接続し、前記半導体チップの周囲を絶縁体で封止した後、前記基板をはがして前記配線を露出させる半導体装置の製造方法であって、前記配線板の前記基板は、前記配線の一部と重なる領域が開口しており、前記開口部内に、突起状の導体(バンプ)が形成されている半導体装置の製造方法である。
【0027】
前記(2)の手段によれば、前記基板の前記配線の一部と重なる領域が開口しており、前記開口部内に突起状の導体(バンプ)が形成されている配線板を用いて半導体装置を製造することにより、前記基板をはがした後、前記配線の露出面上に前記突起状の導体が設けられた半導体装置を容易に得ることができる。
【0028】
また、前記配線板を用いて製造した半導体装置は、前記配線の露出面上に前記突起状の導体が形成されているため、前記半導体装置を実装基板に実装するときに、前記突起状の導体と前記実装基板の配線(端子)を接続させることにより、前記半導体装置と前記実装基板の間の隙間を広くすることができる。そのため、前記半導体装置と前記実装基板の間に絶縁体を流し込みやすくすることができ、前記突起状の導体と前記実装基板の配線(端子)の接続部の封止が容易になる。
【0029】
また、前記突起状の導体と前記実装基板の配線(端子)の接続部が封止になるため、前記突起状の導体と前記実装基板の配線(端子)の接続部の酸化や腐食を防ぐことができ、接続信頼性や電気的特性の劣化を防ぐことができる。
【0030】
またこのとき、前記突起状の導体の表面に接合材が形成されている配線板を用いると、従来の半導体装置の製造方法のように、前記基板をはがした後で前記接合材を形成する必要がない。そのため、前記半導体装置の製造コストを低減することができる。
【0031】
また、前記基板として、例えば、特定の条件のもとで、前記配線との接着力が低下する材料を用いると、前記配線板を形成する工程及び前記半導体チップを実装する工程、ならびにその間の搬送工程などで前記配線が前記基板からはがれるのを防ぐことができる。また、特定の条件のもとで、前記配線との接着力を低下させた状態で前記基板をはがすことができるので、前記基板をはがした後、前記配線の表面に前記基板の残りが生じるのを防ぐことができる。
【0032】
このとき、前記基板としては、例えば、加熱することにより軟化し、接着力が低下する熱可塑性樹脂を用いた基板が挙げられる。また、例えば、光を照射することにより接着力が変化する材料を用いた基板を用いることも可能である。
【0033】
またこのとき、前記基板は、単一の材料である必要はなく、例えば、平板状の基材の表面に熱可塑性樹脂を形成したものを用い、前記基板の前記熱可塑性樹脂上に前記配線が形成されていてもよい。
【0034】
以下、本発明について、図面を参照して実施の形態(実施例)とともに詳細に説明する。
【0035】
なお、実施例を説明するための全図において、同一機能を有するものは、同一符号を付け、その繰り返しの説明は省略する。
【0036】
【発明の実施の形態】
(実施例)
図1及び図2は、本発明による一実施例の配線板の概略構成を示す模式図であり、図1(a)は配線板の平面図、図1(b)は図1(a)のA−A’線での断面図、図2は図1(b)の部分拡大断面図である。
【0037】
図1(a)及び図1(b)、ならびに図2において、1は基板、101は絶縁基材、102は再剥離材(熱可塑性接着剤)、1Aは基板の開口部、2は配線、2Aは配線のランド(外部接続端子)、3は突起状の導体(バンプ)、401は第1機能めっき、402は第2機能めっきである。
【0038】
本実施例の配線板は、図1(a)及び図1(b)、ならびに図2に示すように、基板1の表面に配線2が設けられている。このとき、前記配線2の一端には、ランド2Aが設けられており、前記ランド2Aがアレイ状に配置されている。
【0039】
また、前記基板1は、前記配線2のランド2Aの下部に開口部1Aが設けられており、前記開口部内に、前記配線2と接続された突起状の導体3が設けられている。このとき、前記突起状の導体3は、例えば、銅めっきやニッケルめっきなどからなり、高さが数μmから数十μmになるように設けられている。
【0040】
また、本実施例の配線板は、半導体チップを実装し、前記半導体チップの周囲を封止した後、前記基板をはがして半導体装置を製造するための配線板であって、前記基板1は、例えば、図2に示したように、絶縁基材101の表面に再剥離材102が設けられている。ここで、前記再剥離材102は、例えば、熱可塑性接着剤のように、後の工程で前記配線2をはがすことのできる接着材料である。
【0041】
また、図1(b)では省略しているが、前記配線2の表面、言い換えると露出した面には、例えば、金めっき、錫めっき、錫合金めっきなどの第1機能めっき401が設けられている。また、前記突起状の導体3の表面にも、例えば、錫めっき、錫合金めっき、金めっきなどの第2機能めっき402が設けられている。
【0042】
また、本実施例の配線板では、半導体チップは、例えば、図1(a)に示した領域AR1上に搭載される。また、前記基板1は、一方向に長尺なテープ状であり、図1(a)に示した領域AR2内のパターンが繰り返し設けられている。
【0043】
図3は、本実施例の配線板の製造方法を説明するための模式図であり、図3(a)は基板に開口部を形成する工程の断面図、図3(b)は基板に導体膜を張り合わせる工程の断面図、図3(c)は突起状の導体を形成する工程の断面図、図3(d)は導体膜をパターニングする工程の断面図である。
【0044】
本実施例の配線板を製造するときには、まず、例えば、図3(a)に示したように、前記絶縁基材101の表面に前記再剥離材102が形成された基板1に開口部1Aを形成する。このとき、前記開口部1Aは、例えば、金型を用いた打ち抜き加工で形成する。
【0045】
次に、図3(b)に示すように、前記開口部1Aが形成された基板1と導体膜2’を張り合わせる。このとき、前記導体膜2’は、例えば、電解銅箔や圧延銅箔などを用い、前記基板1の前記再剥離材102が形成された面に張り合わせる。またこのとき、前記再剥離材102には、例えば、熱可塑性接着剤を用い、前記基板1の温度を、例えば、200℃から260℃に加熱して張り合わせる。
【0046】
次に、図3(c)に示すように、前記基板1の開口部1A内に、突起状の導体3を形成する。このとき、前記突起状の導体3は、例えば、電気銅めっきや電気ニッケルめっきなどで、高さが数μmから数十μmになるように形成する。またこのとき、前記突起状の導体3は、前記基板1からはがれやすくするために、前記基板1との接触面積を小さくするのが好ましく、図3(c)に示したように、ドーム状に形成する。
【0047】
次に、図3(d)に示すように、前記導体膜2’をパターニングして配線2を形成する。このとき、前記配線2は、例えば、サブトラクティブ法やセミアディティブ法などを用いて形成する。
【0048】
その後、前記配線2の露出した面に、第1機能めっき401を形成するとともに、前記突起状の導体3の表面に第2機能めっき402を形成すると、図2に示したような配線板を得ることができる。このとき、前記第1機能めっき401と前記第2機能めっき402は、同じ材料を用いて形成してもよいし、異なる材料を用いて、それぞれの機能に最適なめっきを形成してもよい。
【0049】
図4及び図5は、本実施例の配線板を用いた半導体装置の製造方法を説明するための模式図であり、図4(a)は半導体チップを実装する工程の断面図、図4(b)は半導体チップを封止する工程の断面図、図5は基板をはがした後の半導体装置の断面図である。
【0050】
本実施例の配線板を用いて半導体装置を製造するときには、まず、図4(a)に示すように、前記配線板の配線2上に、例えば、熱硬化性接着剤5を用いて半導体チップ6を接着する。そして、前記半導体チップ6の外部電極601と前記配線2をボンディングワイヤ7で電気的に接続する。このとき、図4(a)では省略しているが、前記配線2の表面には、前記第1機能めっき401が形成されており、前記突起状の導体3の表面には、前記第2機能めっき402が形成されている。
【0051】
次に、図4(b)に示すように、前記半導体チップ6及び前記配線2、ならびに前記ボンディングワイヤ7の周囲に封止用絶縁体8を形成して封止する。このとき、前記封止用絶縁体8は、例えば、トランスファモールドで形成する。
【0052】
その後、例えば、全体を170℃から200℃に加熱し、前記再剥離材(熱可塑性接着剤)102の接着力を低下させた状態で前記基板1をはがすと、図5に示すように、前記配線2が前記封止用絶縁体8及び前記熱硬化性接着剤5の表面に露出し、且つ前記配線2のランド(外部接続端子)2A上に、前記突起状の導体3が形成された半導体装置を得ることができる。またこのとき、前記再剥離材102の種類によっては、加熱することなく前記基板1をはがすことができる。
【0053】
図6は、本実施例の作用効果を説明するための模式断面図である。
【0054】
本実施例の配線板を用いて製造した半導体装置は、前記基板1をはがしたときに、図5に示したように、前記配線2のランド2A上に、前記突起状の導体3が形成されている。すなわち、前記半導体装置を実装基板に実装したときに、図6に示すように、前記半導体装置の配線2(ランド2A)と前記実装基板9の配線(端子)901の間に前記突起状の導体3が介在している。そのため、前記突起状の導体3の高さhの分だけ、前記半導体装置と前記実装基板の隙間SPを広くすることができる。
【0055】
また、前記半導体装置と前記実装基板9の隙間を広くすることにより、封止樹脂を流し込みやすくなるため、前記半導体装置の配線2(ランド2A)と前記実装基板9の配線(端子)901との接続部の酸化や腐食を防ぐことができる。そのため、前記半導体装置を実装したときの接続信頼性や電気的特性の劣化を防ぐことができる。
【0056】
以上説明したように、本実施例の配線板によれば、前記基板1に開口部1Aを設け、前記開口部1A内に前記突起状の導体3を設けることにより、外部接続端子(ランド)2A上に突起状の導体3が設けられた半導体装置を容易に得ることができる。
【0057】
また、前記半導体装置の外部接続端子(ランド)2A上に前記突起状の導体3が設けられるため、前記半導体装置を実装基板9に実装したときに、前記突起状導体3の高さhの分だけ、前記半導体装置と前記実装基板9の隙間を広くすることができる。
【0058】
また、前記半導体装置と前記実装基板9の隙間を広くすることにより、封止樹脂を流し込みやすくなるため、前記半導体装置の配線2(ランド2A)と前記実装基板9の配線(端子)901との接続部の酸化や腐食を防ぐことができる。そのため、前記半導体装置を実装したときの接続信頼性や電気的特性の劣化を防ぐことができる。
【0059】
また、前記突起状の導体3及びその表面の第2機能めっき402が設けられた配線板を用いて半導体装置を製造することにより、前記基板をはがした後で、前記配線2の外部接続端子(ランド)2A上に、バンプを形成したり、接合材を形成したりする工程を省略することができる。そのため、半導体装置の製造コストを低減することができる。
【0060】
また、本実施例では、前記基板1は、絶縁基材101上に再剥離材(熱可塑性接着剤)を形成したものを用いているが、これに限らず、例えば、熱可塑性樹脂からなる単一の基板を用いてもよいことは言うまでもない。
【0061】
また、前記再剥離材102も、前記熱可塑性接着剤に限らず、例えば、光を照射することにより接着力が変化する材料を用いてもよい。
【0062】
図7は、前記実施例の変形例を説明するための模式図であり、図7(a)及び図7(b)は配線板の製造方法を説明するための断面図である。
【0063】
前記実施例では、前記配線板の製造方法として、前記開口部1Aが形成された基板1に導体膜2’を張り合わせる例を説明したが、これに限らず、種々の方法で製造することができる。例えば、まず、図7(a)に示すように、前記基板1と前記導体膜2’を張り合わせておき、図7(b)に示すように、前記基板1の前記導体膜2’が接着された面の裏面から開口部1Aを形成してもよい。このとき、前記開口部1Aは、例えば、炭酸ガスレーザなどのレーザ光を照射して形成する。
【0064】
図8及び図9は、前記実施例の応用例を説明するための模式図であり、図8(a)は配線板の概略構成を示す平面図、図8(b)は図8(a)のB−B’線での断面図、図9(a)は図8(a)に示した配線板を用いて製造した半導体装置の平面図、図9(b)は図9(a)のC−C’線での断面図である。
【0065】
前記実施例では、図1(a)に示したように、配線2の外部接続端子(ランド)2Aがアレイ状に配置された、LGA型の半導体装置を製造するための配線板を例に挙げて説明したが、これに限らず、例えば、QFN型の半導体装置を製造する配線板としても用いることができる。
【0066】
前記実施例で説明したような配線板を、前記QFN型の半導体装置の製造に用いるときには、図8(a)及び図8(b)に示すように、前記基板1上の、半導体チップを実装する領域AR1の外周を囲むように前記配線2を設ける。また、前記半導体チップを実装する領域AR1には、例えば、アイランド2Bを設けておく。
【0067】
このときも、図8(b)に示すように、前記基板1の、前記配線2の下部に開口部を設け、前記開口部内に突起状の導体3を設けておく。
【0068】
図8(a)及び図8(b)に示したような配線板を用い、図9(a)及び図9(b)に示すように、前記アイランド2B上に半導体チップ6を接着し、前記半導体チップ6の外部電極601と前記配線2とをボンディングワイヤ7で電気的に接続し、封止用絶縁体8で封止した後、前記基板1をはがせば、前記配線2上に前記突起状の導体3が形成された半導体装置を得ることができる。
【0069】
また、QFN型の半導体装置を製造するときに用いる配線板は、前記実施例で説明したような手順に限らず、例えば、銅板を打ち抜いてリードを形成したリードフレームを前記基板1に張り合わせてもよい。この場合も、前記リードフレームを張り合わせる前、もしくは貼り合わせた後に、前記基板1に開口部1Aを形成し、前記開口部1A内に前記突起状の導体3を形成することにより、配線2上に突起状の導体3が形成された半導体装置を容易に得ることができる。
【0070】
以上、本発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において、種々変更可能であることはもちろんである。
【0071】
【発明の効果】
本発明において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下の通りである。
【0072】
(1)基板の表面に配線が設けられた配線板を用い、前記配線上に半導体チップを実装した後、前記基板をはがして前記配線を露出させた半導体装置において、前記半導体装置を実装基板に実装したときに、前記半導体装置と前記実装基板の間を絶縁体で封止しやすくすることができる。
【0073】
(2)基板の表面に配線が設けられた配線板を用い、前記配線上に半導体チップを実装した後、前記基板をはがして前記配線を露出させた半導体装置において、前記半導体装置を実装基板に実装するときの接続信頼性や電気的特性の劣化を防ぐことができる。
【図面の簡単な説明】
【図1】本発明による一実施例の配線板の概略構成を示す模式図であり、図1(a)は配線板の平面図、図1(b)は図1(a)のA−A’線での断面図である。
【図2】本実施例の配線板の概略構成を示す模式図であり、図1(b)の部分拡大断面図である。
【図3】本実施例の配線板の製造方法を説明するための模式図であり、図3(a)は基板に開口部を形成する工程の断面図、図3(b)は基板に導体膜を張り合わせる工程の断面図、図3(c)は突起状の導体を形成する工程の断面図、図3(d)は導体膜をパターニングする工程の断面図である。
【図4】本実施例の配線板を用いた半導体装置の製造方法を説明するための模式図であり、図4(a)は半導体チップを実装する工程の断面図、図4(b)は半導体チップを封止する工程の断面図である。
【図5】本実施例の配線板を用いた半導体装置の製造方法を説明するための模式図であり、基板をはがした後の半導体装置の断面図である。
【図6】本実施例の作用効果を説明するための模式断面図である。
【図7】前記実施例の変形例を説明するための模式図であり、図7(a)及び図7(b)は、配線板の製造方法を説明するための断面図である。
【図8】前記実施例の応用例を説明するための模式図であり、図8(a)は配線板の概略構成を示す平面図、図8(b)は図8(a)のB−B’線での断面図である。
【図9】前記実施例の応用例を説明するための模式図であり、図9(a)は図8(a)に示した配線板を用いた半導体装置の概略構成を示す平面図、図9(b)は図9(a)のC−C’線での断面図である。
【図10】従来の配線板の概略構成を示す模式図であり、図10(a)は配線板の平面図、図10(b)は図10(a)のD−D’線での断面図である。
【図11】従来の配線板の概略構成を示す模式図であり、図10(b)の拡大断面図である。
【図12】本実施例の配線板を用いた半導体装置の製造方法を説明するための模式図であり、図12(a)は半導体チップを実装する工程の断面図、図12(b)は半導体チップを封止する工程の断面図である。
【図13】本実施例の配線板を用いた半導体装置の製造方法を説明するための模式図であり、図13(a)は基板をはがした後の半導体装置の断面図、図13(b)は配線の表面に機能めっきを形成する工程の断面図である。
【図14】課題を説明するための模式断面図である。
【符号の説明】
1 基板
101 絶縁基材
102 再剥離材(熱可塑性接着剤)
1A 基板の開口部
2 配線
2A ランド(外部接続端子)
2B アイランド
3 突起状の導体
401 第1機能めっき
402 第2機能めっき
5 熱硬化性接着剤
6 半導体チップ
601 半導体チップの外部電極
7 ボンディングワイヤ
8 封止用絶縁体
9 実装基板
901 実装基板の配線(端子)
SP 半導体装置と実装基板の隙間
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring board, a manufacturing method thereof, and a semiconductor device using the wiring board, and more particularly to a technique effective when applied to a wiring board for manufacturing a semiconductor device in which external connection terminals are exposed on the surface. Is.
[0002]
[Prior art]
Conventionally, when manufacturing an LGA (Land Grid Array) type semiconductor device, for example, a wiring board provided with wiring on both surfaces of an insulating substrate such as polyimide tape is used.
[0003]
In the wiring board, for example, wiring connected to an external electrode of a semiconductor chip is provided on the first main surface of the insulating substrate. In addition, an external connection terminal (land) for connecting to the wiring (terminal) of the mounting substrate is provided on the back surface (second main surface) of the first main surface of the insulating substrate. At this time, the wiring on the first main surface of the insulating substrate and the land on the second main surface are electrically connected by, for example, vias.
[0004]
However, when wiring is formed on both surfaces of the insulating substrate, a manufacturing cost is required. Further, the wiring board becomes thick, and it is difficult to reduce the size of the semiconductor device.
[0005]
Therefore, in recent years, as shown in FIGS. 10A and 10B, a method of manufacturing the LGA type semiconductor device using a wiring board in which wiring 2 is provided on the surface of a tape-like substrate 1. Has been proposed.
[0006]
At this time, the substrate 1 is a substrate used to prevent leakage of a sealing insulator when a QFN (Quad Flat Non-leaded package) type semiconductor device is manufactured, for example, as shown in FIG. As shown, a re-peeling material 102 is provided on the surface of an insulating substrate 101 such as a polyimide tape. Here, the re-peeling agent 102 is an adhesive material that can peel off the wiring 2 in a later step, such as a thermoplastic adhesive. The surface of the wiring 2 is provided with a first functional plating 401 such as tin plating, tin alloy plating, or gold plating.
[0007]
At this time, the external connection terminals 2A of the wiring 2 are arranged in an array as shown in FIG. 10A, for example, and one end of the wiring 2 extends around the outer periphery of the area AR1 on which the semiconductor chip is mounted. It is arranged to surround.
[0008]
Further, the substrate 1 is in the form of a tape that is long in one direction, similar to the insulating substrate of the wiring board used in the tape carrier package (TCP), and is in the area AR2 as shown in FIG. A pattern is repeatedly provided.
[0009]
10A and 10B, for example, after a conductive film such as a copper foil is bonded on the substrate 1, the conductive film is patterned to form the wiring 2. Form. Thereafter, the first functional plating 401 is formed on the surface of the wiring 2 as necessary.
[0010]
When manufacturing a semiconductor device using a wiring board as shown in FIGS. 10A and 10B, first, as shown in FIG. 12A, on the wiring 2 of the wiring board, for example, Then, the semiconductor chip 6 is bonded using a thermosetting adhesive 5 made of a thermosetting resin. Then, the external electrode 601 of the semiconductor chip 6 and the wiring 2 are connected by a bonding wire 7.
[0011]
Next, as shown in FIG. 12B, the periphery of the semiconductor chip 6, the wiring 2, and the bonding wire 7 is sealed with a sealing insulator 8. At this time, the sealing insulator 8 is formed by, for example, transfer molding.
[0012]
Next, for example, when the substrate 1 is heated and the substrate 1 is peeled in a state where the adhesive strength of the re-peeling material 102 is reduced, as shown in FIG. A semiconductor device exposed on the surfaces of the thermosetting adhesive 5 and the sealing insulator 8 can be obtained. At this time, depending on the type of the re-peeling material 102, the substrate 1 can be removed without heating.
[0013]
At this time, the semiconductor device is in a state where the wiring 2 is exposed, as shown in FIG. Therefore, as required, second functional plating 402 such as a bonding material is formed on the exposed surface of the wiring 2 as shown in FIG. The second functional plating 402 is formed by, for example, tin plating, tin alloy plating, gold plating, or the like. At this time, the second functional plating 402 may be formed of the same material as the first functional plating 401 or may be formed of a different material.
[0014]
[Problems to be solved by the invention]
However, in the conventional technique, when the semiconductor device is mounted on a mounting substrate, as shown in FIG. 14, the height of the connecting portion between the wiring 2 of the semiconductor device and the wiring (terminal) 901 of the mounting substrate 9 is high. The h is low. Therefore, there is a problem that a gap SP between the semiconductor device and the mounting substrate is narrow and it is difficult to pour a sealing resin into the gap SP.
[0015]
Further, since it is difficult to pour a sealing resin into the gap SP between the semiconductor device and the mounting substrate, without sealing the connection portion between the wiring 2 of the semiconductor device and the wiring (terminal) 901 of the mounting substrate 9, Often exposed to air. Therefore, the connection reliability and electrical characteristics of the connection portion deteriorate due to oxidation of the connection portion between the wiring 2 of the semiconductor device and the wiring (terminal) 901 of the mounting substrate 9 or corrosion due to moisture in the air. There was a problem that it was easy.
[0016]
An object of the present invention is to provide a semiconductor device in which a wiring board provided with wiring on the surface of a substrate is used, a semiconductor chip is mounted on the wiring, and then the substrate is peeled off to expose the wiring. An object of the present invention is to provide a technique capable of facilitating sealing between the semiconductor device and the mounting substrate with an insulator when mounted on the mounting substrate.
[0017]
An object of the present invention is to provide a semiconductor device in which a wiring board provided with wiring on the surface of a substrate is used, a semiconductor chip is mounted on the wiring, and then the substrate is peeled off to expose the wiring. An object of the present invention is to provide a technology capable of preventing deterioration of connection reliability and electrical characteristics when mounted on a mounting board.
[0018]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0019]
[Means for Solving the Problems]
The outline of the invention disclosed in the present invention will be described as follows.
[0020]
(1) A wiring board on which a wiring (conductor pattern) is provided on the surface of the substrate, a semiconductor chip is mounted on the surface of the substrate on which the wiring is provided, and then the substrate is peeled off to form a semiconductor device And the said board | substrate is a wiring board by which the area | region which overlaps with a part of said wiring is opened, and the protrusion-shaped conductor (bump) is provided in the said opening part.
[0021]
According to the means of (1), the protrusion-shaped conductor is provided in the opening of the substrate, so that after mounting and sealing the semiconductor chip on the wiring board, the substrate is removed. Then, a semiconductor device in which the protruding conductor is provided on the exposed surface of the wiring can be obtained. Therefore, when a semiconductor device formed using the wiring board is mounted on a mounting board, the gap between the semiconductor device and the mounting board can be widened by the height of the protruding conductor. At this time, the projecting conductor is preferably provided using, for example, copper, nickel, gold, silver, tin, or an alloy thereof.
[0022]
Further, at this time, if a bonding material is provided on the surface of the protruding conductor, when the semiconductor device is formed using the wiring board, the substrate is peeled off and then bonded to the exposed surface of the wiring. The step of forming the material can be omitted. At this time, as the bonding material, for example, it is preferable to provide tin plating, tin alloy plating, or gold plating.
[0023]
In addition, when the substrate is made of, for example, a material whose adhesive strength with the wiring is lowered under specific conditions, the step of forming the wiring board, the step of mounting the semiconductor chip, and the conveyance between them The wiring can be prevented from peeling off from the substrate in a process or the like. In addition, since the substrate can be peeled off under a specific condition with reduced adhesion to the wiring, after the substrate is peeled off, the substrate remains on the surface of the wiring. Can be prevented.
[0024]
At this time, examples of the substrate include a substrate using a thermoplastic resin that is softened by heating and has a reduced adhesive force. Further, for example, it is possible to use a substrate using a material whose adhesive force changes when irradiated with light.
[0025]
At this time, the substrate does not need to be a single material. For example, the substrate is provided with a thermoplastic resin on the surface of a flat substrate, and the wiring is formed on the thermoplastic resin of the substrate. It may be provided.
[0026]
(2) Adhering a semiconductor chip on a wiring board having a wiring (conductor pattern) formed on the surface of the substrate, electrically connecting the external electrode of the semiconductor chip and the wiring, and insulating the periphery of the semiconductor chip A method of manufacturing a semiconductor device in which the substrate is peeled off after being sealed with a body to expose the wiring, wherein the substrate of the wiring board has an opening that overlaps with a part of the wiring. In this method, a protruding conductor (bump) is formed in the part.
[0027]
According to the means of (2), a semiconductor device using a wiring board in which a region overlapping with a part of the wiring of the substrate is opened, and a protruding conductor (bump) is formed in the opening. By manufacturing the semiconductor device, after peeling off the substrate, a semiconductor device in which the protruding conductor is provided on the exposed surface of the wiring can be easily obtained.
[0028]
In addition, since the protruding conductor is formed on the exposed surface of the wiring in the semiconductor device manufactured using the wiring board, the protruding conductor is mounted when the semiconductor device is mounted on a mounting substrate. By connecting the wirings (terminals) of the mounting substrate to each other, the gap between the semiconductor device and the mounting substrate can be widened. Therefore, an insulator can be easily poured between the semiconductor device and the mounting substrate, and the connection between the protruding conductor and the wiring (terminal) of the mounting substrate can be easily sealed.
[0029]
In addition, since the connecting portion between the protruding conductor and the wiring (terminal) of the mounting substrate is sealed, oxidation and corrosion of the connecting portion between the protruding conductor and the wiring (terminal) of the mounting substrate are prevented. It is possible to prevent deterioration of connection reliability and electrical characteristics.
[0030]
At this time, if a wiring board having a bonding material formed on the surface of the protruding conductor is used, the bonding material is formed after the substrate is peeled off as in the conventional method of manufacturing a semiconductor device. There is no need. Therefore, the manufacturing cost of the semiconductor device can be reduced.
[0031]
In addition, when the substrate is made of, for example, a material whose adhesive strength with the wiring is lowered under specific conditions, the step of forming the wiring board, the step of mounting the semiconductor chip, and the conveyance between them The wiring can be prevented from peeling off from the substrate in a process or the like. In addition, since the substrate can be peeled off under a specific condition with reduced adhesion to the wiring, after the substrate is peeled off, the substrate remains on the surface of the wiring. Can be prevented.
[0032]
At this time, examples of the substrate include a substrate using a thermoplastic resin that is softened by heating and has a reduced adhesive force. Further, for example, it is possible to use a substrate using a material whose adhesive force changes when irradiated with light.
[0033]
At this time, the substrate does not need to be a single material. For example, the substrate is formed by forming a thermoplastic resin on the surface of a flat substrate, and the wiring is formed on the thermoplastic resin of the substrate. It may be formed.
[0034]
Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.
[0035]
In all the drawings for explaining the embodiments, parts having the same function are given the same reference numerals and their repeated explanation is omitted.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
(Example)
1 and 2 are schematic views showing a schematic configuration of a wiring board according to an embodiment of the present invention. FIG. 1 (a) is a plan view of the wiring board, and FIG. 1 (b) is a plan view of FIG. A sectional view taken along line AA ′, FIG. 2 is a partially enlarged sectional view of FIG.
[0037]
1A and 1B, and FIG. 2, 1 is a substrate, 101 is an insulating base material, 102 is a re-peeling material (thermoplastic adhesive), 1A is an opening of the substrate, 2 is wiring, 2A is a land (external connection terminal) of wiring, 3 is a protruding conductor (bump), 401 is first function plating, and 402 is second function plating.
[0038]
In the wiring board of this example, wiring 2 is provided on the surface of a substrate 1 as shown in FIGS. At this time, a land 2A is provided at one end of the wiring 2, and the land 2A is arranged in an array.
[0039]
The substrate 1 is provided with an opening 1A below the land 2A of the wiring 2, and a protruding conductor 3 connected to the wiring 2 is provided in the opening. At this time, the protruding conductor 3 is made of, for example, copper plating or nickel plating, and is provided so that the height is several μm to several tens of μm.
[0040]
Further, the wiring board of this example is a wiring board for manufacturing a semiconductor device by mounting a semiconductor chip, sealing the periphery of the semiconductor chip, and then peeling off the substrate. For example, as shown in FIG. 2, the re-peeling material 102 is provided on the surface of the insulating base material 101. Here, the re-peeling material 102 is an adhesive material that can peel off the wiring 2 in a later step, such as a thermoplastic adhesive.
[0041]
Although omitted in FIG. 1B, a first functional plating 401 such as gold plating, tin plating, or tin alloy plating is provided on the surface of the wiring 2, in other words, the exposed surface. Yes. Further, a second functional plating 402 such as tin plating, tin alloy plating, or gold plating is also provided on the surface of the protruding conductor 3.
[0042]
Further, in the wiring board of this embodiment, the semiconductor chip is mounted on, for example, the area AR1 shown in FIG. The substrate 1 has a tape shape elongated in one direction, and a pattern in the area AR2 shown in FIG. 1A is repeatedly provided.
[0043]
3A and 3B are schematic views for explaining the method of manufacturing the wiring board of this embodiment. FIG. 3A is a cross-sectional view of a process of forming an opening in the substrate, and FIG. 3B is a conductor on the substrate. FIG. 3C is a cross-sectional view of the step of forming the protruding conductors, and FIG. 3D is a cross-sectional view of the step of patterning the conductive film.
[0044]
When manufacturing the wiring board of the present embodiment, first, as shown in FIG. 3A, for example, the opening 1A is formed in the substrate 1 on which the re-peeling material 102 is formed on the surface of the insulating base 101. Form. At this time, the opening 1A is formed, for example, by punching using a mold.
[0045]
Next, as shown in FIG. 3B, the substrate 1 on which the opening 1A is formed and the conductor film 2 ′ are bonded together. At this time, for example, an electrolytic copper foil or a rolled copper foil is used as the conductor film 2 ′, and the conductor film 2 ′ is bonded to the surface of the substrate 1 on which the re-peeling material 102 is formed. At this time, for example, a thermoplastic adhesive is used for the re-peeling material 102, and the temperature of the substrate 1 is heated to 200 ° C. to 260 ° C., for example, and bonded.
[0046]
Next, as shown in FIG. 3C, a protruding conductor 3 is formed in the opening 1 </ b> A of the substrate 1. At this time, the protruding conductors 3 are formed so as to have a height of several μm to several tens of μm, for example, by electrolytic copper plating or electrolytic nickel plating. At this time, it is preferable to reduce the contact area of the protruding conductor 3 with the substrate 1 so that the protruding conductor 3 can be easily peeled off from the substrate 1, and as shown in FIG. Form.
[0047]
Next, as shown in FIG. 3D, the conductor film 2 ′ is patterned to form the wiring 2. At this time, the wiring 2 is formed using, for example, a subtractive method or a semi-additive method.
[0048]
Thereafter, the first functional plating 401 is formed on the exposed surface of the wiring 2 and the second functional plating 402 is formed on the surface of the protruding conductor 3 to obtain a wiring board as shown in FIG. be able to. At this time, the first functional plating 401 and the second functional plating 402 may be formed using the same material, or different materials may be used to form the optimal plating for each function.
[0049]
4 and 5 are schematic views for explaining a method of manufacturing a semiconductor device using the wiring board of this embodiment. FIG. 4A is a cross-sectional view of a process for mounting a semiconductor chip, and FIG. b) is a cross-sectional view of the process of sealing the semiconductor chip, and FIG. 5 is a cross-sectional view of the semiconductor device after the substrate is peeled off.
[0050]
When a semiconductor device is manufactured using the wiring board of this embodiment, first, as shown in FIG. 4A, a semiconductor chip is formed on the wiring 2 of the wiring board using, for example, a thermosetting adhesive 5. 6 is adhered. Then, the external electrode 601 of the semiconductor chip 6 and the wiring 2 are electrically connected by a bonding wire 7. At this time, although omitted in FIG. 4A, the first functional plating 401 is formed on the surface of the wiring 2, and the second function is formed on the surface of the protruding conductor 3. A plating 402 is formed.
[0051]
Next, as shown in FIG. 4B, a sealing insulator 8 is formed around the semiconductor chip 6, the wiring 2, and the bonding wire 7 and sealed. At this time, the sealing insulator 8 is formed by, for example, transfer molding.
[0052]
Thereafter, for example, when the whole is heated from 170 ° C. to 200 ° C. and the substrate 1 is peeled in a state where the adhesive strength of the re-peeling material (thermoplastic adhesive) 102 is reduced, as shown in FIG. Semiconductor in which the wiring 2 is exposed on the surfaces of the sealing insulator 8 and the thermosetting adhesive 5 and the protruding conductor 3 is formed on the land (external connection terminal) 2A of the wiring 2 A device can be obtained. At this time, depending on the kind of the re-peeling material 102, the substrate 1 can be peeled off without heating.
[0053]
FIG. 6 is a schematic cross-sectional view for explaining the operational effects of the present embodiment.
[0054]
In the semiconductor device manufactured using the wiring board of this embodiment, when the substrate 1 is peeled off, the protruding conductor 3 is formed on the land 2A of the wiring 2 as shown in FIG. Has been. That is, when the semiconductor device is mounted on a mounting board, as shown in FIG. 6, the protruding conductors are arranged between the wiring 2 (land 2A) of the semiconductor device and the wiring (terminal) 901 of the mounting board 9. 3 intervenes. Therefore, the gap SP between the semiconductor device and the mounting substrate can be widened by the height h of the protruding conductor 3.
[0055]
Further, since the gap between the semiconductor device and the mounting substrate 9 is widened, it becomes easy to pour sealing resin. Therefore, between the wiring 2 (land 2A) of the semiconductor device and the wiring (terminal) 901 of the mounting substrate 9 It can prevent oxidation and corrosion of the connection part. Therefore, it is possible to prevent deterioration of connection reliability and electrical characteristics when the semiconductor device is mounted.
[0056]
As described above, according to the wiring board of the present embodiment, the opening 1A is provided in the substrate 1, and the protruding conductor 3 is provided in the opening 1A, whereby the external connection terminal (land) 2A. A semiconductor device in which the protruding conductor 3 is provided can be easily obtained.
[0057]
In addition, since the protruding conductor 3 is provided on the external connection terminal (land) 2A of the semiconductor device, when the semiconductor device is mounted on the mounting substrate 9, the height h of the protruding conductor 3 can be reduced. Only the gap between the semiconductor device and the mounting substrate 9 can be widened.
[0058]
Further, since the gap between the semiconductor device and the mounting substrate 9 is widened, it becomes easy to pour sealing resin. Therefore, between the wiring 2 (land 2A) of the semiconductor device and the wiring (terminal) 901 of the mounting substrate 9 It can prevent oxidation and corrosion of the connection part. Therefore, it is possible to prevent deterioration of connection reliability and electrical characteristics when the semiconductor device is mounted.
[0059]
In addition, by manufacturing a semiconductor device using the wiring board provided with the protruding conductor 3 and the second functional plating 402 on the surface thereof, the external connection terminal of the wiring 2 after peeling off the substrate (Land) The process of forming a bump or forming a bonding material on 2A can be omitted. Therefore, the manufacturing cost of the semiconductor device can be reduced.
[0060]
In the present embodiment, the substrate 1 is formed by forming a re-peeling material (thermoplastic adhesive) on the insulating base material 101. However, the present invention is not limited to this. For example, the substrate 1 is made of a single piece made of a thermoplastic resin. It goes without saying that one substrate may be used.
[0061]
Further, the re-peeling material 102 is not limited to the thermoplastic adhesive, and for example, a material whose adhesive force changes when irradiated with light may be used.
[0062]
FIG. 7 is a schematic view for explaining a modification of the embodiment, and FIGS. 7A and 7B are cross-sectional views for explaining a method of manufacturing a wiring board.
[0063]
In the embodiment, as an example of the method for manufacturing the wiring board, the conductor film 2 ′ is bonded to the substrate 1 on which the opening 1A is formed. However, the present invention is not limited to this, and various methods can be used. it can. For example, first, as shown in FIG. 7A, the substrate 1 and the conductor film 2 ′ are bonded together, and the conductor film 2 ′ of the substrate 1 is bonded as shown in FIG. 7B. The opening 1A may be formed from the back surface of the surface. At this time, the opening 1A is formed by irradiating laser light such as a carbon dioxide laser.
[0064]
8 and 9 are schematic views for explaining an application example of the above embodiment. FIG. 8 (a) is a plan view showing a schematic configuration of the wiring board, and FIG. 8 (b) is FIG. 8 (a). FIG. 9A is a plan view of a semiconductor device manufactured using the wiring board shown in FIG. 8A, and FIG. 9B is a cross-sectional view taken along line BB ′ of FIG. It is sectional drawing in CC 'line.
[0065]
In the embodiment, as shown in FIG. 1A, a wiring board for manufacturing an LGA type semiconductor device in which the external connection terminals (lands) 2A of the wiring 2 are arranged in an array is taken as an example. However, the present invention is not limited to this. For example, it can also be used as a wiring board for manufacturing a QFN type semiconductor device.
[0066]
When the wiring board as described in the embodiment is used for manufacturing the QFN type semiconductor device, as shown in FIGS. 8A and 8B, the semiconductor chip on the substrate 1 is mounted. The wiring 2 is provided so as to surround the outer periphery of the area AR1. For example, an island 2B is provided in the area AR1 where the semiconductor chip is mounted.
[0067]
Also at this time, as shown in FIG. 8B, an opening is provided in the lower portion of the wiring 2 of the substrate 1, and a protruding conductor 3 is provided in the opening.
[0068]
Using a wiring board as shown in FIGS. 8A and 8B, as shown in FIGS. 9A and 9B, a semiconductor chip 6 is bonded onto the island 2B, and After the external electrode 601 of the semiconductor chip 6 and the wiring 2 are electrically connected with a bonding wire 7 and sealed with a sealing insulator 8, the substrate 1 is peeled off, and then the protruding shape is formed on the wiring 2. A semiconductor device in which the conductor 3 is formed can be obtained.
[0069]
Further, the wiring board used when manufacturing the QFN type semiconductor device is not limited to the procedure described in the above embodiment. For example, a lead frame in which a lead is formed by punching a copper plate is bonded to the substrate 1. Good. Also in this case, the opening 1A is formed in the substrate 1 before or after the lead frame is pasted, and the protruding conductor 3 is formed in the opening 1A. A semiconductor device in which the protruding conductor 3 is formed can be easily obtained.
[0070]
The present invention has been specifically described above based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. is there.
[0071]
【The invention's effect】
The effects obtained by typical ones of the inventions disclosed in the present invention will be briefly described as follows.
[0072]
(1) In a semiconductor device in which a wiring board provided with wiring on the surface of a substrate is used, a semiconductor chip is mounted on the wiring, and then the substrate is peeled off to expose the wiring. When mounted, the semiconductor device and the mounting substrate can be easily sealed with an insulator.
[0073]
(2) In a semiconductor device in which a wiring board provided with wiring on the surface of a substrate is used, a semiconductor chip is mounted on the wiring, and then the substrate is peeled off to expose the wiring. It is possible to prevent deterioration of connection reliability and electrical characteristics when mounting.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a schematic configuration of a wiring board according to an embodiment of the present invention, FIG. 1 (a) is a plan view of the wiring board, and FIG. 1 (b) is AA in FIG. 1 (a). It is sectional drawing in a line.
FIG. 2 is a schematic diagram showing a schematic configuration of the wiring board of the present embodiment, and is a partially enlarged sectional view of FIG.
3A and 3B are schematic views for explaining a method of manufacturing a wiring board according to the present embodiment, in which FIG. 3A is a cross-sectional view of a process of forming an opening in the substrate, and FIG. 3B is a conductor on the substrate. FIG. 3C is a cross-sectional view of the step of forming the protruding conductors, and FIG. 3D is a cross-sectional view of the step of patterning the conductive film.
4A and 4B are schematic views for explaining a method of manufacturing a semiconductor device using the wiring board according to the present embodiment. FIG. 4A is a cross-sectional view of a process for mounting a semiconductor chip, and FIG. It is sectional drawing of the process of sealing a semiconductor chip.
FIG. 5 is a schematic view for explaining a method of manufacturing a semiconductor device using the wiring board of the present embodiment, and is a cross-sectional view of the semiconductor device after the substrate is peeled off.
FIG. 6 is a schematic cross-sectional view for explaining the function and effect of the present embodiment.
7A and 7B are schematic views for explaining a modification of the embodiment, and FIGS. 7A and 7B are cross-sectional views for explaining a method of manufacturing a wiring board.
8A and 8B are schematic diagrams for explaining an application example of the embodiment, in which FIG. 8A is a plan view showing a schematic configuration of a wiring board, and FIG. 8B is a cross-sectional view taken along line B- in FIG. It is sectional drawing in a B 'line.
9 is a schematic diagram for explaining an application example of the embodiment, and FIG. 9A is a plan view showing a schematic configuration of a semiconductor device using the wiring board shown in FIG. 8A; FIG. 9 (b) is a cross-sectional view taken along line CC ′ of FIG. 9 (a).
10A and 10B are schematic views showing a schematic configuration of a conventional wiring board, in which FIG. 10A is a plan view of the wiring board, and FIG. 10B is a cross-sectional view taken along the line DD ′ of FIG. FIG.
FIG. 11 is a schematic diagram showing a schematic configuration of a conventional wiring board, and is an enlarged cross-sectional view of FIG.
12A and 12B are schematic views for explaining a method of manufacturing a semiconductor device using the wiring board of the present embodiment. FIG. 12A is a cross-sectional view of a process of mounting a semiconductor chip, and FIG. It is sectional drawing of the process of sealing a semiconductor chip.
13A and 13B are schematic views for explaining a method for manufacturing a semiconductor device using the wiring board of the present example. FIG. 13A is a cross-sectional view of the semiconductor device after the substrate is peeled off, and FIG. b) is a cross-sectional view of a process of forming functional plating on the surface of the wiring.
FIG. 14 is a schematic cross-sectional view for explaining a problem.
[Explanation of symbols]
1 Substrate
101 Insulating substrate
102 Removable material (thermoplastic adhesive)
1A Opening of substrate
2 Wiring
2A land (external connection terminal)
2B Island
3 Protruding conductor
401 First function plating
402 Second function plating
5 Thermosetting adhesive
6 Semiconductor chip
601 External electrode of semiconductor chip
7 Bonding wire
8 Sealing insulator
9 Mounting board
901 Wiring (terminal) of mounting board
SP Semiconductor device and mounting board gap

Claims (6)

基板の表面に配線が設けられており、前記基板の前記配線が設けられた面に半導体チップを実装した後、前記基板をはがして半導体装置を形成するための配線板であって、
前記基板は、前記配線の一部と重なる領域が開口しており、
前記開口部内に、突起状の導体が設けられていることを特徴とする配線板。
And wiring is provided on the surface of the substrate, after the wiring of the substrate mounted with the semiconductor chip on the surface provided with a wiring board for forming a semiconductor device peel the substrate,
The substrate has an opening that overlaps a part of the wiring,
In the opening, the wiring board, wherein the protruding guide body is provided.
前記突起状の導体の表面に、接合材が設けられていることを特徴とする請求項1に記載の配線板。  The wiring board according to claim 1, wherein a bonding material is provided on a surface of the protruding conductor. 前記基板は、平板状の基材の表面に、加熱若しくは光の照射によって接着力が低下する再剥離材が設けられており、前記配線は、前記再剥離材上に設けられていることを特徴とする請求項1または請求項2に記載の配線板。The substrate is provided with a re-peeling material whose adhesion is lowered by heating or light irradiation on the surface of a flat base material, and the wiring is provided on the re-peeling material. The wiring board according to claim 1 or 2. 基板の表面に配線が形成された配線板上に半導体チップを接着し、前記半導体チップの外部電極と前記配線とを電気的に接続し、前記半導体チップの周囲を絶縁体で封止した後、
前記基板をはがして前記配線を露出させる半導体装置の製造方法であって、
前記配線板の前記基板は、前記配線の一部と重なる領域が開口しており、
前記開口部内に、突起状の導体が形成されていることを特徴とする半導体装置の製造方法。
The semiconductor chip is bonded to the wiring is formed wiring board on the surface of the substrate, and the wiring and external electrode of the semiconductor chip are electrically connected, after the periphery of the semiconductor chip is sealed with an insulator ,
A method of manufacturing a semiconductor device in which the substrate is peeled off to expose the wiring,
The substrate of the wiring board has an opening that overlaps a part of the wiring,
In the opening, a method of manufacturing a semiconductor device characterized by protruding conductors are formed.
前記配線板は、前記突起状の導体の表面に接合材が形成されていることを特徴とする請求項4に記載の半導体装置の製造方法。  The method of manufacturing a semiconductor device according to claim 4, wherein the wiring board has a bonding material formed on a surface of the protruding conductor. 前記配線板の前記基板は、平板状の基材の表面に、加熱若しくは光の照射によって接着力が低下する再剥離材が形成されていることを特徴とする請求項4または請求項5に記載の半導体装置の製造方法。The re-peeling material whose adhesive force is reduced by heating or light irradiation is formed on the surface of the flat base material on the substrate of the wiring board. Manufacturing method of the semiconductor device.
JP2002108000A 2002-04-10 2002-04-10 Wiring board and method of manufacturing semiconductor device using the same Expired - Fee Related JP3783648B2 (en)

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