JP2003303920A - Wiring plate and manufacturing method of semiconductor device using the same - Google Patents

Wiring plate and manufacturing method of semiconductor device using the same

Info

Publication number
JP2003303920A
JP2003303920A JP2002108000A JP2002108000A JP2003303920A JP 2003303920 A JP2003303920 A JP 2003303920A JP 2002108000 A JP2002108000 A JP 2002108000A JP 2002108000 A JP2002108000 A JP 2002108000A JP 2003303920 A JP2003303920 A JP 2003303920A
Authority
JP
Japan
Prior art keywords
wiring
substrate
semiconductor device
wiring board
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002108000A
Other languages
Japanese (ja)
Other versions
JP3783648B2 (en
Inventor
Satoshi Chinda
聡 珍田
Akira Matsuura
亮 松浦
Mamoru Onda
護 御田
Takayuki Yoshikazu
崇之 吉和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP2002108000A priority Critical patent/JP3783648B2/en
Publication of JP2003303920A publication Critical patent/JP2003303920A/en
Application granted granted Critical
Publication of JP3783648B2 publication Critical patent/JP3783648B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that employs a wiring board on the surface of which wirings are provided, and after having packaged semiconductor chips onto the wiring, detaches the board to expose the wirings which facilitates the sealing off the gap between the semiconductor device and the packaging plate with an insulator when the semiconductor device is packaged onto the packaging board. <P>SOLUTION: The plate is a wiring plate, that has wirings (conductor pattern) on the surface of a board, and after having packaged semiconductor chips onto the surface of the board where the wirings are arranged, detaches the board to form a semiconductor device. The board has openings that overlap with a portion of the wirings and the opening is provided with a projecting conductor (bump). <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、配線板及びその製
造方法、ならびに配線板を用いた半導体装置に関し、特
に、外部接続端子が表面に露出した状態の半導体装置を
製造するための配線板に適用して有効な技術に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board, a method for manufacturing the wiring board, and a semiconductor device using the wiring board, and more particularly to a wiring board for manufacturing a semiconductor device in which external connection terminals are exposed on the surface. It relates to technology that is effective when applied.

【0002】[0002]

【従来の技術】従来、LGA(Land Grid Array)型の
半導体装置を製造するときには、例えば、ポリイミドテ
ープなどの絶縁基板の両面に配線を設けた配線板が用い
られている。
2. Description of the Related Art Conventionally, when manufacturing an LGA (Land Grid Array) type semiconductor device, a wiring board having wiring on both sides of an insulating substrate such as a polyimide tape is used.

【0003】前記配線板は、例えば、前記絶縁基板の第
1主面に、半導体チップの外部電極と接続される配線が
設けられている。また、前記絶縁基板の前記第1主面の
裏面(第2主面)には、実装基板の配線(端子)と接続
するための外部接続端子(ランド)が設けられている。
このとき、前記絶縁基板の第1主面の配線と第2主面の
ランドとは、例えば、ビアにより電気的に接続されてい
る。
In the wiring board, for example, wirings connected to the external electrodes of the semiconductor chip are provided on the first main surface of the insulating substrate. Further, an external connection terminal (land) for connecting to a wiring (terminal) of the mounting board is provided on the back surface (second main surface) of the first main surface of the insulating substrate.
At this time, the wiring on the first main surface and the land on the second main surface of the insulating substrate are electrically connected by, for example, vias.

【0004】しかしながら、前記絶縁基板の両面に配線
を形成する場合、製造コストがかかる。また、前記配線
板が厚くなり、半導体装置の小型化が難しい。
However, when wiring is formed on both surfaces of the insulating substrate, manufacturing costs are high. Further, the wiring board becomes thick, and it is difficult to downsize the semiconductor device.

【0005】そこで、近年では、図10(a)及び図1
0(b)に示すように、テープ状の基板1の表面に配線
2を設けた配線板を用いて、前記LGA型の半導体装置
を製造する方法が提案されている。
Therefore, in recent years, FIG. 10 (a) and FIG.
As shown in FIG. 0 (b), there has been proposed a method of manufacturing the LGA type semiconductor device using a wiring board in which wiring 2 is provided on the surface of a tape-shaped substrate 1.

【0006】このとき、前記基板1は、例えば、QFN
(Quad Flat Non-leaded package)型の半導体装置を製
造するときに、封止用絶縁体の漏れを防ぐために用いら
れる基板であり、例えば、図11に示すように、ポリイ
ミドテープなどの絶縁基材101の表面に再剥離材10
2が設けられている。ここで、前記再剥離剤102は、
例えば、熱可塑性接着剤のように、後の工程で前記配線
2をはがすことができる接着材料である。また、前記配
線2の表面には、例えば、錫めっき、錫合金めっき、金
めっきなどの第1機能めっき401が設けられている。
At this time, the substrate 1 is, for example, a QFN.
A substrate used to prevent leakage of a sealing insulator when manufacturing a (Quad Flat Non-leaded package) type semiconductor device. For example, as shown in FIG. 11, an insulating base material such as a polyimide tape is used. Removable material 10 on the surface of 101
Two are provided. Here, the removable agent 102 is
For example, it is an adhesive material such as a thermoplastic adhesive that can peel off the wiring 2 in a later step. The surface of the wiring 2 is provided with a first functional plating 401 such as tin plating, tin alloy plating, gold plating, or the like.

【0007】またこのとき、前記配線2の外部接続端子
2Aは、例えば、図10(a)のようにアレイ状に配置
されており、前記配線2の一端は、半導体チップが搭載
される領域AR1の外周を囲むように配置されている。
At this time, the external connection terminals 2A of the wiring 2 are arranged in an array, for example, as shown in FIG. 10A, and one end of the wiring 2 has an area AR1 where a semiconductor chip is mounted. Are arranged so as to surround the outer periphery of the.

【0008】また、前記基板1は、テープキャリアパッ
ケージ(TCP)に用いられる配線板の絶縁基板と同様
に、一方向に長尺なテープ状であり、図10(a)に示
したような領域AR2内のパターンが繰り返し設けられ
ている。
The substrate 1 is a tape shape elongated in one direction like the insulating substrate of a wiring board used in a tape carrier package (TCP), and has a region as shown in FIG. 10 (a). The pattern in AR2 is repeatedly provided.

【0009】図10(a)及び図10(b)に示したよ
うな配線板は、例えば、前記基板1上に、銅箔などの導
体膜を接着した後、前記導体膜をパターニングして前記
配線2を形成する。その後、必要に応じて前記配線2の
表面に前記第1機能めっき401を形成する。
In the wiring board as shown in FIGS. 10 (a) and 10 (b), for example, after a conductor film such as copper foil is adhered onto the substrate 1, the conductor film is patterned to form the wiring board. The wiring 2 is formed. Then, the first functional plating 401 is formed on the surface of the wiring 2 as needed.

【0010】図10(a)及び図10(b)に示したよ
うな配線板を用いて半導体装置を製造するときには、ま
ず、図12(a)に示すように、前記配線板の配線2上
に、例えば、熱硬化性樹脂からなる熱硬化性接着剤5を
用いて半導体チップ6を接着する。そして、前記半導体
チップ6の外部電極601と前記配線2をボンディング
ワイヤ7で接続する。
When manufacturing a semiconductor device using a wiring board as shown in FIGS. 10A and 10B, first, as shown in FIG. 12A, on the wiring 2 of the wiring board. Then, the semiconductor chip 6 is bonded by using, for example, a thermosetting adhesive 5 made of a thermosetting resin. Then, the external electrode 601 of the semiconductor chip 6 and the wiring 2 are connected by the bonding wire 7.

【0011】次に、図12(b)に示すように、前記半
導体チップ6、前記配線2、及び前記ボンディングワイ
ヤ7の周囲を封止用絶縁体8で封止する。このとき、前
記封止用絶縁体8は、例えば、トランスファモールドで
形成する。
Next, as shown in FIG. 12B, the periphery of the semiconductor chip 6, the wiring 2, and the bonding wire 7 is sealed with a sealing insulator 8. At this time, the sealing insulator 8 is formed by transfer molding, for example.

【0012】次に、例えば、前記基板1を加熱して、前
記再剥離材102の接着力を低下させた状態で前記基板
1をはがすと、図13(a)に示したように、前記配線
2が、前記熱硬化性接着剤5及び前記封止用絶縁体8の
表面に露出した状態の半導体装置を得ることができる。
このとき、前記再剥離材102の種類によっては、前記
基板1を加熱しなくてもはがすことができる。
Next, for example, when the substrate 1 is peeled off while heating the substrate 1 to reduce the adhesive force of the removable material 102, as shown in FIG. It is possible to obtain a semiconductor device in which 2 is exposed on the surfaces of the thermosetting adhesive 5 and the sealing insulator 8.
At this time, depending on the type of the removable material 102, the substrate 1 can be peeled off without heating.

【0013】このとき、前記半導体装置は、図13
(a)に示したように、前記配線2が露出した状態にな
っている。そのため、必要に応じて、図13(b)に示
すように、前記配線2の露出した面に、接合材などの第
2機能めっき402を形成する。前記第2機能めっき4
02は、例えば、錫めっき、錫合金めっき、金めっきな
どで形成する。このとき、前記第2機能めっき402
は、前記第1機能めっき401と同じ材料で形成しても
よいし、異なる材料で形成してもよい。
At this time, the semiconductor device shown in FIG.
As shown in (a), the wiring 2 is exposed. Therefore, as shown in FIG. 13B, a second functional plating 402 such as a bonding material is formed on the exposed surface of the wiring 2, if necessary. Second functional plating 4
02 is formed by, for example, tin plating, tin alloy plating, gold plating, or the like. At this time, the second functional plating 402
May be formed of the same material as the first functional plating 401 or may be formed of a different material.

【0014】[0014]

【発明が解決しようとする課題】しかしながら、前記従
来の技術では、前記半導体装置を実装基板に実装したと
きに、図14に示すように、前記半導体装置の配線2と
前記実装基板9の配線(端子)901との接続部の高さ
hが低い。そのため、前記半導体装置と前記実装基板の
隙間SPが狭く、前記隙間SPに封止樹脂を流し込むの
が難しいという問題があった。
However, in the prior art, when the semiconductor device is mounted on a mounting board, as shown in FIG. 14, the wiring 2 of the semiconductor device and the wiring of the mounting board 9 ( The height h of the connection portion with the (terminal) 901 is low. Therefore, there is a problem that the gap SP between the semiconductor device and the mounting substrate is narrow and it is difficult to pour the sealing resin into the gap SP.

【0015】また、前記半導体装置と前記実装基板の隙
間SPに封止樹脂を流し込むのが難しいので、前記半導
体装置の配線2と前記実装基板9の配線(端子)901
との接続部を封止せずに、空気中に露出させた状態にす
ることが多い。そのため、前記半導体装置の配線2と前
記実装基板9の配線(端子)901との接続部の酸化、
あるいは空気中の水分による腐食などで、前記接続部の
接続信頼性や電気的特性が劣化しやすいという問題があ
った。
Since it is difficult to pour the sealing resin into the gap SP between the semiconductor device and the mounting substrate, the wiring 2 of the semiconductor device and the wiring (terminal) 901 of the mounting substrate 9 are provided.
It is often the case that the connection part with and is not exposed and is exposed to the air. Therefore, oxidation of the connection portion between the wiring 2 of the semiconductor device and the wiring (terminal) 901 of the mounting substrate 9,
Alternatively, there is a problem that the connection reliability and the electrical characteristics of the connection portion are likely to be deteriorated due to corrosion due to moisture in the air.

【0016】本発明の目的は、基板の表面に配線が設け
られた配線板を用い、前記配線上に半導体チップを実装
した後、前記基板をはがして前記配線を露出させた半導
体装置において、前記半導体装置を実装基板に実装した
ときに、前記半導体装置と前記実装基板の間を絶縁体で
封止しやすくすることが可能な技術を提供することにあ
る。
An object of the present invention is to provide a semiconductor device in which a wiring board provided with wiring on the surface of a substrate is used, a semiconductor chip is mounted on the wiring, and then the substrate is peeled off to expose the wiring. It is an object of the present invention to provide a technique capable of facilitating sealing between the semiconductor device and the mounting substrate with an insulator when the semiconductor device is mounted on the mounting substrate.

【0017】本発明の目的は、基板の表面に配線が設け
られた配線板を用い、前記配線上に半導体チップを実装
した後、前記基板をはがして前記配線を露出させた半導
体装置において、前記半導体装置を実装基板に実装する
ときの接続信頼性や電気的特性の劣化を防ぐことが可能
な技術を提供することにある。
An object of the present invention is to provide a semiconductor device in which a wiring board provided with wiring on a surface of a substrate is used, a semiconductor chip is mounted on the wiring, and then the substrate is peeled off to expose the wiring. An object of the present invention is to provide a technique capable of preventing deterioration of connection reliability and electrical characteristics when mounting a semiconductor device on a mounting board.

【0018】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0019】[0019]

【課題を解決するための手段】本発明において開示され
る発明の概要を説明すれば、以下の通りである。
The outline of the invention disclosed in the present invention is as follows.

【0020】(1)基板の表面に配線(導体パターン)
が設けられており、前記基板の前記配線が設けられた面
に半導体チップを実装した後、前記基板をはがして半導
体装置を形成するための配線板であって、前記基板は、
前記配線の一部と重なる領域が開口しており、前記開口
部内に、突起状の導体(バンプ)が設けられている配線
板である。
(1) Wiring (conductor pattern) on the surface of the substrate
Is provided, after mounting a semiconductor chip on the surface of the substrate on which the wiring is provided, a wiring board for peeling off the substrate to form a semiconductor device, wherein the substrate is
In the wiring board, a region overlapping with a part of the wiring is opened, and a protrusion-shaped conductor (bump) is provided in the opening.

【0021】前記(1)の手段によれば、前記基板の開
口部内に、前記突起状の導体が設けられていることによ
り、前記配線板上に半導体チップを実装し、封止した
後、前記基板をはがしたときに、前記配線の露出面に前
記突起状の導体が設けられた半導体装置を得ることがで
きる。そのため、前記配線板を用いて形成した半導体装
置を実装基板に実装するときに、前記突起状の導体の高
さ分だけ、前記半導体装置と前記実装基板の隙間を広く
することができる。このとき、前記突起状の導体は、例
えば、銅、ニッケル、金、銀、錫、もしくはこれらの合
金を用いて設けることが好ましい。
According to the above-mentioned means (1), since the projecting conductor is provided in the opening of the substrate, the semiconductor chip is mounted on the wiring board and sealed, and thereafter the semiconductor chip is sealed. When the substrate is peeled off, it is possible to obtain a semiconductor device in which the protruding conductor is provided on the exposed surface of the wiring. Therefore, when mounting the semiconductor device formed using the wiring board on the mounting substrate, the gap between the semiconductor device and the mounting substrate can be widened by the height of the protruding conductor. At this time, it is preferable that the projecting conductor is provided by using, for example, copper, nickel, gold, silver, tin, or an alloy thereof.

【0022】またこのとき、前記突起状の導体の表面に
接合材が設けられていると、前記配線板を用いて半導体
装置を形成したときに、前記基板をはがした後、前記配
線の露出面に接合材を形成する工程が省略することがで
きる。このとき、前記接合材としては、例えば、錫めっ
き、錫合金めっき、金めっきを設けることが好ましい。
At this time, if a bonding material is provided on the surface of the projecting conductor, the wiring is exposed after the substrate is peeled off when a semiconductor device is formed using the wiring board. The step of forming the bonding material on the surface can be omitted. At this time, as the bonding material, for example, tin plating, tin alloy plating, or gold plating is preferably provided.

【0023】また、前記基板として、例えば、特定の条
件のもとで、前記配線との接着力が低下する材料を用い
ると、前記配線板を形成する工程及び前記半導体チップ
を実装する工程、ならびにその間の搬送工程などで前記
配線が前記基板からはがれるのを防ぐことができる。ま
た、特定の条件のもとで、前記配線との接着力を低下さ
せた状態で前記基板をはがすことができるので、前記基
板をはがした後、前記配線の表面に前記基板の残りが生
じるのを防ぐことができる。
Further, when a material whose adhesion to the wiring is reduced under a specific condition is used as the substrate, for example, the step of forming the wiring board and the step of mounting the semiconductor chip, and It is possible to prevent the wiring from being peeled off from the substrate in a transportation process or the like during that time. In addition, under a specific condition, the substrate can be peeled off in a state where the adhesive force with the wiring is reduced, so that after the substrate is peeled off, the substrate remains on the surface of the wiring. Can be prevented.

【0024】このとき、前記基板としては、例えば、加
熱することにより軟化し、接着力が低下する熱可塑性樹
脂を用いた基板が挙げられる。また、例えば、光を照射
することにより接着力が変化する材料を用いた基板を用
いることも可能である。
At this time, the substrate may be, for example, a substrate using a thermoplastic resin that is softened by heating and has a reduced adhesive force. Further, for example, a substrate using a material whose adhesive force changes by irradiation with light can be used.

【0025】またこのとき、前記基板は、単一の材料で
ある必要はなく、例えば、平板状の基材の表面に熱可塑
性樹脂を設けたものを用い、前記基板の前記熱可塑性樹
脂上に前記配線を設けてもよい。
Further, at this time, the substrate does not have to be a single material, and for example, a plate-shaped substrate provided with a thermoplastic resin on the surface thereof is used, and the substrate is coated with the thermoplastic resin. The wiring may be provided.

【0026】(2)基板の表面に配線(導体パターン)
が形成された配線板上に半導体チップを接着し、前記半
導体チップの外部電極と前記配線とを電気的に接続し、
前記半導体チップの周囲を絶縁体で封止した後、前記基
板をはがして前記配線を露出させる半導体装置の製造方
法であって、前記配線板の前記基板は、前記配線の一部
と重なる領域が開口しており、前記開口部内に、突起状
の導体(バンプ)が形成されている半導体装置の製造方
法である。
(2) Wiring (conductor pattern) on the surface of the substrate
A semiconductor chip is bonded onto a wiring board on which the external electrodes of the semiconductor chip and the wiring are electrically connected,
A method of manufacturing a semiconductor device, wherein after the periphery of the semiconductor chip is sealed with an insulator, the substrate is peeled off to expose the wiring, wherein the substrate of the wiring board has a region overlapping with a part of the wiring. This is a method of manufacturing a semiconductor device in which an opening is formed and a projecting conductor (bump) is formed in the opening.

【0027】前記(2)の手段によれば、前記基板の前
記配線の一部と重なる領域が開口しており、前記開口部
内に突起状の導体(バンプ)が形成されている配線板を
用いて半導体装置を製造することにより、前記基板をは
がした後、前記配線の露出面上に前記突起状の導体が設
けられた半導体装置を容易に得ることができる。
According to the above-mentioned means (2), a wiring board is used in which a region of the substrate which overlaps with a part of the wiring is opened, and a projecting conductor (bump) is formed in the opening. By manufacturing a semiconductor device by using the above method, it is possible to easily obtain a semiconductor device in which the protruding conductor is provided on the exposed surface of the wiring after the substrate is peeled off.

【0028】また、前記配線板を用いて製造した半導体
装置は、前記配線の露出面上に前記突起状の導体が形成
されているため、前記半導体装置を実装基板に実装する
ときに、前記突起状の導体と前記実装基板の配線(端
子)を接続させることにより、前記半導体装置と前記実
装基板の間の隙間を広くすることができる。そのため、
前記半導体装置と前記実装基板の間に絶縁体を流し込み
やすくすることができ、前記突起状の導体と前記実装基
板の配線(端子)の接続部の封止が容易になる。
Further, in the semiconductor device manufactured using the wiring board, since the protrusion-shaped conductor is formed on the exposed surface of the wiring, the protrusion when the semiconductor device is mounted on the mounting board. It is possible to widen the gap between the semiconductor device and the mounting substrate by connecting the conductors and the wiring (terminals) of the mounting substrate. for that reason,
An insulator can be easily poured between the semiconductor device and the mounting board, and the connection between the protruding conductor and the wiring (terminal) of the mounting board can be easily sealed.

【0029】また、前記突起状の導体と前記実装基板の
配線(端子)の接続部が封止になるため、前記突起状の
導体と前記実装基板の配線(端子)の接続部の酸化や腐
食を防ぐことができ、接続信頼性や電気的特性の劣化を
防ぐことができる。
Further, since the connecting portion between the projecting conductor and the wiring (terminal) of the mounting board is sealed, the connecting portion between the projecting conductor and the wiring (terminal) of the mounting board is oxidized or corroded. Can be prevented and deterioration of connection reliability and electrical characteristics can be prevented.

【0030】またこのとき、前記突起状の導体の表面に
接合材が形成されている配線板を用いると、従来の半導
体装置の製造方法のように、前記基板をはがした後で前
記接合材を形成する必要がない。そのため、前記半導体
装置の製造コストを低減することができる。
At this time, if a wiring board in which a bonding material is formed on the surface of the protruding conductor is used, the bonding material is removed after the substrate is peeled off as in the conventional semiconductor device manufacturing method. Need not be formed. Therefore, the manufacturing cost of the semiconductor device can be reduced.

【0031】また、前記基板として、例えば、特定の条
件のもとで、前記配線との接着力が低下する材料を用い
ると、前記配線板を形成する工程及び前記半導体チップ
を実装する工程、ならびにその間の搬送工程などで前記
配線が前記基板からはがれるのを防ぐことができる。ま
た、特定の条件のもとで、前記配線との接着力を低下さ
せた状態で前記基板をはがすことができるので、前記基
板をはがした後、前記配線の表面に前記基板の残りが生
じるのを防ぐことができる。
When a material whose adhesiveness to the wiring is reduced under a specific condition is used as the substrate, for example, the step of forming the wiring board and the step of mounting the semiconductor chip, and It is possible to prevent the wiring from being peeled off from the substrate in a transportation process or the like during that time. In addition, under a specific condition, the substrate can be peeled off in a state where the adhesive force with the wiring is reduced, so that after the substrate is peeled off, the substrate remains on the surface of the wiring. Can be prevented.

【0032】このとき、前記基板としては、例えば、加
熱することにより軟化し、接着力が低下する熱可塑性樹
脂を用いた基板が挙げられる。また、例えば、光を照射
することにより接着力が変化する材料を用いた基板を用
いることも可能である。
At this time, the substrate may be, for example, a substrate using a thermoplastic resin that is softened by heating and has a reduced adhesive force. Further, for example, a substrate using a material whose adhesive force changes by irradiation with light can be used.

【0033】またこのとき、前記基板は、単一の材料で
ある必要はなく、例えば、平板状の基材の表面に熱可塑
性樹脂を形成したものを用い、前記基板の前記熱可塑性
樹脂上に前記配線が形成されていてもよい。
Further, at this time, the substrate does not have to be made of a single material. For example, a plate-shaped base material having a surface on which a thermoplastic resin is formed is used, and the substrate is coated with the thermoplastic resin. The wiring may be formed.

【0034】以下、本発明について、図面を参照して実
施の形態(実施例)とともに詳細に説明する。
Hereinafter, the present invention will be described in detail with reference to the drawings together with the embodiments (embodiments).

【0035】なお、実施例を説明するための全図におい
て、同一機能を有するものは、同一符号を付け、その繰
り返しの説明は省略する。
In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

【0036】[0036]

【発明の実施の形態】(実施例)図1及び図2は、本発
明による一実施例の配線板の概略構成を示す模式図であ
り、図1(a)は配線板の平面図、図1(b)は図1
(a)のA−A’線での断面図、図2は図1(b)の部
分拡大断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment) FIGS. 1 and 2 are schematic views showing a schematic structure of a wiring board according to an embodiment of the present invention. FIG. 1 (a) is a plan view of the wiring board. Figure 1 (b) is
FIG. 2A is a sectional view taken along line AA ′ of FIG. 2A, and FIG. 2 is a partially enlarged sectional view of FIG.

【0037】図1(a)及び図1(b)、ならびに図2
において、1は基板、101は絶縁基材、102は再剥
離材(熱可塑性接着剤)、1Aは基板の開口部、2は配
線、2Aは配線のランド(外部接続端子)、3は突起状
の導体(バンプ)、401は第1機能めっき、402は
第2機能めっきである。
1 (a) and 1 (b), and FIG.
In FIG. 1, 1 is a substrate, 101 is an insulating base material, 102 is a removable material (thermoplastic adhesive), 1A is a substrate opening, 2 is wiring, 2A is wiring land (external connection terminal), and 3 is a protrusion Is a conductor (bump), 401 is a first functional plating, and 402 is a second functional plating.

【0038】本実施例の配線板は、図1(a)及び図1
(b)、ならびに図2に示すように、基板1の表面に配
線2が設けられている。このとき、前記配線2の一端に
は、ランド2Aが設けられており、前記ランド2Aがア
レイ状に配置されている。
The wiring board of this embodiment is shown in FIGS.
As shown in (b) and FIG. 2, the wiring 2 is provided on the surface of the substrate 1. At this time, a land 2A is provided at one end of the wiring 2, and the land 2A is arranged in an array.

【0039】また、前記基板1は、前記配線2のランド
2Aの下部に開口部1Aが設けられており、前記開口部
内に、前記配線2と接続された突起状の導体3が設けら
れている。このとき、前記突起状の導体3は、例えば、
銅めっきやニッケルめっきなどからなり、高さが数μm
から数十μmになるように設けられている。
In the substrate 1, an opening 1A is provided below the land 2A of the wiring 2, and a projecting conductor 3 connected to the wiring 2 is provided in the opening. . At this time, the protrusion-shaped conductor 3 is, for example,
Made of copper plating or nickel plating, with a height of several μm
To several tens of μm.

【0040】また、本実施例の配線板は、半導体チップ
を実装し、前記半導体チップの周囲を封止した後、前記
基板をはがして半導体装置を製造するための配線板であ
って、前記基板1は、例えば、図2に示したように、絶
縁基材101の表面に再剥離材102が設けられてい
る。ここで、前記再剥離材102は、例えば、熱可塑性
接着剤のように、後の工程で前記配線2をはがすことの
できる接着材料である。
The wiring board of this embodiment is a wiring board for manufacturing a semiconductor device by mounting a semiconductor chip, sealing the periphery of the semiconductor chip, and then peeling off the substrate. 1, the re-peelable material 102 is provided on the surface of the insulating base material 101, as shown in FIG. Here, the re-peelable material 102 is an adhesive material capable of peeling the wiring 2 in a later step, such as a thermoplastic adhesive.

【0041】また、図1(b)では省略しているが、前
記配線2の表面、言い換えると露出した面には、例え
ば、金めっき、錫めっき、錫合金めっきなどの第1機能
めっき401が設けられている。また、前記突起状の導
体3の表面にも、例えば、錫めっき、錫合金めっき、金
めっきなどの第2機能めっき402が設けられている。
Although not shown in FIG. 1B, a first functional plating 401 such as gold plating, tin plating or tin alloy plating is formed on the surface of the wiring 2, that is, the exposed surface. It is provided. A second functional plating 402 such as tin plating, tin alloy plating, or gold plating is also provided on the surface of the projecting conductor 3.

【0042】また、本実施例の配線板では、半導体チッ
プは、例えば、図1(a)に示した領域AR1上に搭載
される。また、前記基板1は、一方向に長尺なテープ状
であり、図1(a)に示した領域AR2内のパターンが
繰り返し設けられている。
In the wiring board of this embodiment, the semiconductor chip is mounted on the area AR1 shown in FIG. 1A, for example. The substrate 1 is in the form of a tape elongated in one direction, and the pattern in the area AR2 shown in FIG. 1A is repeatedly provided.

【0043】図3は、本実施例の配線板の製造方法を説
明するための模式図であり、図3(a)は基板に開口部
を形成する工程の断面図、図3(b)は基板に導体膜を
張り合わせる工程の断面図、図3(c)は突起状の導体
を形成する工程の断面図、図3(d)は導体膜をパター
ニングする工程の断面図である。
FIG. 3 is a schematic view for explaining the method for manufacturing a wiring board of this embodiment, FIG. 3 (a) is a sectional view of a step of forming an opening in a substrate, and FIG. FIG. 3C is a cross-sectional view of the step of laminating the conductor film on the substrate, FIG. 3C is a cross-sectional view of the step of forming a protruding conductor, and FIG. 3D is a cross-sectional view of the step of patterning the conductor film.

【0044】本実施例の配線板を製造するときには、ま
ず、例えば、図3(a)に示したように、前記絶縁基材
101の表面に前記再剥離材102が形成された基板1
に開口部1Aを形成する。このとき、前記開口部1A
は、例えば、金型を用いた打ち抜き加工で形成する。
When manufacturing the wiring board of this embodiment, first, for example, as shown in FIG. 3A, the substrate 1 in which the removable material 102 is formed on the surface of the insulating base material 101 is used.
The opening 1A is formed in the. At this time, the opening 1A
Is formed by, for example, punching using a mold.

【0045】次に、図3(b)に示すように、前記開口
部1Aが形成された基板1と導体膜2’を張り合わせ
る。このとき、前記導体膜2’は、例えば、電解銅箔や
圧延銅箔などを用い、前記基板1の前記再剥離材102
が形成された面に張り合わせる。またこのとき、前記再
剥離材102には、例えば、熱可塑性接着剤を用い、前
記基板1の温度を、例えば、200℃から260℃に加
熱して張り合わせる。
Next, as shown in FIG. 3 (b), the substrate 1 having the opening 1A formed thereon and the conductor film 2'are attached to each other. At this time, for the conductor film 2 ′, for example, an electrolytic copper foil or a rolled copper foil is used, and the removable material 102 of the substrate 1 is used.
Attach it to the surface on which was formed. At this time, for example, a thermoplastic adhesive is used for the re-peelable material 102, and the temperature of the substrate 1 is heated to, for example, 200 ° C. to 260 ° C. and laminated.

【0046】次に、図3(c)に示すように、前記基板
1の開口部1A内に、突起状の導体3を形成する。この
とき、前記突起状の導体3は、例えば、電気銅めっきや
電気ニッケルめっきなどで、高さが数μmから数十μm
になるように形成する。またこのとき、前記突起状の導
体3は、前記基板1からはがれやすくするために、前記
基板1との接触面積を小さくするのが好ましく、図3
(c)に示したように、ドーム状に形成する。
Next, as shown in FIG. 3C, a projecting conductor 3 is formed in the opening 1A of the substrate 1. At this time, the protrusion-shaped conductor 3 is, for example, electrolytic copper plating or electrolytic nickel plating and has a height of several μm to several tens μm.
To be formed. Further, at this time, it is preferable to reduce the contact area of the projecting conductor 3 with the substrate 1 so that the projecting conductor 3 can be easily peeled off from the substrate 1.
As shown in (c), it is formed in a dome shape.

【0047】次に、図3(d)に示すように、前記導体
膜2’をパターニングして配線2を形成する。このと
き、前記配線2は、例えば、サブトラクティブ法やセミ
アディティブ法などを用いて形成する。
Next, as shown in FIG. 3D, the conductor film 2'is patterned to form the wiring 2. At this time, the wiring 2 is formed by using, for example, a subtractive method or a semi-additive method.

【0048】その後、前記配線2の露出した面に、第1
機能めっき401を形成するとともに、前記突起状の導
体3の表面に第2機能めっき402を形成すると、図2
に示したような配線板を得ることができる。このとき、
前記第1機能めっき401と前記第2機能めっき402
は、同じ材料を用いて形成してもよいし、異なる材料を
用いて、それぞれの機能に最適なめっきを形成してもよ
い。
Then, the exposed surface of the wiring 2 is first
When the functional plating 401 is formed and the second functional plating 402 is formed on the surface of the protrusion-shaped conductor 3, as shown in FIG.
A wiring board as shown in can be obtained. At this time,
The first functional plating 401 and the second functional plating 402
May be formed using the same material, or different materials may be used to form the optimum plating for each function.

【0049】図4及び図5は、本実施例の配線板を用い
た半導体装置の製造方法を説明するための模式図であ
り、図4(a)は半導体チップを実装する工程の断面
図、図4(b)は半導体チップを封止する工程の断面
図、図5は基板をはがした後の半導体装置の断面図であ
る。
FIGS. 4 and 5 are schematic views for explaining a method for manufacturing a semiconductor device using the wiring board of this embodiment, and FIG. 4A is a sectional view of a process for mounting a semiconductor chip, 4B is a cross-sectional view of the step of sealing the semiconductor chip, and FIG. 5 is a cross-sectional view of the semiconductor device after the substrate is peeled off.

【0050】本実施例の配線板を用いて半導体装置を製
造するときには、まず、図4(a)に示すように、前記
配線板の配線2上に、例えば、熱硬化性接着剤5を用い
て半導体チップ6を接着する。そして、前記半導体チッ
プ6の外部電極601と前記配線2をボンディングワイ
ヤ7で電気的に接続する。このとき、図4(a)では省
略しているが、前記配線2の表面には、前記第1機能め
っき401が形成されており、前記突起状の導体3の表
面には、前記第2機能めっき402が形成されている。
When manufacturing a semiconductor device using the wiring board of this embodiment, first, as shown in FIG. 4A, for example, a thermosetting adhesive 5 is used on the wiring 2 of the wiring board. To bond the semiconductor chip 6. Then, the external electrode 601 of the semiconductor chip 6 and the wiring 2 are electrically connected by the bonding wire 7. At this time, although omitted in FIG. 4A, the first functional plating 401 is formed on the surface of the wiring 2, and the second functional plating is formed on the surface of the projecting conductor 3. The plating 402 is formed.

【0051】次に、図4(b)に示すように、前記半導
体チップ6及び前記配線2、ならびに前記ボンディング
ワイヤ7の周囲に封止用絶縁体8を形成して封止する。
このとき、前記封止用絶縁体8は、例えば、トランスフ
ァモールドで形成する。
Next, as shown in FIG. 4B, a sealing insulator 8 is formed and sealed around the semiconductor chip 6, the wiring 2, and the bonding wire 7.
At this time, the sealing insulator 8 is formed by transfer molding, for example.

【0052】その後、例えば、全体を170℃から20
0℃に加熱し、前記再剥離材(熱可塑性接着剤)102
の接着力を低下させた状態で前記基板1をはがすと、図
5に示すように、前記配線2が前記封止用絶縁体8及び
前記熱硬化性接着剤5の表面に露出し、且つ前記配線2
のランド(外部接続端子)2A上に、前記突起状の導体
3が形成された半導体装置を得ることができる。またこ
のとき、前記再剥離材102の種類によっては、加熱す
ることなく前記基板1をはがすことができる。
Thereafter, for example, the entire temperature is changed from 170 ° C. to 20 ° C.
The re-peelable material (thermoplastic adhesive) 102 is heated to 0 ° C.
When the substrate 1 is peeled off in a state where the adhesive force is reduced, as shown in FIG. 5, the wiring 2 is exposed on the surfaces of the sealing insulator 8 and the thermosetting adhesive 5, and Wiring 2
It is possible to obtain a semiconductor device in which the protruding conductor 3 is formed on the land (external connection terminal) 2A. At this time, depending on the type of the re-peelable material 102, the substrate 1 can be peeled off without heating.

【0053】図6は、本実施例の作用効果を説明するた
めの模式断面図である。
FIG. 6 is a schematic sectional view for explaining the function and effect of this embodiment.

【0054】本実施例の配線板を用いて製造した半導体
装置は、前記基板1をはがしたときに、図5に示したよ
うに、前記配線2のランド2A上に、前記突起状の導体
3が形成されている。すなわち、前記半導体装置を実装
基板に実装したときに、図6に示すように、前記半導体
装置の配線2(ランド2A)と前記実装基板9の配線
(端子)901の間に前記突起状の導体3が介在してい
る。そのため、前記突起状の導体3の高さhの分だけ、
前記半導体装置と前記実装基板の隙間SPを広くするこ
とができる。
In the semiconductor device manufactured using the wiring board of this embodiment, when the substrate 1 is peeled off, as shown in FIG. 5, the protrusion-shaped conductor is formed on the land 2A of the wiring 2. 3 is formed. That is, when the semiconductor device is mounted on a mounting board, as shown in FIG. 6, the protruding conductor is provided between the wiring 2 (land 2A) of the semiconductor device and the wiring (terminal) 901 of the mounting board 9. 3 intervenes. Therefore, only the height h of the protruding conductor 3
The gap SP between the semiconductor device and the mounting substrate can be widened.

【0055】また、前記半導体装置と前記実装基板9の
隙間を広くすることにより、封止樹脂を流し込みやすく
なるため、前記半導体装置の配線2(ランド2A)と前
記実装基板9の配線(端子)901との接続部の酸化や
腐食を防ぐことができる。そのため、前記半導体装置を
実装したときの接続信頼性や電気的特性の劣化を防ぐこ
とができる。
Further, by widening the gap between the semiconductor device and the mounting substrate 9, the sealing resin can be easily poured, so that the wiring 2 (land 2A) of the semiconductor device and the wiring (terminal) of the mounting substrate 9 can be obtained. Oxidation and corrosion of the connection portion with 901 can be prevented. Therefore, it is possible to prevent deterioration of connection reliability and electrical characteristics when the semiconductor device is mounted.

【0056】以上説明したように、本実施例の配線板に
よれば、前記基板1に開口部1Aを設け、前記開口部1
A内に前記突起状の導体3を設けることにより、外部接
続端子(ランド)2A上に突起状の導体3が設けられた
半導体装置を容易に得ることができる。
As described above, according to the wiring board of this embodiment, the opening 1A is provided in the substrate 1, and the opening 1 is formed.
By providing the protruding conductor 3 in A, it is possible to easily obtain a semiconductor device in which the protruding conductor 3 is provided on the external connection terminal (land) 2A.

【0057】また、前記半導体装置の外部接続端子(ラ
ンド)2A上に前記突起状の導体3が設けられるため、
前記半導体装置を実装基板9に実装したときに、前記突
起状導体3の高さhの分だけ、前記半導体装置と前記実
装基板9の隙間を広くすることができる。
Further, since the protruding conductor 3 is provided on the external connection terminal (land) 2A of the semiconductor device,
When the semiconductor device is mounted on the mounting substrate 9, the gap between the semiconductor device and the mounting substrate 9 can be widened by the height h of the protruding conductor 3.

【0058】また、前記半導体装置と前記実装基板9の
隙間を広くすることにより、封止樹脂を流し込みやすく
なるため、前記半導体装置の配線2(ランド2A)と前
記実装基板9の配線(端子)901との接続部の酸化や
腐食を防ぐことができる。そのため、前記半導体装置を
実装したときの接続信頼性や電気的特性の劣化を防ぐこ
とができる。
Further, by widening the gap between the semiconductor device and the mounting substrate 9, it becomes easier to pour the sealing resin. Therefore, the wiring 2 (land 2A) of the semiconductor device and the wiring (terminal) of the mounting substrate 9 are provided. Oxidation and corrosion of the connection portion with 901 can be prevented. Therefore, it is possible to prevent deterioration of connection reliability and electrical characteristics when the semiconductor device is mounted.

【0059】また、前記突起状の導体3及びその表面の
第2機能めっき402が設けられた配線板を用いて半導
体装置を製造することにより、前記基板をはがした後
で、前記配線2の外部接続端子(ランド)2A上に、バ
ンプを形成したり、接合材を形成したりする工程を省略
することができる。そのため、半導体装置の製造コスト
を低減することができる。
Further, a semiconductor device is manufactured by using a wiring board provided with the projecting conductors 3 and the second functional plating 402 on the surface thereof, so that the wiring 2 is removed after the substrate is peeled off. It is possible to omit the step of forming bumps or forming a bonding material on the external connection terminals (lands) 2A. Therefore, the manufacturing cost of the semiconductor device can be reduced.

【0060】また、本実施例では、前記基板1は、絶縁
基材101上に再剥離材(熱可塑性接着剤)を形成した
ものを用いているが、これに限らず、例えば、熱可塑性
樹脂からなる単一の基板を用いてもよいことは言うまで
もない。
Further, in the present embodiment, the substrate 1 uses the releasable material (thermoplastic adhesive) formed on the insulating base material 101, but the present invention is not limited to this. For example, a thermoplastic resin may be used. It goes without saying that a single substrate consisting of

【0061】また、前記再剥離材102も、前記熱可塑
性接着剤に限らず、例えば、光を照射することにより接
着力が変化する材料を用いてもよい。
Further, the re-peelable material 102 is not limited to the thermoplastic adhesive, but a material whose adhesive force changes by irradiation with light may be used.

【0062】図7は、前記実施例の変形例を説明するた
めの模式図であり、図7(a)及び図7(b)は配線板
の製造方法を説明するための断面図である。
FIG. 7 is a schematic view for explaining a modified example of the above embodiment, and FIGS. 7A and 7B are sectional views for explaining a method for manufacturing a wiring board.

【0063】前記実施例では、前記配線板の製造方法と
して、前記開口部1Aが形成された基板1に導体膜2’
を張り合わせる例を説明したが、これに限らず、種々の
方法で製造することができる。例えば、まず、図7
(a)に示すように、前記基板1と前記導体膜2’を張
り合わせておき、図7(b)に示すように、前記基板1
の前記導体膜2’が接着された面の裏面から開口部1A
を形成してもよい。このとき、前記開口部1Aは、例え
ば、炭酸ガスレーザなどのレーザ光を照射して形成す
る。
In the above-described embodiment, as a method of manufacturing the wiring board, the conductor film 2'is formed on the substrate 1 in which the opening 1A is formed.
Although the example of laminating is described, the invention is not limited to this, and it can be manufactured by various methods. For example, first,
As shown in FIG. 7A, the substrate 1 and the conductor film 2 ′ are adhered to each other, and as shown in FIG.
From the back surface of the surface to which the conductor film 2'is bonded to the opening 1A
May be formed. At this time, the opening 1A is formed by irradiating a laser beam such as a carbon dioxide gas laser.

【0064】図8及び図9は、前記実施例の応用例を説
明するための模式図であり、図8(a)は配線板の概略
構成を示す平面図、図8(b)は図8(a)のB−B’
線での断面図、図9(a)は図8(a)に示した配線板
を用いて製造した半導体装置の平面図、図9(b)は図
9(a)のC−C’線での断面図である。
8 and 9 are schematic views for explaining an application example of the above-mentioned embodiment, FIG. 8 (a) is a plan view showing a schematic structure of a wiring board, and FIG. 8 (b) is FIG. (A) BB '
9A is a plan view of a semiconductor device manufactured using the wiring board shown in FIG. 8A, and FIG. 9B is a CC ′ line of FIG. 9A. FIG.

【0065】前記実施例では、図1(a)に示したよう
に、配線2の外部接続端子(ランド)2Aがアレイ状に
配置された、LGA型の半導体装置を製造するための配
線板を例に挙げて説明したが、これに限らず、例えば、
QFN型の半導体装置を製造する配線板としても用いる
ことができる。
In the above-described embodiment, as shown in FIG. 1A, a wiring board for manufacturing an LGA type semiconductor device in which external connection terminals (lands) 2A of the wiring 2 are arranged in an array is used. Although explained using an example, the present invention is not limited to this, and for example,
It can also be used as a wiring board for manufacturing a QFN type semiconductor device.

【0066】前記実施例で説明したような配線板を、前
記QFN型の半導体装置の製造に用いるときには、図8
(a)及び図8(b)に示すように、前記基板1上の、
半導体チップを実装する領域AR1の外周を囲むように
前記配線2を設ける。また、前記半導体チップを実装す
る領域AR1には、例えば、アイランド2Bを設けてお
く。
When the wiring board as described in the above embodiment is used for manufacturing the QFN type semiconductor device, as shown in FIG.
As shown in FIGS. 8A and 8B, on the substrate 1,
The wiring 2 is provided so as to surround the outer periphery of the area AR1 on which the semiconductor chip is mounted. Further, for example, an island 2B is provided in the area AR1 on which the semiconductor chip is mounted.

【0067】このときも、図8(b)に示すように、前
記基板1の、前記配線2の下部に開口部を設け、前記開
口部内に突起状の導体3を設けておく。
At this time also, as shown in FIG. 8B, an opening is provided in the substrate 1 below the wiring 2, and a projecting conductor 3 is provided in the opening.

【0068】図8(a)及び図8(b)に示したような
配線板を用い、図9(a)及び図9(b)に示すよう
に、前記アイランド2B上に半導体チップ6を接着し、
前記半導体チップ6の外部電極601と前記配線2とを
ボンディングワイヤ7で電気的に接続し、封止用絶縁体
8で封止した後、前記基板1をはがせば、前記配線2上
に前記突起状の導体3が形成された半導体装置を得るこ
とができる。
Using the wiring board as shown in FIGS. 8A and 8B, the semiconductor chip 6 is bonded onto the island 2B as shown in FIGS. 9A and 9B. Then
When the external electrode 601 of the semiconductor chip 6 and the wiring 2 are electrically connected by the bonding wire 7 and sealed by the sealing insulator 8, and then the substrate 1 is peeled off, the protrusions are formed on the wiring 2. It is possible to obtain a semiconductor device in which the striped conductor 3 is formed.

【0069】また、QFN型の半導体装置を製造すると
きに用いる配線板は、前記実施例で説明したような手順
に限らず、例えば、銅板を打ち抜いてリードを形成した
リードフレームを前記基板1に張り合わせてもよい。こ
の場合も、前記リードフレームを張り合わせる前、もし
くは貼り合わせた後に、前記基板1に開口部1Aを形成
し、前記開口部1A内に前記突起状の導体3を形成する
ことにより、配線2上に突起状の導体3が形成された半
導体装置を容易に得ることができる。
Further, the wiring board used when manufacturing the QFN type semiconductor device is not limited to the procedure described in the above embodiment, and for example, a lead frame formed by punching a copper plate to form leads is formed on the substrate 1. You may stick them together. Also in this case, the opening 1A is formed in the substrate 1 before the lead frames are bonded to each other or after the lead frames are bonded to each other, and the projecting conductor 3 is formed in the opening 1A. It is possible to easily obtain a semiconductor device in which the protruding conductor 3 is formed.

【0070】以上、本発明を、前記実施例に基づき具体
的に説明したが、本発明は、前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲において、種々
変更可能であることはもちろんである。
Although the present invention has been specifically described based on the above embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

【0071】[0071]

【発明の効果】本発明において開示される発明のうち、
代表的なものによって得られる効果を簡単に説明すれ
ば、以下の通りである。
Of the inventions disclosed in the present invention,
The effects obtained by the representative ones will be briefly described as follows.

【0072】(1)基板の表面に配線が設けられた配線
板を用い、前記配線上に半導体チップを実装した後、前
記基板をはがして前記配線を露出させた半導体装置にお
いて、前記半導体装置を実装基板に実装したときに、前
記半導体装置と前記実装基板の間を絶縁体で封止しやす
くすることができる。
(1) In a semiconductor device in which a wiring board provided with wiring on the surface of a substrate is used, a semiconductor chip is mounted on the wiring, and then the substrate is peeled off to expose the wiring, the semiconductor device is When mounted on a mounting board, it is possible to facilitate sealing between the semiconductor device and the mounting board with an insulator.

【0073】(2)基板の表面に配線が設けられた配線
板を用い、前記配線上に半導体チップを実装した後、前
記基板をはがして前記配線を露出させた半導体装置にお
いて、前記半導体装置を実装基板に実装するときの接続
信頼性や電気的特性の劣化を防ぐことができる。
(2) In a semiconductor device in which a wiring board having wirings provided on the surface of a substrate is used, a semiconductor chip is mounted on the wirings, and then the substrate is peeled off to expose the wirings. It is possible to prevent deterioration of connection reliability and electrical characteristics when mounting on a mounting board.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による一実施例の配線板の概略構成を示
す模式図であり、図1(a)は配線板の平面図、図1
(b)は図1(a)のA−A’線での断面図である。
FIG. 1 is a schematic diagram showing a schematic configuration of a wiring board of an embodiment according to the present invention, FIG. 1 (a) is a plan view of the wiring board, and FIG.
1B is a sectional view taken along the line AA ′ of FIG.

【図2】本実施例の配線板の概略構成を示す模式図であ
り、図1(b)の部分拡大断面図である。
FIG. 2 is a schematic diagram showing a schematic configuration of a wiring board of the present embodiment, and is a partially enlarged cross-sectional view of FIG. 1 (b).

【図3】本実施例の配線板の製造方法を説明するための
模式図であり、図3(a)は基板に開口部を形成する工
程の断面図、図3(b)は基板に導体膜を張り合わせる
工程の断面図、図3(c)は突起状の導体を形成する工
程の断面図、図3(d)は導体膜をパターニングする工
程の断面図である。
3A and 3B are schematic diagrams for explaining the method for manufacturing a wiring board according to the present embodiment. FIG. 3A is a sectional view of a step of forming an opening in a substrate, and FIG. 3B is a conductor on the substrate. 3C is a cross-sectional view of a step of laminating films, FIG. 3C is a cross-sectional view of a step of forming a conductor having a protrusion shape, and FIG. 3D is a cross-sectional view of a step of patterning a conductor film.

【図4】本実施例の配線板を用いた半導体装置の製造方
法を説明するための模式図であり、図4(a)は半導体
チップを実装する工程の断面図、図4(b)は半導体チ
ップを封止する工程の断面図である。
4A and 4B are schematic views for explaining a method for manufacturing a semiconductor device using the wiring board of the present embodiment, FIG. 4A is a cross-sectional view of a process of mounting a semiconductor chip, and FIG. It is sectional drawing of the process of sealing a semiconductor chip.

【図5】本実施例の配線板を用いた半導体装置の製造方
法を説明するための模式図であり、基板をはがした後の
半導体装置の断面図である。
FIG. 5 is a schematic view for explaining the method for manufacturing a semiconductor device using the wiring board of the present embodiment, which is a cross-sectional view of the semiconductor device after the substrate is peeled off.

【図6】本実施例の作用効果を説明するための模式断面
図である。
FIG. 6 is a schematic cross-sectional view for explaining the function and effect of this embodiment.

【図7】前記実施例の変形例を説明するための模式図で
あり、図7(a)及び図7(b)は、配線板の製造方法
を説明するための断面図である。
FIG. 7 is a schematic diagram for explaining a modified example of the embodiment, and FIGS. 7 (a) and 7 (b) are cross-sectional views for explaining a method for manufacturing a wiring board.

【図8】前記実施例の応用例を説明するための模式図で
あり、図8(a)は配線板の概略構成を示す平面図、図
8(b)は図8(a)のB−B’線での断面図である。
8A and 8B are schematic views for explaining an application example of the embodiment, FIG. 8A is a plan view showing a schematic configuration of a wiring board, and FIG. 8B is a B- of FIG. 8A. It is sectional drawing in a B'line.

【図9】前記実施例の応用例を説明するための模式図で
あり、図9(a)は図8(a)に示した配線板を用いた
半導体装置の概略構成を示す平面図、図9(b)は図9
(a)のC−C’線での断面図である。
FIG. 9 is a schematic diagram for explaining an application example of the embodiment, and FIG. 9 (a) is a plan view showing a schematic configuration of a semiconductor device using the wiring board shown in FIG. 8 (a). 9 (b) is FIG.
It is sectional drawing in the CC 'line of (a).

【図10】従来の配線板の概略構成を示す模式図であ
り、図10(a)は配線板の平面図、図10(b)は図
10(a)のD−D’線での断面図である。
FIG. 10 is a schematic diagram showing a schematic configuration of a conventional wiring board, FIG. 10 (a) is a plan view of the wiring board, and FIG. 10 (b) is a cross section taken along line DD ′ of FIG. 10 (a). It is a figure.

【図11】従来の配線板の概略構成を示す模式図であ
り、図10(b)の拡大断面図である。
11 is a schematic diagram showing a schematic configuration of a conventional wiring board, and is an enlarged cross-sectional view of FIG. 10 (b).

【図12】本実施例の配線板を用いた半導体装置の製造
方法を説明するための模式図であり、図12(a)は半
導体チップを実装する工程の断面図、図12(b)は半
導体チップを封止する工程の断面図である。
12A and 12B are schematic views for explaining a method for manufacturing a semiconductor device using the wiring board of the present embodiment, FIG. 12A is a cross-sectional view of a process of mounting a semiconductor chip, and FIG. It is sectional drawing of the process of sealing a semiconductor chip.

【図13】本実施例の配線板を用いた半導体装置の製造
方法を説明するための模式図であり、図13(a)は基
板をはがした後の半導体装置の断面図、図13(b)は
配線の表面に機能めっきを形成する工程の断面図であ
る。
FIG. 13 is a schematic view for explaining the method for manufacturing a semiconductor device using the wiring board of the present embodiment, FIG. 13 (a) is a cross-sectional view of the semiconductor device after the substrate is removed, and FIG. b) is a cross-sectional view of the step of forming functional plating on the surface of the wiring.

【図14】課題を説明するための模式断面図である。FIG. 14 is a schematic cross-sectional view for explaining the problem.

【符号の説明】[Explanation of symbols]

1 基板 101 絶縁基材 102 再剥離材(熱可塑性接着剤) 1A 基板の開口部 2 配線 2A ランド(外部接続端子) 2B アイランド 3 突起状の導体 401 第1機能めっき 402 第2機能めっき 5 熱硬化性接着剤 6 半導体チップ 601 半導体チップの外部電極 7 ボンディングワイヤ 8 封止用絶縁体 9 実装基板 901 実装基板の配線(端子) SP 半導体装置と実装基板の隙間 1 substrate 101 insulating base material 102 Removable material (thermoplastic adhesive) 1A Substrate opening 2 wiring 2A land (external connection terminal) 2B island 3 protruding conductor 401 First functional plating 402 Second functional plating 5 Thermosetting adhesive 6 semiconductor chips 601 Semiconductor chip external electrodes 7 Bonding wire 8 Insulator for sealing 9 Mounting board 901 Mounting board wiring (terminals) SP Gap between semiconductor device and mounting board

───────────────────────────────────────────────────── フロントページの続き (72)発明者 御田 護 東京都千代田区大手町一丁目6番1号 日 立電線株式会社内 (72)発明者 吉和 崇之 東京都千代田区大手町一丁目6番1号 日 立電線株式会社内   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Mamoru Mita             1-6-1, Otemachi, Chiyoda-ku, Tokyo             Standing Wire Co., Ltd. (72) Inventor Takayuki Yoshikazu             1-6-1, Otemachi, Chiyoda-ku, Tokyo             Standing Wire Co., Ltd.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】基板の表面に配線(導体パターン)が設け
られており、前記基板の前記配線が設けられた面に半導
体チップを実装した後、前記基板をはがして半導体装置
を形成するための配線板であって、 前記基板は、前記配線の一部と重なる領域が開口してお
り、 前記開口部内に、突起状の導体(バンプ)が設けられて
いることを特徴とする配線板。
1. A wiring (conductor pattern) is provided on the surface of a substrate, and after mounting a semiconductor chip on the surface of the substrate on which the wiring is provided, the substrate is peeled off to form a semiconductor device. A wiring board, wherein the substrate has an opening in a region overlapping with a part of the wiring, and a protrusion-shaped conductor (bump) is provided in the opening.
【請求項2】前記突起状の導体の表面に、接合材が設け
られていることを特徴とする請求項1に記載の配線板。
2. The wiring board according to claim 1, wherein a bonding material is provided on the surface of the protruding conductor.
【請求項3】前記基板は、平板状の基材の表面に、特定
の条件のもとで接着力が低下する再剥離材が設けられて
おり、前記配線は、前記再剥離材上に設けられているこ
とを特徴とする請求項1または請求項2に記載の配線
板。
3. The substrate is provided with a re-peeling material whose adhesive force is reduced under a specific condition on a surface of a flat base material, and the wiring is provided on the re-peeling material. The wiring board according to claim 1 or 2, wherein the wiring board is provided.
【請求項4】基板の表面に配線(導体パターン)が形成
された配線板上に半導体チップを接着し、前記半導体チ
ップの外部電極と前記配線とを電気的に接続し、前記半
導体チップの周囲を絶縁体で封止した後、前記基板をは
がして前記配線を露出させる半導体装置の製造方法であ
って、 前記配線板の前記基板は、前記配線の一部と重なる領域
が開口しており、 前記開口部内に、突起状の導体(バンプ)が形成されて
いることを特徴とする半導体装置の製造方法。
4. A semiconductor chip is adhered onto a wiring board having wiring (conductor pattern) formed on the surface of a substrate, and the external electrodes of the semiconductor chip and the wiring are electrically connected to each other, and the periphery of the semiconductor chip is provided. After sealing with an insulator, a method of manufacturing a semiconductor device in which the substrate is peeled off to expose the wiring, wherein the substrate of the wiring board has an opening in a region overlapping with part of the wiring, A method for manufacturing a semiconductor device, wherein a conductor (bump) having a protrusion shape is formed in the opening.
【請求項5】前記配線板は、前記突起状の導体の表面に
接合材が形成されていることを特徴とする請求項4に記
載の半導体装置の製造方法。
5. The method of manufacturing a semiconductor device according to claim 4, wherein the wiring board has a bonding material formed on a surface of the protruding conductor.
【請求項6】前記配線板の前記基板は、平板状の基材の
表面に、特定の条件のもとで接着力が低下する再剥離材
が形成されていることを特徴とする請求項4または請求
項5に記載の半導体装置の製造方法。
6. The substrate of the wiring board is characterized in that a re-peelable material whose adhesive strength is reduced under specific conditions is formed on a surface of a flat plate-shaped base material. Alternatively, the method of manufacturing a semiconductor device according to claim 5.
JP2002108000A 2002-04-10 2002-04-10 Wiring board and method of manufacturing semiconductor device using the same Expired - Fee Related JP3783648B2 (en)

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Country Link
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009113507A1 (en) * 2008-03-10 2009-09-17 吉川工業株式会社 Semiconductor device, and communication apparatus and electronic apparatus provided with semiconductor device

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JP2001257290A (en) * 2000-03-10 2001-09-21 Sanyu Rec Co Ltd Method of manufacturing electronic component

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JPH04277636A (en) * 1991-03-05 1992-10-02 Shinko Electric Ind Co Ltd Preparation of semiconductor device
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JP2001102484A (en) * 1999-10-01 2001-04-13 Shinko Electric Ind Co Ltd Semiconductor device, carrier substrate, and manufacturing method thereof
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WO2009113507A1 (en) * 2008-03-10 2009-09-17 吉川工業株式会社 Semiconductor device, and communication apparatus and electronic apparatus provided with semiconductor device
JP2009218804A (en) * 2008-03-10 2009-09-24 Yoshikawa Kogyo Co Ltd Semiconductor device, and communication apparatus and electronic apparatus provided with the same
JP4551461B2 (en) * 2008-03-10 2010-09-29 吉川工業株式会社 Semiconductor device and communication device and electronic device provided with the same
US8384202B2 (en) 2008-03-10 2013-02-26 Yoshikawa Kogyo Co., Ltd. Semiconductor device, and communication apparatus and electronic apparatus having the same

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