JPH0394430A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0394430A
JPH0394430A JP1231133A JP23113389A JPH0394430A JP H0394430 A JPH0394430 A JP H0394430A JP 1231133 A JP1231133 A JP 1231133A JP 23113389 A JP23113389 A JP 23113389A JP H0394430 A JPH0394430 A JP H0394430A
Authority
JP
Japan
Prior art keywords
base film
semiconductor chip
resin
circuit pattern
sealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1231133A
Other languages
Japanese (ja)
Other versions
JP2840317B2 (en
Inventor
Katsuya Fukase
克哉 深瀬
Masato Tanaka
正人 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP1231133A priority Critical patent/JP2840317B2/en
Publication of JPH0394430A publication Critical patent/JPH0394430A/en
Application granted granted Critical
Publication of JP2840317B2 publication Critical patent/JP2840317B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the number of production processes by a method wherein a base film is etched and required parts such as terminal parts for external connection use out of circuit patterns are exposed so that products corresponding to uses of various products can be manufactured easily and that a collective resin sealing operation can be executed. CONSTITUTION:A semiconductor chip 16 is bonded to a die bonding part 14 which has been plated with gold or the like; the semiconductor chip 16 and circuit patterns 12 are wire-bonded; then, the semiconductor chip 16, a circuit component 22 and the like are resin-sealed. During this resin-sealing operation, only one side of a base film 10 on which the semiconductor chip 16 has been mounted is resin-sealed; bonding wires 18 and the circuit patterns 12 are resin- sealed collectively; the rear surface of an encapsulant which has been obtained is covered with the base film 10. A resist pattern 26 is formed on an exposed face of the base film 10; after that, it is etched; required parts such as terminal parts 28 for external connection use out of the circuit patterns 12 are exposed. Thereby, production operation is made easy and the number of production processes can be reduced.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体チップ及び所要の回路部品等が一体的に
樹脂封止されて提供される半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor chip and necessary circuit components are integrally sealed with resin.

（従来技術） 半導体装置は電子装置をはじめきわめて多稚類の製品に
ひろく用いられており，ＩＣ力一ドといった小形商品に
も利用されるようになっている．これら製品で用いられ
る半導体装置の実装方式としては、パッケージに半導体
チップを搭載してパッケージごと回路基板に実装するパ
ッケージ方式と、回路基板に半導体チップをじかに接続
するベアチップ方式とがある。(Prior art) Semiconductor devices are widely used in a wide variety of products including electronic devices, and are also being used in small products such as IC power devices. As mounting methods for semiconductor devices used in these products, there are a package method in which a semiconductor chip is mounted on a package and mounted on a circuit board together with the package, and a bare chip method in which the semiconductor chip is directly connected to a circuit board.

前記のパッケージ方式の場合は、パッケージ内に半導体
チップが封止されて保護されているので、取り扱いがき
わめて容易であり、実装が容易にでき、また耐環境性に
優れている等の特徴がある。In the case of the above-mentioned packaging method, the semiconductor chip is sealed and protected within the package, so it is extremely easy to handle, easy to mount, and has excellent environmental resistance. .

これに対して、ペアチップ方式は回路基板にじかに半導
体チップを接続するから、小面積で実装でき，高密度実
装が可能になるという特徴がある。On the other hand, the paired chip method connects semiconductor chips directly to the circuit board, so it can be mounted in a small area and can be mounted at high density.

（発明が解決しようとする課題） 上記のように、回路基板等に半導体チップを搭載する方
法には、パッケージ方式あるいはペアチップ方式がある
が、いずれもそれぞれ別体に作成した半導体チップ等の
回路部品を別々に実装しているため、製造工程が複雑に
なって装置の信頼性が劣ること、装置の小形化が制限さ
れること等の問題点があった。(Problem to be Solved by the Invention) As mentioned above, there are two methods for mounting semiconductor chips on circuit boards, etc.: the package method and the pair chip method. Since the devices are mounted separately, there are problems such as a complicated manufacturing process, poor reliability of the device, and restrictions on miniaturization of the device.

また，半導体チップは通常、回路基板等の接続用基板に
実装されるから、ＩＣカードのようなきわめて薄形に形
成される装置においては基板の厚さが薄形化を制限する
という問題点があった。Furthermore, since semiconductor chips are usually mounted on connection substrates such as circuit boards, there is a problem in that the thickness of the substrate limits how thin devices can be made to be, such as IC cards. there were.

そこで、本発明は上記問題点を解消すべくなされたもの
であり，その目的とするところは、半導体チップと回路
部品等を容易に一体的に搭載することができ、製造工数
を減らすことができて、製造コス１−を下げることがで
きると共に、製造プロセスを簡略化することによって不
良品の発生率を低下させ，装置の信頼性を高めることが
でき、また，装置の小形化、薄形化が達成でき、高密度
実装を可能とする半導体装置の製造方法を提供しようと
するものである。Therefore, the present invention was made to solve the above-mentioned problems, and its purpose is to easily mount a semiconductor chip and circuit components in one piece, thereby reducing the number of manufacturing steps. In addition, by simplifying the manufacturing process, it is possible to reduce the incidence of defective products and increase the reliability of the equipment. The present invention aims to provide a method for manufacturing a semiconductor device that can achieve this and enable high-density packaging.

（課題を解決するための手段） 本発明は上記し１的を達或するため次の構戊をそなえる
。(Means for Solving the Problems) In order to achieve the above object, the present invention has the following structure.

すなわち，電気的絶縁性を有するベースフィルム上に回
路パターンを設け、前記ベースフィルム上に半導体チッ
プを接合して半導体チップと前記回路パターンとをワイ
ヤボンディングによって接続し、前記ベースフィルムの
半導体チップが搭載された一方の面側を、半導体チップ
、ボンディングワイヤ、回路パターンを含めて一体的に
樹脂封止し、ベースフィルムをエッチングして、回路パ
ターンのうち外部接続用の端子部等の所要部位を露出さ
せることを特徴とする。That is, a circuit pattern is provided on a base film having electrical insulation properties, a semiconductor chip is bonded onto the base film, the semiconductor chip and the circuit pattern are connected by wire bonding, and the semiconductor chip of the base film is mounted. The semiconductor chip, bonding wires, and circuit pattern are integrally sealed with resin on one side, and the base film is etched to expose the required parts of the circuit pattern, such as terminals for external connections. It is characterized by causing

（作用） ベースフィルム上に設けたダイボンディング部に半導体
チップを接合してワイヤボンディングすることによって
回路パターンと接続する。半導体チップおよび回路パタ
ーンが一体的に樹脂封止され、ベースフイルムの所要部
位をエッチング除去することによって外部接続用の端子
部等が形成される． （実施例） 以下本発明の好適な実施例を添付図面に基づいて詳細に
説明する。(Function) The semiconductor chip is bonded to the die bonding portion provided on the base film and connected to the circuit pattern by wire bonding. The semiconductor chip and circuit pattern are integrally encapsulated with resin, and terminals for external connections are formed by etching away the required portions of the base film. (Embodiments) Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

第１図（ａ）〜（ｅ）は本発明に係る半導体装置の製造
方法を示す説明図である。FIGS. 1(a) to 1(e) are explanatory diagrams showing a method for manufacturing a semiconductor device according to the present invention.

図で１０はポリイミド等の電気的絶縁性を有するフィル
ムから成るベースフイルムで，１２はこのベースフィル
ム１０上に形或した回路パターン、１４は半導体チップ
を接合するダイボンデイング部である。In the figure, 10 is a base film made of an electrically insulating film such as polyimide, 12 is a circuit pattern formed on this base film 10, and 14 is a die bonding part for bonding a semiconductor chip.

回路パターン１２およびダイボンディング部１４は、た
とえばベースフィルム１０上に銅箔を接着し、銅箔上に
レジストパターンを形成してエッチングすることによっ
て形成することができる．ベースフィルム１０に銅箔を
接合する場合は、接着剤を用いる場合と接着剤を用いな
い場合とがある。The circuit pattern 12 and the die bonding part 14 can be formed, for example, by bonding a copper foil onto the base film 10, forming a resist pattern on the copper foil, and etching the resist pattern. When bonding the copper foil to the base film 10, an adhesive may be used or no adhesive may be used.

次に、第１図山》に示すように、金めつき等を施したダ
イボンディング部ｌ４に半導体チップ１６を接合し、半
導体チップ１６と回路パターン１２とをワイヤボンディ
ングする。１８はボンディングワイヤである。なお、回
路パターン１２上のボンディング部２０には、ボンディ
ングを確実にするためあらかじめ金めつき等を施してお
く。２２は回路パターン１２に接続した回路部品である
。Next, as shown in FIG. 1, the semiconductor chip 16 is bonded to the gold-plated die bonding portion l4, and the semiconductor chip 16 and the circuit pattern 12 are wire-bonded. 18 is a bonding wire. Note that the bonding portion 20 on the circuit pattern 12 is plated with gold or the like in advance to ensure bonding. 22 is a circuit component connected to the circuit pattern 12.

次に、上記半導体チップ１６および回路部品２２等を樹
脂封止する。この樹脂封止の際には、半導体チップ１６
が搭載されているベースフィルム１０の片面側のみを樹
脂封止し，前記ボンディングワイヤ１８および回路パタ
ーン１２を一体的に樹脂封止する。得られた封止体は、
その下面にベースフィルム１０が被覆されている６ 次に、ベースフィルム１０の露出面にレジストパターン
２６を形或する（第１図（ｄ））　．次に、ベースフィ
ルム１０をエッチングし、回路パターンｌ２のうち外部
接続用の端子部２８等の所要部位を露出させる。端子部
２８には腐食などを防止するため金めっき３０等を施す
．こうして、第１図（ｅ）に示す半導体装置が得られる
．得られた半導体装置は、第ｌ図（ａ）に示すように、
半導体チップ１６および回路部品２２、回路パターン１
２等が一体的に封止され、端子部２８等の所要部位が露
出するものとなる。Next, the semiconductor chip 16, circuit components 22, etc. are sealed with resin. During this resin sealing, the semiconductor chip 16
Only one side of the base film 10 on which is mounted is sealed with resin, and the bonding wire 18 and circuit pattern 12 are integrally sealed with resin. The obtained sealed body is
The lower surface of the base film 10 is covered with the base film 10. Next, a resist pattern 26 is formed on the exposed surface of the base film 10 (FIG. 1(d)). Next, the base film 10 is etched to expose required portions of the circuit pattern l2, such as the terminal portions 28 for external connection. The terminal portion 28 is plated with gold 30 or the like to prevent corrosion. In this way, the semiconductor device shown in FIG. 1(e) is obtained. The obtained semiconductor device, as shown in FIG. 1(a),
Semiconductor chip 16, circuit component 22, circuit pattern 1
2, etc. are integrally sealed, and required portions such as the terminal portion 28 are exposed.

なお、上記製造方法においてはベースフィルム１０上に
銅箔等の金ｇｃ層を接合し、この金属層をエッチングし
て回路パターン等を形成するが，この金属層として電解
銅箔を用いることも有効である。電解銅箔は表面が複雑
な凹凸を有する粗面として形成されるもので、粗面を封
止樹脂２４に接合する側にして樹脂封止することにより
、アンカー効果によって封止樹脂１７と回路パターン１
２とを強固に接合させることができる．なお，電解銅箔
を用いる場合は、ボンディング部２０等にはあらかじめ
平滑処理および金めつき等を施しておくのがよい。Note that in the above manufacturing method, a gold GC layer such as copper foil is bonded onto the base film 10, and this metal layer is etched to form a circuit pattern, etc., but it is also effective to use electrolytic copper foil as this metal layer. It is. The electrolytic copper foil is formed as a rough surface with complicated irregularities, and by sealing with the rough surface on the side that will be bonded to the sealing resin 24, the anchor effect will bond the sealing resin 17 and the circuit pattern. 1
2 can be firmly joined. Note that when electrolytic copper foil is used, it is preferable that the bonding portion 20 and the like be smoothed, gold plated, etc. in advance.

上記の半導体装置は、各種製品、用途に応じて設計、製
造することが容易にできるから、各種機器に搭載して効
果的に利用することができる。The above-described semiconductor device can be easily designed and manufactured according to various products and uses, and therefore can be mounted on various types of equipment and used effectively.

また、半導体チップは回路パターンに接続されているだ
けで回路基板を要しないから、装置の小形化、薄形化に
きわめて有効である。これによりＩＣカードのような小
形商品にも容易に応用利用することが可能となる． また、上記製造方法においてはワイヤボンディング法に
よって半導体チップを接続しているから、製造が容易で
あると共に、製造上の信頼性も高いという利点がある。Further, since the semiconductor chip is only connected to the circuit pattern and does not require a circuit board, it is extremely effective in making the device smaller and thinner. This makes it possible to easily apply it to small products such as IC cards. Further, in the above manufacturing method, since the semiconductor chips are connected by wire bonding, there are advantages that manufacturing is easy and manufacturing reliability is high.

また、リードフレームを等を用いる場合とくらべて回路
パターンが高密度に形成でき，高集積化を図ることがで
きるという利点がある。Further, compared to the case where a lead frame or the like is used, there is an advantage that circuit patterns can be formed with higher density and higher integration can be achieved.

なお、上記製造方法においては長尺状のベースフィルム
を用いることにより連続加工による量産が容易に可能と
なる。In addition, in the above manufacturing method, mass production by continuous processing is easily possible by using a long base film.

第２図は長尺帯状体を用いた加工例を示す。図でＩＯは
前記ベースフィルムで，ベースフィルム１０上には回路
パターンが繰り返しパターンで形成され，同時に各回路
パターンに接続して検査用ライン４０および電解めっき
の導通をとるためのバスライン４２が設けられる。FIG. 2 shows an example of processing using a long strip. In the figure, IO is the base film, and a circuit pattern is formed in a repeating pattern on the base film 10, and at the same time, a bus line 42 is provided to connect to each circuit pattern to ensure continuity of an inspection line 40 and electrolytic plating. It will be done.

回路パターン、検査用ライン４ｏ、バスライン４２はベ
ースフィルムＩＯ上に接合した銅箔をエッチングして形
成する。次いで、半導体チップを搭載し、ワイヤボンデ
ィングした後樹脂封止する．第２図はこの樹脂封止した
状態である。The circuit pattern, inspection line 4o, and bus line 42 are formed by etching the copper foil bonded onto the base film IO. Next, a semiconductor chip is mounted, wire bonded, and then resin-sealed. FIG. 2 shows this resin-sealed state.

樹脂封止した後、ベースフィルム１０をエッチングして
端子部等を露出させ、金めつき処理等を施し、不要部分
を除去して各モジュール部をベースフィルム１０から分
離する。After resin sealing, the base film 10 is etched to expose the terminal portions and the like, gold plating or the like is performed, unnecessary portions are removed, and each module portion is separated from the base film 10.

モジュール部をあらかじめ検査する場合は、樹脂封止し
た後、検査用ライン４０の短絡部分を打ち抜いて行う６
４４は回路を独立させるための打ち抜き部である。When inspecting the module part in advance, after sealing it with resin, punch out the short-circuited part of the inspection line 40.
44 is a punched portion for making the circuit independent.

この製造方法によれば、上記のようにめっき処理を含め
て連続加工ができ、製造途中で半導体装置の検査を行う
ことができ、能率的な製造方法となる． 以上、本発明について好適な実施例を挙げて種々説明し
たが、本発明はこの実施例に限定されるものではなく、
発明の精神を逸脱しない範囲内で多くの改変を施し得る
のはもちろんのことである。According to this manufacturing method, continuous processing including the plating process can be performed as described above, and the semiconductor device can be inspected during the manufacturing process, resulting in an efficient manufacturing method. The present invention has been variously explained above using preferred embodiments, but the present invention is not limited to these embodiments.
Of course, many modifications can be made without departing from the spirit of the invention.

（発明の効果） 上述したように、本発明に係る半導体装置の製造方法に
よれば、各稚製品の用途に応じた製品を製造することが
容易にでき、また一体的に樹脂封止することによって製
造工数を減らすことができて製造が容易になると共に、
製品の信頼性を向上させることができる。また、これに
よって製造コストを下げることができる。(Effects of the Invention) As described above, according to the method for manufacturing a semiconductor device according to the present invention, it is possible to easily manufacture products according to the intended use of each child product, and it is possible to integrally resin-seal the products. In addition to reducing manufacturing man-hours and making manufacturing easier,
Product reliability can be improved. This also allows manufacturing costs to be lowered.

また，半導体装置の小形化、薄形化を達或することがで
きて高密度実装を可能にする等の著効を奏する．It also has significant effects such as making semiconductor devices smaller and thinner, making high-density packaging possible.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）〜（ｅ）は本発明に係る半導体装置の製造
方法を示す説明図、第２図は長尺体を用いた製造方法を
示す説明図である。 １０・・・ベースフィルム、　　１２・・・回路パター
ン、　　１４・・・ダイボンディング部、１６・・・半
導体チップ、　　ｌ８・・・ボンディングワイヤ，　２
０・・・ボンディング部、２２・・・回路部品、　２４
・・・封止樹脂、２６　・ ２８　・ ４０　・ ４２　・ ・レジストパターン、 ・端子部、　３０・・ ・検査用ライン、 ・バスライン、　４４ ・金めつき、 ・打ち抜き部。FIGS. 1(a) to (e) are explanatory diagrams showing a method of manufacturing a semiconductor device according to the present invention, and FIG. 2 is an explanatory diagram showing a manufacturing method using a long body. DESCRIPTION OF SYMBOLS 10... Base film, 12... Circuit pattern, 14... Die bonding part, 16... Semiconductor chip, l8... Bonding wire, 2
0... Bonding part, 22... Circuit component, 24
...Sealing resin, 26, 28, 40, 42, resist pattern, terminal section, 30, inspection line, bus line, 44, gold plating, punching section.

Claims (1)

【特許請求の範囲】 １、電気的絶縁性を有するベースフィルム上に回路パタ
ーンを設け、 前記ベースフィルム上に半導体チップを接 合して半導体チップと前記回路パターンとをワイヤボン
ディングによって接続し、 前記ベースフィルムの半導体チップが搭載 された一方の面側を、半導体チップ、ボンディングワイ
ヤ、回路パターンを含めて一体的に樹脂封止し、 ベースフィルムをエッチングして、回路パ ターンのうち外部接続用の端子部等の所要部位を露出さ
せることを特徴とする半導体装置の製造方法。[Claims] 1. A circuit pattern is provided on an electrically insulating base film, a semiconductor chip is bonded onto the base film, and the semiconductor chip and the circuit pattern are connected by wire bonding, One side of the film on which the semiconductor chip is mounted is integrally sealed with resin, including the semiconductor chip, bonding wires, and circuit pattern, and the base film is etched to remove the terminal portion of the circuit pattern for external connection. 1. A method for manufacturing a semiconductor device, characterized by exposing required parts such as.
JP1231133A 1989-09-06 1989-09-06 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2840317B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1231133A JP2840317B2 (en) 1989-09-06 1989-09-06 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1231133A JP2840317B2 (en) 1989-09-06 1989-09-06 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0394430A true JPH0394430A (en) 1991-04-19
JP2840317B2 JP2840317B2 (en) 1998-12-24

Family

ID=16918799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1231133A Expired - Fee Related JP2840317B2 (en) 1989-09-06 1989-09-06 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2840317B2 (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997039482A1 (en) * 1996-04-18 1997-10-23 Tessera, Inc. Methods for manufacturing a semiconductor package
US6333252B1 (en) * 2000-01-05 2001-12-25 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
JP2002110858A (en) * 1994-03-18 2002-04-12 Hitachi Chem Co Ltd Semiconductor package and its manufacturing method
US6451627B1 (en) * 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
JP2002334950A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Method of manufacturing semiconductor package and semiconductor package
JP2002334948A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Semiconductor package, substrate for semiconductor element mounting and method of manufacturing them
JP2002334951A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Substrate for semiconductor element mounting and semiconductor package
JP2002334949A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Semiconductor package and method of manufacturing substrate for semiconductor element mounting
US6528879B2 (en) 2000-09-20 2003-03-04 Sanyo Electric Co., Ltd. Semiconductor device and semiconductor module
US6583444B2 (en) 1997-02-18 2003-06-24 Tessera, Inc. Semiconductor packages having light-sensitive chips
DE10210841A1 (en) * 2002-03-12 2003-10-16 Martin Michalk Production of electrical switches or modules comprises arranging semiconductor chips and/or electronic components on circuit support with an etching resist, structuring the resist and producing circuit structure from the circuit support
US6746897B2 (en) 1994-03-18 2004-06-08 Naoki Fukutomi Fabrication process of semiconductor package and semiconductor package
US7165316B2 (en) 1996-04-18 2007-01-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US7173336B2 (en) 2000-01-31 2007-02-06 Sanyo Electric Co., Ltd. Hybrid integrated circuit device
US7208826B2 (en) * 2000-07-05 2007-04-24 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208756A (en) * 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208756A (en) * 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6746897B2 (en) 1994-03-18 2004-06-08 Naoki Fukutomi Fabrication process of semiconductor package and semiconductor package
US7187072B2 (en) 1994-03-18 2007-03-06 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
JP2002110858A (en) * 1994-03-18 2002-04-12 Hitachi Chem Co Ltd Semiconductor package and its manufacturing method
JP2002334950A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Method of manufacturing semiconductor package and semiconductor package
JP2002334948A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Semiconductor package, substrate for semiconductor element mounting and method of manufacturing them
JP2002334951A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Substrate for semiconductor element mounting and semiconductor package
JP2002334949A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Semiconductor package and method of manufacturing substrate for semiconductor element mounting
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US7165316B2 (en) 1996-04-18 2007-01-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
WO1997039482A1 (en) * 1996-04-18 1997-10-23 Tessera, Inc. Methods for manufacturing a semiconductor package
US7095054B2 (en) 1997-02-18 2006-08-22 Tessera, Inc. Semiconductor package having light sensitive chips
US6583444B2 (en) 1997-02-18 2003-06-24 Tessera, Inc. Semiconductor packages having light-sensitive chips
US6888168B2 (en) 1997-02-18 2005-05-03 Tessera, Inc. Semiconductor package having light sensitive chips
US6451627B1 (en) * 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
US6495909B2 (en) 2000-01-05 2002-12-17 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6333252B1 (en) * 2000-01-05 2001-12-25 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US7173336B2 (en) 2000-01-31 2007-02-06 Sanyo Electric Co., Ltd. Hybrid integrated circuit device
US7276793B2 (en) 2000-01-31 2007-10-02 Sanyo Electric Co., Ltd. Semiconductor device and semiconductor module
US7208826B2 (en) * 2000-07-05 2007-04-24 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US6528879B2 (en) 2000-09-20 2003-03-04 Sanyo Electric Co., Ltd. Semiconductor device and semiconductor module
DE10210841A1 (en) * 2002-03-12 2003-10-16 Martin Michalk Production of electrical switches or modules comprises arranging semiconductor chips and/or electronic components on circuit support with an etching resist, structuring the resist and producing circuit structure from the circuit support
DE10210841B4 (en) * 2002-03-12 2007-02-08 Assa Abloy Identification Technology Group Ab Module and method for the production of electrical circuits and modules

Also Published As

Publication number Publication date
JP2840317B2 (en) 1998-12-24

Similar Documents

Publication Publication Date Title
JP3038553B2 (en) Substrate for semiconductor package, semiconductor package, and method of manufacturing the same
JP2781020B2 (en) Semiconductor device and manufacturing method thereof
JPH0394430A (en) Manufacture of semiconductor device
JP2781018B2 (en) Semiconductor device and manufacturing method thereof
US6348416B1 (en) Carrier substrate for producing semiconductor device
JP2915282B2 (en) Plastic molded integrated circuit package
JP2781019B2 (en) Semiconductor device and manufacturing method thereof
JPH07263611A (en) Lead frame for semiconductor device
JPH088385A (en) Resin sealed semiconductor device
JPH03123067A (en) Lead frame and semiconductor device
JP2798108B2 (en) Hybrid integrated circuit device
KR100199286B1 (en) Chip-scale package having pcb formed with recess
JP2813588B2 (en) Semiconductor device and manufacturing method thereof
JP2784209B2 (en) Semiconductor device
JP2822446B2 (en) Hybrid integrated circuit device
JP2813587B2 (en) Semiconductor device and manufacturing method thereof
JP2002164497A (en) Semiconductor device and method for manufacturing the same
JPH07326690A (en) Package for semiconductor device and semiconductor device
JPS60227492A (en) Electronic circuit block
JPS59152656A (en) Semiconductor device
JPH11102991A (en) Semiconductor element mounting frame
JPS6038291Y2 (en) Printed wiring board for chip mounting
JPS6242549A (en) Package for electronic part and manufacture thereof
JP4311294B2 (en) Electronic device and manufacturing method thereof
JP3059007U (en) Semiconductor package

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees