JP2813587B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2813587B2 JP2813587B2 JP1296198A JP1296198A JP2813587B2 JP 2813587 B2 JP2813587 B2 JP 2813587B2 JP 1296198 A JP1296198 A JP 1296198A JP 1296198 A JP1296198 A JP 1296198A JP 2813587 B2 JP2813587 B2 JP 2813587B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit pattern
- base film
- semiconductor chip
- semiconductor device
- surface side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体チップが一体
的に樹脂封止されて提供される半導体装置およびその製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a semiconductor chip integrally molded with a resin, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】半導体装置は電子装置をはじめきわめて
多種類の製品に広く利用されており、ＩＣカードといっ
た小形製品にも利用されるようになっている。これら製
品で用いられる半導体装置の実装方式には、パッケージ
に半導体チップを搭載してパッケージごと回路基板に実
装するパッケージ方式と、回路基板に半導体チップをじ
かに接続するベアチップ方式とがある。前記のパッケー
ジ方式の場合は、パッケージ内に半導体チップが封止さ
れて保護されているので、取り扱いがきわめて容易であ
り、実装が容易にでき、また耐環境性に優れている等の
特徴がある。これに対し、ベアチップ方式は回路基板に
じかに半導体チップを接続するから、小面積で実装で
き、高密度実装が可能になるという特徴がある。2. Description of the Related Art Semiconductor devices are widely used in a wide variety of products including electronic devices, and are also used in small products such as IC cards. Semiconductor device mounting methods used in these products include a package method in which a semiconductor chip is mounted on a package and the entire package is mounted on a circuit board, and a bare chip method in which the semiconductor chip is directly connected to the circuit board. In the case of the above-mentioned package system, since the semiconductor chip is sealed and protected in the package, it has features such as extremely easy handling, easy mounting, and excellent environmental resistance. . On the other hand, the bare chip method is characterized in that a semiconductor chip is directly connected to a circuit board, so that it can be mounted in a small area and high density mounting is possible.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記ベ
アチップ方式は装置の小型化が図れるものの、半導体チ
ップが露出するので耐環境性に劣るという問題は避けら
れない。そこで、本発明は上記問題点を解消すべくなさ
れたものであり、その目的とするところは、小型化が図
れると共に、耐環境性にも優れる半導体装置およびその
製造方法を提供するにある。However, in the bare chip method, although the size of the device can be reduced, the problem that the semiconductor chip is exposed and the environment resistance is poor is inevitable. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device which can be reduced in size and has excellent environmental resistance and a method of manufacturing the same.
【０００４】[0004]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち本発明に係る半導
体装置によれば、電気的絶縁性を有するベースフィルム
の一方の面側に回路パターンが形成され、半導体チップ
が前記回路パターンとフリップチップ法あるいはＴＡＢ
方式によって電気的に接続されて搭載され、前記ベース
フィルムの一方の面側に、前記半導体チップおよび回路
パターンが一体に樹脂封止され、前記ベースフィルムの
所要部位が除去されてベースフィルムの他方の面側に露
出する、前記回路パターンの外部接続用の端子部が形成
されていることを特徴としている。The present invention has the following arrangement to achieve the above object. That is, according to the semiconductor device of the present invention, a circuit pattern is formed on one surface side of an electrically insulating base film, and the semiconductor chip is combined with the circuit pattern by a flip chip method or TAB.
The semiconductor chip and the circuit pattern are integrally resin-sealed on one surface side of the base film, and a required portion of the base film is removed to remove the other part of the base film. A terminal portion for external connection of the circuit pattern, which is exposed on the surface side, is formed.
【０００５】半導体チップと回路パターンが樹脂封止さ
れたものであるので、小型化が図れるとともに、半導体
チップはさらに電機絶縁性を有するフィルムによって被
覆されてもいるので耐環境性に優れる。[0005] Since the semiconductor chip and the circuit pattern are sealed with a resin, miniaturization can be achieved, and the semiconductor chip is further covered with a film having electric insulation, so that it has excellent environmental resistance.
【０００６】また本発明に係る半導体装置の製造方法で
は、電気的絶縁性を有するベースフィルムの一方の面側
に回路パターンを形成する工程と、該回路パターンが形
成されたベースフィルム面側に半導体チップをフリップ
チップ法あるいはＴＡＢ方式によって電気的に接続して
搭載する工程と、前記ベースフィルムの半導体チップが
搭載された一方の面側に、前記半導体チップおよび回路
パターンを一体に樹脂封止する工程と、前記ベースフィ
ルムの所要部位をエッチングして、ベースフィルムの他
方の面側に前記回路パターンの外部接続用の端子部を露
出させる工程とを含むことを特徴としている。ベースフ
ィルムをそのまま残すので、耐環境性に優れる半導体装
置を簡易な方法で製造できる。In a method of manufacturing a semiconductor device according to the present invention, a step of forming a circuit pattern on one surface of an electrically insulating base film and a step of forming a semiconductor pattern on the surface of the base film on which the circuit pattern is formed are performed. A step of electrically connecting and mounting the chip by a flip chip method or a TAB method; and a step of integrally resin-sealing the semiconductor chip and the circuit pattern on one surface side of the base film on which the semiconductor chip is mounted. And etching a required portion of the base film to expose a terminal portion for external connection of the circuit pattern on the other surface side of the base film. Since the base film is left as it is, a semiconductor device having excellent environmental resistance can be manufactured by a simple method.
【０００７】[0007]
【発明の実施の形態】以下に本発明の好適な実施の形態
を添付図面に基づいて詳細に説明する。図１は本発明に
係る半導体装置の製造方法を示す説明図である。この製
造方法ではＦＰＣ（Flexible printed circuit）を用い
て製造することを特徴とする。図１（ａ）はベースフィ
ルム３０に回路パターン１２を形成してＦＰＣを形成し
た状態を示す。ベースフィルム３０にはポリイミド等の
電気的絶縁性を有するフィルムを用いる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an explanatory view showing a method for manufacturing a semiconductor device according to the present invention. This manufacturing method is characterized by manufacturing using an FPC (Flexible printed circuit). FIG. 1A shows a state in which the circuit pattern 12 is formed on the base film 30 to form an FPC. As the base film 30, a film having electrical insulation such as polyimide is used.
【０００８】次に、回路パターン１２に半導体チップ１
８及び回路部品２０を搭載する（図１（ｂ））。半導体
チップ１８は上記実施例と同様にフリップチップ法によ
って接続する。このため、半導体チップ１８にはあらか
じめバンプ１９を形成し、回路パターン１２のボンディ
ング部に位置合わせして接続する。次に、半導体チップ
１８が搭載されているベースフィルム３０の片面側を樹
脂封止する（図１（ｃ））。Next, the semiconductor chip 1 is added to the circuit pattern 12.
8 and the circuit component 20 are mounted (FIG. 1B). The semiconductor chip 18 is connected by the flip chip method as in the above embodiment. For this purpose, bumps 19 are formed on the semiconductor chip 18 in advance, and are connected to the bonding portions of the circuit pattern 12 while being aligned. Next, one side of the base film 30 on which the semiconductor chip 18 is mounted is resin-sealed (FIG. 1C).
【０００９】次に、ベースフィルム３０を部分的にエッ
チング除去し、回路パターン１２のうち端子部等の必要
個所を露出させる。図１（ｄ）で２４はベースフィルム
３０を除去して形成した端子部である。端子部２４には
接点の信頼性を維持するため金めっき等を施す。こうし
て、半導体チップおよび所要の回路部品が一体的に樹脂
封止された半導体装置が得られる。この実施例の半導体
装置は、回路パターン１２がベースフィルム３０によっ
て被覆され、ベースフィルム３０が前述した保護コーテ
ィングを兼ねている。Next, the base film 30 is partially etched away to expose necessary portions of the circuit pattern 12 such as terminals. In FIG. 1D, reference numeral 24 denotes a terminal portion formed by removing the base film 30. The terminal portion 24 is plated with gold or the like to maintain the reliability of the contact. Thus, a semiconductor device in which the semiconductor chip and required circuit components are integrally sealed with resin is obtained. In the semiconductor device of this embodiment, the circuit pattern 12 is covered with a base film 30, and the base film 30 also serves as the above-described protective coating.
【００１０】上記実施例では、フリップチップ法によっ
て半導体チップを接続したが、ＴＡＢ方式によって半導
体チップを接続する場合も同様にして製造することがで
きる（図示せず）。なお、ＦＰＣを形成する際の金属層
としては、表面が粗面に形成される電解銅箔が使用でき
る。電解銅箔を使用することにより回路パターンと封止
樹脂２２とが強固に接合できるという利点がある。この
ＦＰＣを用いる例において、フープ材からなるＦＰＣを
用いることにより連続加工が可能である。In the above embodiment, the semiconductor chips are connected by the flip chip method. However, when the semiconductor chips are connected by the TAB method, they can be manufactured in the same manner (not shown). In addition, as a metal layer at the time of forming an FPC, an electrolytic copper foil having a rough surface can be used. The use of the electrolytic copper foil has an advantage that the circuit pattern and the sealing resin 22 can be firmly joined. In this example using FPC, continuous processing is possible by using FPC made of hoop material.
【００１１】以上の実施例で説明した半導体装置の製造
方法によれば、各種製品、用途に応じた機能を有する半
導体装置を製造することが容易にでき、各種機器に搭載
して所要の機能を発揮させることができる。また、得ら
れた半導体装置を単体としてみた場合、半導体チップは
回路パターンに接続されているのみで、回路基板を使用
しないから、装置の小形化、薄型化にきわめて有効であ
る。これにより、ＩＣカードのような小形製品にも容易
に応用利用することが可能になる。According to the method of manufacturing a semiconductor device described in the above embodiments, a semiconductor device having a function corresponding to various products and applications can be easily manufactured, and a required function can be mounted on various devices. Can be demonstrated. Further, when the obtained semiconductor device is viewed as a single body, the semiconductor chip is only connected to the circuit pattern and does not use a circuit board, which is extremely effective for downsizing and thinning the device. This makes it possible to easily apply and use small products such as IC cards.
【００１２】また、上記製造方法においてはフリップチ
ップ法あるいはＴＡＢ方式によって半導体チップを接続
しているから、半導体チップを接続する面積が小さくて
すみ、高密度実装が可能となると共に、さらに薄形化を
図ることができる。また、半導体チップおよび回路部品
等が樹脂によって完全に封止して提供されるから耐環境
性も向上するという利点がある。以上、本発明について
好適な実施例をあげて種々説明したが、本発明はこの実
施例に限定されるものではなく、発明の精神を逸脱しな
い範囲内で多くの改変を施し得るのはもちろんのことで
ある。Further, in the above manufacturing method, since the semiconductor chips are connected by the flip chip method or the TAB method, the area for connecting the semiconductor chips can be small, high-density mounting is possible, and the thickness is further reduced. Can be achieved. Further, since the semiconductor chip and the circuit components are completely sealed and provided with the resin, there is an advantage that the environmental resistance is improved. As described above, the present invention has been described variously with preferred embodiments, but the present invention is not limited to these embodiments, and it is needless to say that many modifications can be made without departing from the spirit of the invention. That is.
【００１３】[0013]
【発明の効果】本発明に係る半導体装置では、半導体チ
ップと回路パターンが樹脂封止されたものであるので、
小型化が図れるとともに、半導体チップはさらに電機絶
縁性を有するフィルムによって被覆されてもいるので耐
環境性に優れる。また本発明方法では、ベースフィルム
をそのまま残すので、耐環境性に優れる半導体装置を簡
易な方法で製造できる。In the semiconductor device according to the present invention, the semiconductor chip and the circuit pattern are sealed with resin.
In addition to miniaturization, the semiconductor chip is further covered with a film having electrical insulation, so that it has excellent environmental resistance. In the method of the present invention, since the base film is left as it is, a semiconductor device having excellent environmental resistance can be manufactured by a simple method.
【図１】図１は半導体装置の製造方法の実施例を示す説
明図である。FIG. 1 is an explanatory view showing an embodiment of a method for manufacturing a semiconductor device.
１２ 回路パターン １８ 半導体チップ １９ バンプ ２０ 回路部品 ２２ 封止樹脂 ２４ 端子部 ３０ ベースフィルム DESCRIPTION OF SYMBOLS 12 Circuit pattern 18 Semiconductor chip 19 Bump 20 Circuit component 22 Sealing resin 24 Terminal part 30 Base film
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/12 H01L 25/00──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 23/12 H01L 25/00
Claims (2)
一方の面側に回路パターンが形成され、 半導体チップが前記回路パターンとフリップチップ法あ
るいはＴＡＢ方式によって電気的に接続されて搭載さ
れ、 前記ベースフィルムの一方の面側に、前記半導体チップ
および回路パターンが一体に樹脂封止され、 前記ベースフィルムの所要部位が除去されてベースフィ
ルムの他方の面側に露出する、前記回路パターンの外部
接続用の端子部が形成されていることを特徴とする半導
体装置。1. A circuit pattern is formed on one surface side of a base film having electrical insulation, and a semiconductor chip is mounted on the circuit pattern by being electrically connected to the circuit pattern by a flip chip method or a TAB method. For external connection of the circuit pattern, the semiconductor chip and the circuit pattern are integrally resin-sealed on one surface side of the film, and a required portion of the base film is removed and exposed on the other surface side of the base film. A semiconductor device characterized in that a terminal portion is formed.
一方の面側に回路パターンを形成する工程と、 該回路パターンが形成されたベースフィルム面側に半導
体チップをフリップチップ法あるいはＴＡＢ方式によっ
て電気的に接続して搭載する工程と、 前記ベースフィルムの半導体チップが搭載された一方の
面側に、前記半導体チップおよび回路パターンを一体に
樹脂封止する工程と、 前記ベースフィルムの所要部位をエッチングして、ベー
スフィルムの他方の面側に前記回路パターンの外部接続
用の端子部を露出させる工程とを含むことを特徴とする
半導体装置の製造方法。2. A step of forming a circuit pattern on one surface of a base film having electrical insulation, and a step of forming a semiconductor chip on a surface of the base film on which the circuit pattern is formed by a flip chip method or a TAB method. Step of electrically connecting and mounting; step of integrally resin-sealing the semiconductor chip and the circuit pattern on one surface side of the base film on which the semiconductor chip is mounted; and etching required portions of the base film. Exposing a terminal portion for external connection of the circuit pattern on the other surface side of the base film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1296198A JP2813587B2 (en) | 1998-01-26 | 1998-01-26 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1296198A JP2813587B2 (en) | 1998-01-26 | 1998-01-26 | Semiconductor device and manufacturing method thereof |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1231135A Division JP2781019B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10178043A JPH10178043A (en) | 1998-06-30 |
| JP2813587B2 true JP2813587B2 (en) | 1998-10-22 |
Family
ID=11819864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1296198A Expired - Fee Related JP2813587B2 (en) | 1998-01-26 | 1998-01-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2813587B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6313521B1 (en) | 1998-11-04 | 2001-11-06 | Nec Corporation | Semiconductor device and method of manufacturing the same |
-
1998
- 1998-01-26 JP JP1296198A patent/JP2813587B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10178043A (en) | 1998-06-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |