JP2781020B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2781020B2 JP2781020B2 JP23132389A JP23132389A JP2781020B2 JP 2781020 B2 JP2781020 B2 JP 2781020B2 JP 23132389 A JP23132389 A JP 23132389A JP 23132389 A JP23132389 A JP 23132389A JP 2781020 B2 JP2781020 B2 JP 2781020B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit pattern
- semiconductor chip
- semiconductor device
- copper foil
- electrolytic copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体チップが一体的に樹脂封止されて提供
される半導体装置及びその製造方法に関する。Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device provided with a semiconductor chip integrally sealed with a resin, and a method of manufacturing the same.
（従来の技術） 半導体チップは電子装置をはじめきわめて各種類の製
品にひろく用いられており、ICカードといった小形製品
にも利用されるようになっている。(Prior Art) Semiconductor chips are widely used in various types of products including electronic devices, and are also used in small products such as IC cards.
これら製品で用いられる半導体装置の実装方式には、
パッケージに半導体チップを搭載してパッケージごと回
路基板に実装するパッケージ方式と、回路基板に半導体
チップをじかに接続するベアチップ方式とがある。The semiconductor device mounting methods used in these products include:
There are a package system in which a semiconductor chip is mounted on a package and the entire package is mounted on a circuit board, and a bare chip system in which a semiconductor chip is directly connected to a circuit board.
前記のパッケージ方式の場合は、パッケージ内に半導
体チップが封止されて保護されているので、取り扱いが
きわめて容易であり、実装が容易にでき、また耐環境性
に優れている等の特徴がある。In the case of the above-mentioned package system, since the semiconductor chip is sealed and protected in the package, it has features such as extremely easy handling, easy mounting, and excellent environmental resistance. .
これに対し、ベアチップ方式は回路基板にじかに半導
体チップを接続するから、小面積で実装でき、高密度実
装が可能になるという特徴がある。On the other hand, the bare chip method is characterized in that a semiconductor chip is directly connected to a circuit board, so that it can be mounted in a small area and high density mounting is possible.
（発明が解決しようとする課題） しかしながら、上記ベアチップ方式にしても、半導体
チップは回路基板等の接続用基板に実装されるから、IC
カードのようなきわめて薄型に形成される装置において
は基板の厚さが薄型化を阻むという問題点があった。ま
た半導体チップが露出することから、耐環境性に劣ると
いう問題は避けられない。(Problems to be Solved by the Invention) However, even with the above bare chip method, since the semiconductor chip is mounted on a connection board such as a circuit board, an IC is required.
In an extremely thin device such as a card, there is a problem that the thickness of the substrate prevents the thinning. Further, since the semiconductor chip is exposed, the problem of poor environmental resistance is inevitable.
そこで本発明は上記問題点を解消すべくなされたもの
であり、その目的とするところは、小型化が図れ、かつ
耐環境性に優れる半導体装置およびその製造方法を提供
するにある。SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and an object of the present invention is to provide a semiconductor device which can be reduced in size and has excellent environmental resistance and a method for manufacturing the same.
（課題を解決するための手段） 本発明は上記目的を達成するため次の構成を備える。(Means for Solving the Problems) The present invention has the following configuration to achieve the above object.
すなわち、本発明に係る半導体装置では、半導体チッ
プと回路パターンとがワイヤボンディングによって電気
的に接続され、前記回路パターンの半導体チップが搭載
された一方の面側に、前記半導体チップ、ボンディング
ワイヤおよび回路パターンが封止樹脂により一体に樹脂
封止された半導体装置において、前記回路パターンは電
解銅箔がエッチングされて形成され、該電解銅箔の粗面
側となる一方の面が前記封止樹脂に接合されていること
を特徴としている。That is, in the semiconductor device according to the present invention, the semiconductor chip and the circuit pattern are electrically connected by wire bonding, and the semiconductor chip, the bonding wire, and the circuit are provided on one surface side of the circuit pattern on which the semiconductor chip is mounted. In a semiconductor device in which a pattern is integrally resin-sealed with a sealing resin, the circuit pattern is formed by etching an electrolytic copper foil, and one surface on the rough side of the electrolytic copper foil is formed in the sealing resin. It is characterized by being joined.
半導体チップの回路パターンとが樹脂封止されている
ので、小型化が図れ、耐環境性にも優れると共に、電解
銅箔からなる回路パターンの粗面側が封止樹脂に接合さ
れているので、接合が強固である。Since the circuit pattern of the semiconductor chip is resin-sealed, miniaturization and excellent environmental resistance can be achieved, and the rough side of the circuit pattern made of electrolytic copper foil is bonded to the sealing resin. Is strong.
電解銅箔からなる前記回路パターンの鏡面側となる他
方の面を前記封止樹脂の表面に露出させてもよい。The other surface on the mirror surface side of the circuit pattern made of the electrolytic copper foil may be exposed to the surface of the sealing resin.
あるいは電解銅箔からなる前記回路パターンの鏡面側
となる他方の面を、外部接続用の端子部等の所要個所を
除いて、電気的絶縁性を有する保護コーティングによっ
て被覆してもよい。この場合には一層耐環境性に優れ
る。Alternatively, the other surface on the mirror surface side of the circuit pattern made of the electrolytic copper foil may be covered with a protective coating having an electrical insulation property except for a necessary portion such as a terminal portion for external connection. In this case, the environment resistance is further improved.
また本発明に係る半導体装置の製造方法では、電気的
絶縁性を有するベースフィルム上に剥離可能に金属層が
設けられた転写フィルムの金属層をエッチングして回路
パターンを形成する工程と、外転写フィルムの回路パタ
ーンが形成された一方の面側に半導体チップを接合する
工程と、該半導体チップと前記回路パターンとをワイヤ
ボンディングによって電気的に接続する工程と、前記転
写フィルムの半導体チップが搭載された一方の面側に、
前記半導体チップ、ボンディングワイヤおよび回路パタ
ーンを一体に樹脂封止する工程と、前記ベースフィルム
を封止樹脂から剥離除去する工程とを含むことを特徴と
している。Further, in the method for manufacturing a semiconductor device according to the present invention, a step of etching a metal layer of a transfer film provided with a metal layer in a releasable manner on a base film having electrical insulation to form a circuit pattern; A step of bonding a semiconductor chip to one surface of the film on which the circuit pattern is formed, a step of electrically connecting the semiconductor chip and the circuit pattern by wire bonding, and a step of mounting the semiconductor chip of the transfer film. On one side,
The method includes a step of integrally sealing the semiconductor chip, the bonding wires and the circuit pattern with a resin, and a step of peeling and removing the base film from a sealing resin.
回路パターンを転写法によって形成するので製造が容
易である。Since the circuit pattern is formed by a transfer method, manufacture is easy.
なお、前記回路パターンの他方の面側に、外部接続用
の端子部等の所要個所を除いて、電気的絶縁性を有する
保護コーティングを施すようにすれば、耐環境性に一層
優れる半導体装置を提供できる。In addition, if a protective coating having electrical insulation properties is applied to the other surface side of the circuit pattern except for a required portion such as a terminal portion for external connection, a semiconductor device having more excellent environmental resistance can be obtained. Can be provided.
また前記金属層を有する転写フィルムとして、電気的
絶縁性を有するベースフィルムに電解銅箔を鏡面側をベ
ースフィルムに向け、粗面側を外方に向けて接合した転
写フィルムを用いることにより、封止樹脂との接合強度
の高い回路パターンを有する半導体装置を提供できる。Further, as the transfer film having the metal layer, by using a transfer film in which an electrolytic copper foil is joined to an electrically insulating base film with the mirror side facing the base film and the rough side facing outward, the sealing film is used. It is possible to provide a semiconductor device having a circuit pattern having a high bonding strength with the resin.
（実施例） 以下本発明の好適な実施例を添付図面に基づいて詳細
に説明する。Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
第１図（ａ）〜（ｅ）は本発明に係る半導体の製造方
法を示す説明図である。1 (a) to 1 (e) are explanatory views showing a method for manufacturing a semiconductor according to the present invention.
本製造方法では電気的絶縁性を有するベースフィルム
と金属層を剥離可能に接合してなる転写フィルムを用い
ることを特徴とする。This manufacturing method is characterized in that a transfer film is used in which a base film having electrical insulation properties and a metal layer are peelably joined.
第１図（ａ）は転写フィルム10の金属層13上にレジス
トを塗布し、露光、現像してレジストパターンを形成
し、金属層13をエッチングすることによってダイボンデ
ィング部13aおよび回路パターン13bを形成した状態を示
す。回路パターン13bには、半導体チップとワイヤボン
ディングされるボンディング部及び信号線路、外部接続
用の端子部等を形成する。FIG. 1A shows that a resist is applied on the metal layer 13 of the transfer film 10, exposed and developed to form a resist pattern, and the metal layer 13 is etched to form a die bonding portion 13a and a circuit pattern 13b. It shows the state where it was done. On the circuit pattern 13b, a bonding portion to be wire-bonded to the semiconductor chip, a signal line, a terminal portion for external connection, and the like are formed.
なお、上記転写フィルム10に設ける金属層13としては
電解銅箔が好適に用いられる。電解銅箔はその表面が複
雑な凹凸を有する粗面に形成されたもので、転写フィル
ム10の金属層13として用いる場合は、電解銅箔の鏡面側
をベースフィルム12に接合する。As the metal layer 13 provided on the transfer film 10, an electrolytic copper foil is preferably used. The surface of the electrolytic copper foil is formed on a rough surface having complicated irregularities. When the electrolytic copper foil is used as the metal layer 13 of the transfer film 10, the mirror side of the electrolytic copper foil is bonded to the base film 12.
電解銅箔を用いた場合は、後述する樹脂封止の際、電
解銅箔の粗面がアンカー効果によって封止樹脂と強固に
接続し、これによって回路パターン13bと封止樹脂との
密着性が良好になるという利点がある。In the case of using an electrolytic copper foil, the rough surface of the electrolytic copper foil is firmly connected to the sealing resin by an anchor effect at the time of resin encapsulation described later, whereby the adhesion between the circuit pattern 13b and the encapsulating resin is improved. There is an advantage that it becomes better.
次に、金めっき等を施したダイボンディング部13aに
半導体チップ15を接合し、通常のワイヤボンディング法
によって半導体チップ15と回路パターンとを接続する。
（第１図（ｂ））。同図で16は回路パターン13bに設け
たボンディング部である。金属層13が電解銅箔の場合は
表面が粗面となっているから、ボンディング部16にはあ
らかじめ平滑処理を施し、金めっきを施して、ボンディ
ングが確実になされるようにするとよい。18はボンディ
ングワイヤである。Next, the semiconductor chip 15 is bonded to the die bonding portion 13a that has been subjected to gold plating or the like, and the semiconductor chip 15 and the circuit pattern are connected by a normal wire bonding method.
(FIG. 1 (b)). In the figure, reference numeral 16 denotes a bonding portion provided on the circuit pattern 13b. When the metal layer 13 is an electrolytic copper foil, the surface is rough, so that the bonding portion 16 is preferably subjected to a smoothing process in advance and gold plating to ensure the bonding. 18 is a bonding wire.
次に、半導体チップ15、ボンディングワイヤ18、回路
パターン13b等を樹脂封止する。この樹脂封止の際、所
要の回路部品19はあらかじめ所定位置に接続しておき、
モジュールを形成する範囲全体を一体的に樹脂封止す
る。なお、樹脂封止する際は金属層13が設けられたベー
スフィルム12の片面側のみ封止する。（第１図
（ｃ））。Next, the semiconductor chip 15, the bonding wires 18, the circuit pattern 13b, and the like are sealed with resin. At the time of this resin sealing, necessary circuit components 19 are connected to predetermined positions in advance,
The entire area for forming the module is integrally resin-sealed. Note that, when sealing with resin, only one side of the base film 12 on which the metal layer 13 is provided is sealed. (FIG. 1 (c)).
次に、第１図（ｄ）に示すようにベースフィルム12を
剥離する。上記のように電解銅箔を用いた場合は、封止
樹脂20とダイボンディング部13a、回路パターン13bとが
強固に接合するから、回路パターン13b等を樹脂側に残
してベースフィルム12のみを簡単に剥離することができ
る。こうして、半導体チップ15および回路部品19等が一
体的に樹脂封止された半導体装置が得られる。Next, the base film 12 is peeled off as shown in FIG. When the electrolytic copper foil is used as described above, since the sealing resin 20 and the die bonding portion 13a and the circuit pattern 13b are firmly bonded, the circuit pattern 13b and the like are left on the resin side and only the base film 12 is easily formed. Can be peeled off. Thus, a semiconductor device in which the semiconductor chip 15 and the circuit component 19 and the like are integrally resin-sealed is obtained.
ベースフィルム12を剥離除去した状態で、半導体装置
の封止樹脂20の外面にはダイボンディング部13a、回路
パターン13bの表面が露出する。得られた半導体装置
は、このまま半導体チップモジュールとして、電子機器
等に実装して用いることができる。With the base film 12 removed and removed, the surfaces of the die bonding portion 13a and the circuit pattern 13b are exposed on the outer surface of the sealing resin 20 of the semiconductor device. The obtained semiconductor device can be used as it is, as a semiconductor chip module, mounted on an electronic device or the like.
なお、単体として用いる場合などの際には、第１図
（ｅ）に示すように、回路パターン13bの露出面に保護
コーティング22を施して用いる。図で24は外部接続用の
端子部である。端子部24等には腐蝕防止のため金めっき
等を施す。得られた半導体装置は端子部24等のみが露出
し、回路パターン13b、半導体チップ15、回路部品19等
がすべて封止されて提供される。In the case of using the circuit pattern 13b alone, as shown in FIG. 1 (e), a protective coating 22 is applied to the exposed surface of the circuit pattern 13b. In the figure, reference numeral 24 denotes a terminal portion for external connection. The terminal portion 24 and the like are plated with gold or the like to prevent corrosion. In the obtained semiconductor device, only the terminal portions 24 and the like are exposed, and the circuit pattern 13b, the semiconductor chip 15, the circuit components 19 and the like are all sealed and provided.
上記実施例の製造方法によれば、各種用途に応じて設
計、製造すること容易にでき、各種機器に搭載して効果
的に利用することができる。According to the manufacturing method of the above embodiment, it is easy to design and manufacture according to various uses, and it can be mounted on various devices and used effectively.
また、半導体チップおよび回路部品が一体的に封止樹
脂して製造されるから、製造プロセスが簡略化でき、製
造コストを下げることができるとともに、信頼性の高い
製品を製造することが可能となる。In addition, since the semiconductor chip and the circuit component are manufactured integrally with the sealing resin, the manufacturing process can be simplified, the manufacturing cost can be reduced, and a highly reliable product can be manufactured. .
また、転写フィルムを用いたことによって製造が容易
になると共に、回路パターンを高密度で形成することが
容易にできて高集積化された半導体チップを容易に搭載
することが可能となる。In addition, the use of the transfer film facilitates the manufacture, makes it possible to easily form a circuit pattern at high density, and makes it possible to easily mount a highly integrated semiconductor chip.
また、上記製造方法においては半導体チップをワイヤ
ボンディング法によって接続しているから、製造上の確
実性が高く、容易に製造することができる。Further, in the above-described manufacturing method, since the semiconductor chips are connected by the wire bonding method, manufacturing reliability is high, and the semiconductor chip can be easily manufactured.
また、半導体チップは回路パターンに接続されている
のみで、回路基板を要しないから、装置の小形化、薄形
化を達成することができ、ICカードのような小形製品の
製造に効果的に応用することが可能になる。Also, since the semiconductor chip is only connected to the circuit pattern and does not require a circuit board, the device can be made smaller and thinner, which is effective for manufacturing small products such as IC cards. It can be applied.
なお、上記製造方法においては、長尺状の転写フィル
ムを用いることにより、連続加工による量産が容易に可
能となる。In the above manufacturing method, mass production by continuous processing can be easily performed by using a long transfer film.
第２図は長尺状の転写フィルムを用いて加工した例で
ある。図で10は転写フィルムで、ベースフィルム上には
回路パターンが繰り返しパターンで形成され、同時に各
回路パターンに接続して検査用ライン30および電解めっ
き用の導通をとるためのバスライン32が設けられる。FIG. 2 shows an example of processing using a long transfer film. In the drawing, reference numeral 10 denotes a transfer film, on which a circuit pattern is formed in a repeating pattern on a base film, and at the same time, a test line 30 connected to each circuit pattern and a bus line 32 for providing conduction for electrolytic plating are provided. .
回路パターン、検査用ライン30、バスライン32は転写
フィルム10の金属層をエッチングして形成する。次い
で、半導体チップを搭載し、ワイヤボンディングした後
樹脂封止する。第２図はこの樹脂封止した状態である。The circuit pattern, the inspection line 30, and the bus line 32 are formed by etching the metal layer of the transfer film 10. Next, a semiconductor chip is mounted, and after wire bonding, resin sealing is performed. FIG. 2 shows this resin-sealed state.
樹脂封止した後、前述したように、ベースフィルムを
剥離除去し、保護コーティング22、金めっき等を施し、
検査用ライン30等の不要部分を除去して各モジュール部
を単体に分離する。After resin sealing, as described above, the base film is peeled and removed, and a protective coating 22 and gold plating are applied.
Unnecessary parts such as the inspection line 30 are removed to separate each module unit.
モジュール部をあらかじめ検査する場合は、樹脂封止
した後、検査用ライン30の短絡部分を打ち抜いて行う。
34は回路を独立させるための打ち抜き部である。In the case of inspecting the module portion in advance, after short-circuiting a portion of the inspection line 30 after sealing with a resin, it is performed.
Reference numeral 34 denotes a punching section for making the circuit independent.
この製造方法によれば、上記のようにめっき処理を含
めて連続加工ができ、製造途中で製品検査が容易にで
き、きわめて能率的に製造することができる。According to this manufacturing method, continuous processing including plating can be performed as described above, product inspection can be easily performed during manufacturing, and extremely efficient manufacturing can be achieved.
以上、本発明について好適な実施例を挙げて種々説明
したが、本発明はこの実施例に限定されるものではな
く、発明の精神を逸脱しない範囲内で多くの改変を施し
得るのはもちろんのことである。As described above, the present invention has been described variously with reference to the preferred embodiments. However, the present invention is not limited to these embodiments, and it goes without saying that many modifications can be made without departing from the spirit of the invention. That is.
（発明の効果） 本発明は係る半導体装置では、半導体チップと回路パ
ターンとが樹脂封止されているので、小型化、薄型化が
図れ、耐環境性にも優れると共に、電解銅箔からなる回
路パターンの粗面側が封止樹脂に接合されているので、
接合が強固である。(Effects of the Invention) In the semiconductor device according to the present invention, since the semiconductor chip and the circuit pattern are resin-sealed, the semiconductor device can be reduced in size and thickness, has excellent environmental resistance, and has a circuit made of electrolytic copper foil. Since the rough side of the pattern is joined to the sealing resin,
Bonding is strong.
電解銅箔からなる前記回路パターンの鏡面側となる他
方の面を、外部接続用の端子部等の所要個所を除いて保
護コーティングによって被覆することにより、一層耐環
境性に優れる半導体装置を提供できる。By coating the other surface of the circuit pattern made of the electrolytic copper foil on the mirror surface side with a protective coating except for a required portion such as a terminal portion for external connection, a semiconductor device having more excellent environmental resistance can be provided. .
また本発明方法によれば、回路パターンを転写法によ
って形成するので製造が容易である。Further, according to the method of the present invention, since the circuit pattern is formed by the transfer method, manufacturing is easy.
その際、転写フィルムとして、電気的絶縁性を有する
ベースフィルムに電解銅箔を鏡面側をベースフィルムに
向け、粗面側を外方に向けて接合した転写フィルムを用
いることにより、封止樹脂との接合強度の高い回路パタ
ーンを有する半導体装置を提供できる。At that time, as a transfer film, by using a transfer film in which the electrolytic copper foil is bonded to the base film having electrical insulation properties with the mirror side facing the base film and the rough side facing outwards, the sealing resin and And a semiconductor device having a circuit pattern having a high bonding strength.
第１図は本発明に係る半導体装置の製造方法を示す説明
図、第２図は長尺状の転写フィルムを用いた製造例を示
す説明図である。 10……転写フィルム、12……ベースフィルム、13……金
属層、13a……ダイボンディング部、13b……回路パター
ン、14……剥離層、16……ボンディング部、18……ボン
ディングワイヤ、19……回路部品、20……封止樹脂、22
……保護コーティング、30……検査用ライン、32……バ
スライン、34……打ち抜き部。FIG. 1 is an explanatory view showing a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is an explanatory view showing an example of manufacturing using a long transfer film. 10 transfer film, 12 base film, 13 metal layer, 13a die bonding portion, 13b circuit pattern, 14 release layer, 16 bonding portion, 18 bonding wire, 19 …… Circuit components, 20 …… Encapsulation resin, 22
… Protective coating, 30… Inspection line, 32… Bus line, 34… Punching part.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 マイク・マクシェーン アメリカ合衆国 テキサス州 78721、 オースチン、エド・ブルースタイン・ブ ールヴァード 3501 モトローラ・イン コーポレーテッド、セミコンダクター・ プロダクツ・セクター内 (72)発明者 内田 杉雄 長野県長野市大字栗田字舎利田711番地 新光電気工業株式会社内 (72)発明者 佐藤 健 長野県長野市大字栗田字舎利田711番地 新光電気工業株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mike McShane 78721, Texas, USA Austin, Ed Brustein Boulevard 3501 Motorola Incorporated, within the Semiconductor Products Sector (72) Inventor Sugio Uchida Nagano 711 Shinoda Electric Industrial Co., Ltd., Kurita character building, Nagano city, Nagano prefecture (72) Inventor Ken Sato 711 Shinoda electric industry corporation, Kurita character building, Nagano city, Nagano prefecture
Claims (6)
ンディングによって電気的に接続され、前記回路パター
ンの半導体チップが搭載された一方の面側に、前記半導
体チップ、ボンディングワイヤおよび回路パターンが封
止樹脂により一体に樹脂封止された半導体装置におい
て、 前記回路パターンは電解銅箔がエッチングされて形成さ
れ、該電解銅箔の粗面側となる一方の面が前記封止樹脂
に接合されていることを特徴とする半導体装置。1. A semiconductor chip and a circuit pattern are electrically connected by wire bonding, and the semiconductor chip, the bonding wires and the circuit pattern are formed on a sealing resin on one side of the circuit pattern on which the semiconductor chip is mounted. In the semiconductor device integrally resin-sealed, the circuit pattern is formed by etching an electrolytic copper foil, and one surface on the rough surface side of the electrolytic copper foil is joined to the sealing resin. A semiconductor device characterized by the above-mentioned.
側となる他方の面が、前記封止樹脂の表面に露出してい
ることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the other surface on the mirror surface side of the circuit pattern made of electrolytic copper foil is exposed on the surface of the sealing resin.
側となる他方の面が、外部接続用の端子部等の所要個所
を除いて、電気的絶縁性を有する保護コーティングによ
って被覆されていることを特徴とする請求項１記載の半
導体装置。3. The other side of the circuit pattern made of electrolytic copper foil, which is a mirror surface side, is covered with a protective coating having electrical insulation properties except for required portions such as external connection terminals. The semiconductor device according to claim 1, wherein:
剥離可能に金属層が設けられた転写フィルムの金属層を
エッチングして回路パターンを形成する工程と、 該転写フィルム10の回路パターンが形成された一方の面
側に半導体チップを接合する工程と、 該半導体チップと前記回路パターンとをワイヤボンディ
ングによって電気的に接続する工程と、 前記転写フィルムの半導体チップが搭載された一方の面
側に、前記半導体チップ、ボンディングワイヤおよび回
路パターンを一体に樹脂封止する工程と、 前記ベースフィルムを封止樹脂から剥離除去する工程と を含むことを特徴とする半導体装置の製造方法。4. A step of forming a circuit pattern by etching a metal layer of a transfer film having a releasable metal layer on a base film having electrical insulation, and forming a circuit pattern of the transfer film 10. Bonding the semiconductor chip to the one surface side, electrically connecting the semiconductor chip and the circuit pattern by wire bonding, and bonding the semiconductor chip to the one surface side of the transfer film on which the semiconductor chip is mounted. And a step of integrally sealing the semiconductor chip, the bonding wires and the circuit pattern with a resin, and a step of peeling and removing the base film from a sealing resin.
続用の端子部等の所要個所を除いて、電気的絶縁性を有
する保護コーティングを施す工程を含むことを特徴とす
る請求項４記載の半導体装置の製造方法。5. The method according to claim 4, further comprising the step of applying a protective coating having an electrical insulation property to the other surface side of the circuit pattern except for a required portion such as a terminal portion for external connection. The manufacturing method of the semiconductor device described in the above.
て、電気的絶縁性を有するベースフィルムに電解銅箔を
鏡面側をベースフィルムに向け、粗面側を外方に向けて
接合した転写フィルムを用いることを特徴とする請求項
４または５記載の半導体装置の製造方法。6. A transfer film provided with the metal layer, wherein an electrolytic copper foil is bonded to an electrically insulating base film with the mirror side facing the base film and the rough side facing outward. 6. The method for manufacturing a semiconductor device according to claim 4, wherein said method is used.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23132389A JP2781020B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor device and manufacturing method thereof |
| US07/756,952 US5200362A (en) | 1989-09-06 | 1991-09-09 | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
| US07/876,315 US5273938A (en) | 1989-09-06 | 1992-04-30 | Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film |
| US07/907,970 US5239198A (en) | 1989-09-06 | 1992-07-02 | Overmolded semiconductor device having solder ball and edge lead connective structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23132389A JP2781020B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0399456A JPH0399456A (en) | 1991-04-24 |
| JP2781020B2 true JP2781020B2 (en) | 1998-07-30 |
Family
ID=16921835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23132389A Expired - Lifetime JP2781020B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2781020B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006093575A (en) * | 2004-09-27 | 2006-04-06 | Hitachi Cable Ltd | Semiconductor device and its manufacturing method |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2962586B2 (en) * | 1991-03-05 | 1999-10-12 | 新光電気工業株式会社 | Semiconductor device, method of manufacturing the same, and joined body used therefor |
| JPH0685114A (en) * | 1992-09-01 | 1994-03-25 | Toshiba Corp | Resin seal semiconductor device and manufacture thereof |
| JP3247384B2 (en) * | 1994-03-18 | 2002-01-15 | 日立化成工業株式会社 | Semiconductor package manufacturing method and semiconductor package |
| JP3093960B2 (en) * | 1995-07-06 | 2000-10-03 | 株式会社三井ハイテック | Method for manufacturing semiconductor circuit element mounting substrate frame |
| JP3304705B2 (en) * | 1995-09-19 | 2002-07-22 | セイコーエプソン株式会社 | Manufacturing method of chip carrier |
| JP3129169B2 (en) * | 1995-11-08 | 2001-01-29 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| US6329711B1 (en) | 1995-11-08 | 2001-12-11 | Fujitsu Limited | Semiconductor device and mounting structure |
| JPH11121646A (en) * | 1997-10-14 | 1999-04-30 | Hitachi Cable Ltd | Semiconductor package and manufacture thereof |
| JP3521758B2 (en) * | 1997-10-28 | 2004-04-19 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| JPH11251484A (en) * | 1998-03-06 | 1999-09-17 | Mitsui High Tec Inc | Chip-sized semiconductor device |
| KR20000002999A (en) * | 1998-06-25 | 2000-01-15 | 윤종용 | Semiconductor chip package and production method thereof |
| JP3510839B2 (en) * | 2000-03-28 | 2004-03-29 | 三洋電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP2002076040A (en) * | 2000-08-30 | 2002-03-15 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
| JP5046481B2 (en) * | 2004-09-27 | 2012-10-10 | 日立電線株式会社 | Semiconductor device and manufacturing method thereof |
| JP5001542B2 (en) | 2005-03-17 | 2012-08-15 | 日立電線株式会社 | Electronic device substrate, method for manufacturing the same, and method for manufacturing the electronic device |
| JP4503039B2 (en) * | 2006-04-27 | 2010-07-14 | 三洋電機株式会社 | Circuit equipment |
| JP5113346B2 (en) | 2006-05-22 | 2013-01-09 | 日立電線株式会社 | Electronic device substrate and manufacturing method thereof, and electronic device and manufacturing method thereof |
| KR100764684B1 (en) * | 2006-11-01 | 2007-10-08 | 인티그런트 테크놀로지즈(주) | The method of semiconductor package, semiconductor device and the method of manufacturing therof |
| JP6050975B2 (en) * | 2012-03-27 | 2016-12-21 | 新光電気工業株式会社 | Lead frame, semiconductor device, and lead frame manufacturing method |
| JP6868455B2 (en) * | 2016-06-02 | 2021-05-12 | パナソニック株式会社 | Electronic component package and its manufacturing method |
| US10698005B2 (en) * | 2017-04-20 | 2020-06-30 | Asahi Kasei Microdevices Corporation | Magnetic detection device, current detection device, method for manufacturing magnetic detection device, and method for manufacturing current detection device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59208756A (en) * | 1983-05-12 | 1984-11-27 | Sony Corp | Manufacture of semiconductor device package |
-
1989
- 1989-09-06 JP JP23132389A patent/JP2781020B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59208756A (en) * | 1983-05-12 | 1984-11-27 | Sony Corp | Manufacture of semiconductor device package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006093575A (en) * | 2004-09-27 | 2006-04-06 | Hitachi Cable Ltd | Semiconductor device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0399456A (en) | 1991-04-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2781020B2 (en) | Semiconductor device and manufacturing method thereof | |
| US5519936A (en) | Method of making an electronic package with a thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
| US5773884A (en) | Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
| US6291271B1 (en) | Method of making semiconductor chip package | |
| US5633533A (en) | Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
| JPH04277636A (en) | Preparation of semiconductor device | |
| JP2781018B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2840317B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3059097B2 (en) | Electronic circuit board and its manufacturing method | |
| US6271057B1 (en) | Method of making semiconductor chip package | |
| JP2781019B2 (en) | Semiconductor device and manufacturing method thereof | |
| US5844305A (en) | Lead frame for semiconductor devices | |
| JP2915282B2 (en) | Plastic molded integrated circuit package | |
| JPH11274223A (en) | Wire bonding method to double metal covered pad surface and electric card structure containing its wire bonding | |
| JP2638758B2 (en) | Stacked semiconductor package and stacked package socket | |
| JP2813588B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2651608B2 (en) | Substrate for mounting electronic components | |
| JPH06112363A (en) | Semiconductor package | |
| JP2622862B2 (en) | Substrate for mounting electronic components with leads | |
| JP2813587B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2652223B2 (en) | Substrate for mounting electronic components | |
| JPH1074859A (en) | Qfn semiconductor package | |
| JP2784248B2 (en) | Method for manufacturing semiconductor device | |
| JP4643055B2 (en) | TAB tape carrier manufacturing method | |
| JPH04111456A (en) | Electronic component mounting board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090515 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100515 Year of fee payment: 12 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100515 Year of fee payment: 12 |