JP3869693B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP3869693B2
JP3869693B2 JP2001268413A JP2001268413A JP3869693B2 JP 3869693 B2 JP3869693 B2 JP 3869693B2 JP 2001268413 A JP2001268413 A JP 2001268413A JP 2001268413 A JP2001268413 A JP 2001268413A JP 3869693 B2 JP3869693 B2 JP 3869693B2
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conductor
insulating substrate
conductor terminal
semiconductor device
semiconductor chip
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JP2003078076A (en
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聡 珍田
勝美 鈴木
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の製造方法に関し、特に、ＱＦＮ（Quad Flat Non-leaded package）型あるいはＳＯＮ（Small Outline Non-leaded package）型のように導体端子（リード）が装置の外形から突出していない半導体装置に適用して有効な技術に関するものである。
【０００２】
【従来の技術】
従来、半導体チップの外部電極（ボンディングパッド）と導体端子（リード）をボンディングワイヤで電気的に接続し、前記半導体チップ、前記ボンディングワイヤ、及び前記ボンディングワイヤと前記リードの接続部を絶縁体で封止した半導体装置には、ＱＦＮ型やＳＯＮ型のように、前記リードが前記絶縁体から突出せず、前記絶縁体の表面に露出した状態の半導体装置がある。
【０００３】
前記ＱＦＮ型の半導体装置は、例えば、図１１（ａ）に示すように、半導体チップ１の外周部に沿って、実装基板あるいは外部装置と接続される導体端子（リード）２が配置されており、図１１（ｂ）に示すように、前記半導体チップ１と前記導体端子２は、例えば、フィルム状接着剤５’により接着されている。また、前記半導体チップ１の外部電極（ボンディングパッド）１０１と前記導体端子２は、図１１（ｂ）に示したように、ボンディングワイヤ３により電気的に接続されており、前記半導体チップ１、前記ボンディングワイヤ３、及び前記ボンディングワイヤ３と前記導体端子２との接続部が、例えば、エポキシ系樹脂などの熱硬化性樹脂のような絶縁体４で封止されている。またこのとき、前記導体端子２は、前記半導体チップ１の外側の領域で、例えば、図１１（ｂ）に示したように、前記半導体チップ１から遠ざかる方向に変形しており、前記導体端子２の一端が前記絶縁体４の表面に露出している。
【０００４】
前記ＱＦＮ型の半導体装置の製造方法を簡単に説明すると、まず、図１２に示すように、銅板などの金属板の所定位置にリードパターンを形成したリードフレーム１０を準備する。このとき、前記リードパターンには、半導体装置（パッケージ）として切り出す領域Ｌ１の外側から半導体チップを搭載する領域Ｌ２に向かって延びる導体端子２が設けられている。また、前記リードパターンは、例えば、金型による打ち抜き加工や、エッチング処理により形成される。また、前記リードパターンを形成した後、前記導体端子２の先端部を、図１１（ｂ）に示したように変形させる。またこのとき、前記リードフレーム１０は帯状あるいは短冊状になっており、一枚のリードフレーム１０に、図１２に示したリードパターンが数個から十数個、繰り返し形成される。
【０００５】
次に、図１３（ａ）に示すように、フィルム状接着剤５’を用いて、前記リードフレーム１０の導体端子２上に半導体チップ１を接着し、図１３（ｂ）に示すように、前記半導体チップ１の外部電極（ボンディングパッド）１０１と前記リードフレーム１０の導体端子２とをボンディングワイヤ３で電気的に接続する。
【０００６】
次に、図１４（ａ）に示すように、前記半導体チップ１が実装されたリードフレーム１０を、所定の形状の空間（キャビティ）８０１Ａが設けられた上金型８Ａと平板状の下金型８Ｂの間に設置し、封止用の絶縁体４として、例えば、未硬化の熱硬化性樹脂を前記上金型８Ａのキャビティ８０１Ａと前記下金型８Ｂで囲まれた空間内に流し込み、成形した後、所定の温度で所定時間加熱して前記絶縁体４（熱硬化性樹脂）を硬化させ、前記半導体チップ１、前記ボンディングワイヤ３、及び前記ボンディングワイヤ３と前記導体端子２の接続部を封止する。このとき、前記導体端子２の一面が、図１４（ａ）に示すように、前記下金型８Ｂと接触しているため、前記絶縁体４を硬化させて封止した後、前記導体端子２は、図１４（ｂ）に示したように、その表面の一部が前記絶縁体４の表面に露出する。
【０００７】
その後、図１２に示した、前記リードフレーム１０の領域Ｌ１を切り出す、すなわち、前記導体端子２の、前記絶縁体４から突出した部分を切断して個片化すると、図１１（ａ）及び図１１（ｂ）に示したようなＱＦＮ型の半導体装置になる。
【０００８】
【発明が解決しようとする課題】
しかしながら、前記従来の技術では、図１４（ａ）に示したような上金型８Ａ及び下金型８Ｂを用いたトランスファーモールドにより、前記半導体チップ１、前記ボンディングワイヤ３、及び前記ボンディングワイヤ３と前記導体端子２の接続部を封止しているが、前記リードフレーム１０の導体配線２は、先端部の成形時や搬送時、あるいはワイヤボンディング時にかかる外力、または前記上金型８Ａと下金型８Ｂで固定するときの加圧などにより変形しやすく、図１５（ａ）及び図１５（ｂ）に示すように、前記下金型８Ｂと前記変形した導体端子２’の間に隙間ができてしまうことがある。ここで、図１５（ｂ）は図１５（ａ）のＤ−Ｄ’線での断面図である。
【０００９】
図１５（ａ）及び図１５（ｂ）に示したように、前記変形した導体端子２’と前記下金型８Ｂの間に隙間ができると、前記絶縁体４（熱硬化性樹脂）を流し込んだときに、前記絶縁体４が前記隙間にも流れ込むため、前記絶縁体４を硬化させて封止した後、図１５（ｃ）に示すように、前記変形した導体端子２’は、前記絶縁体４で覆われてしまう、すなわち露出不良になるという問題があった。
【００１０】
前記導体端子２の露出不良により、例えば、前記導体端子２の露出面が狭くなると、前記半導体装置を実装する際の実装性が低下し、実装基板との接続信頼性が低下するという問題がある。また、前記導体端子２の前記絶縁体４で覆われた面積が大きい場合には、その半導体装置は不良品となり、半導体装置の製造歩留まりが低下するため、半導体装置の製造コストが増大するという問題があった。
【００１１】
また、図１２に示したような、前記リードフレーム１０を用いてＱＦＮ型の半導体装置を製造する場合には、封止工程の後の個片化工程で、前記導体端子２の突出部分２Ａを切断するが、図１６（ａ）に示すように、前記導体端子２の外形が矩形の場合、切断時に前記導体端子２にかかる応力（負荷）により前記導体端子２が前記絶縁体４から剥離しやすいという問題がある。そのため、例えば、図１６（ｂ）に示すように、外形が６角形状の導体端子１１にして、前記絶縁体４への引っ掛かりをよくする方法がある。この場合、金型による打ち抜き加工で前記リードフレームを形成することが難しく、エッチングにより前記リードフレームを形成しているが、エッチングの場合は処理時間が長くなり、生産性が低下するという問題があった。
【００１２】
また、図１６（ｂ）に示したような、６角形状の導体端子１１の場合も、搬送中や半導体チップを実装する工程で変形が起こりやすく、前記封止工程において、変形した導体端子が前記絶縁体４で覆われて不良品になりやすく、製造歩留まりが低下し、製造コストが増大すると言う問題があった。
【００１３】
また、前記リードフレームを用いて製造する場合には、前記リードフレームが短冊状であり、一枚のリードフレームで数個から十数個の半導体装置しか製造できないため、生産性が低く、製造コストが上昇するという問題があった。
【００１４】
また、図１１（ａ）及び図１１（ｂ）に示したようなＱＦＮ型の半導体装置の場合、前記絶縁体４で前記ボンディングワイヤ３を封止するとともに、前記導体端子２を前記絶縁体４の表面に露出させるために、前記導体端子２を変形させている。そのため、前記導体端子２の高さ分だけ前記半導体装置が厚くなり、半導体装置の薄型化が難しいという問題があった。
【００１５】
また、従来のＱＦＮ型の半導体装置の場合、前記半導体チップ１を前記導体端子２上に接着しているが、前記各導体端子２は、短絡しないようにある程度の距離を確保しなければならない。そのため、微細化や高密度化が難しいという問題がある。また、多ピン化すると半導体装置が大型化してしまうという問題があった。
【００１６】
本発明の目的は、ＱＦＮ型あるいはＳＯＮ型の半導体装置において、リード（導体端子）の露出不良を低減することが可能な技術を提供することにある。
【００１７】
本発明の他の目的は、ＱＦＮ型あるいはＳＯＮ型の半導体装置において、装置の製造歩留まりを向上させ、製造コストを低減することが可能な技術を提供することにある。
【００１８】
本発明の他の目的は、ＱＦＮ型あるいはＳＯＮ型の半導体装置において、装置の生産性を向上させ、製造コストを低減することが可能な技術を提供することにある。
【００１９】
本発明の他の目的は、ＱＦＮ型あるいはＳＯＮ型の半導体装置において、装置を薄型化することが可能な技術を提供することにある。
【００２０】
本発明の他の目的は、ＱＦＮ型あるいはＳＯＮ型の半導体装置において、多ピン化による装置の大型化を防ぐことが可能な技術を提供することにある。
【００２１】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面によって明らかになるであろう。
【００２２】
【課題を解決するための手段】
本発明において開示される発明の概要を説明すれば、以下のとおりである。
【００２３】
すなわち、ポリイミド樹脂基板を絶縁基板として用い、前記絶縁基板の表面に所定のパターンの導体端子を形成する導体端子形成工程と、前記導体端子が形成された絶縁基板上に半導体チップを接着し、前記半導体チップの外部電極（ボンディングパッド）と前記導体端子を電気的に接続する半導体チップ実装工程と、前記半導体チップ、前記導体端子、及び前記半導体チップの外部電極と前記導体端子との接続部分を絶縁体で封止する封止工程と、前記封止工程の後、前記絶縁体で封止された前記半導体チップ及び前記導体端子を前記絶縁基板から剥離する剥離工程とを備える半導体装置の製造方法であって、前記導体端子形成工程は、前記絶縁基板の表面に、所定の温度に加熱したときに前記絶縁基板との密着力が低下するニッケル合金からなる導体を用いて前記導体端子を形成し、前記剥離工程は、前記所定の温度に加熱して前記絶縁基板と前記導体端子との密着力を低下させてから剥離する半導体装置の製造方法である。
【００２４】
上記の手段によれば、前記絶縁基板の表面に、所定の条件にしたときに前記絶縁基板との密着性（接着性）が低下する導体を用いて前記導体端子を形成しておくことにより、封止工程の際には、前記絶縁基板と前記導体端子の密着力を高くしておき、前記導体端子と前記絶縁基板の接着界面に前記絶縁体が流れ込むのを防ぎ、前記封止工程の後、前記所定の条件で前記絶縁基板と前記導体端子の密着力を低下させて剥離することで、前記導体端子の一面、すなわち前記絶縁基板との接着界面の露出不良を低減することができる。
【００２５】
また、前記所定の条件で前記絶縁基板との密着力が低下する導体を用いて前記導体端子を形成することにより、前記剥離工程で前記導体端子を前記絶縁基板から剥離する際にかかる負荷を低減させることができ、前記導体端子が前記半導体チップを封止する絶縁体から剥離しにくくすることができる。
【００２６】
またこのとき、前記導体端子は、例えば、前記絶縁基板の表面に、所定の条件にしたときに前記絶縁基板との密着力が低下する第１導体膜を形成し、前記第1導体膜上に第2導体膜を形成し、前記第1導体膜及び前記第2導体膜をエッチング処理して形成する。またこのとき、前記第１導体膜及び前記第２導体膜をエッチング処理する工程では、前記第２導体上の前記導体端子を形成する部分にレジスト（エッチングレジスト）を形成するが、前記エッチングレジストには樹脂系材料のもののほかに、例えば、金めっきなどが用いられる。前記エッチングレジストに金めっきを用いた場合、エッチング処理後に前記金めっきを残しておき、ボンディングワイヤとの接続性をよくするための端子めっきとして用いることができる。
【００２７】
また、前記導体端子は、前記第１導体膜及び前記第２導体膜をエッチング処理する方法の他に、例えば、前記絶縁基板の表面に、所定の条件にしたときに前記絶縁基板との密着力が低下する第１導体膜を形成し、前記絶縁基板の表面に形成された前記第１導体膜上に、所定のパターンの第２導体膜を形成した後、前記第１導体膜の不要な部分を除去して前記導体端子を形成する、アディティブ法を用いた形成方法もある。
【００２８】
また、前記絶縁基板上に形成する前記第１導体膜には、所定の温度で所定時間加熱したときに前記絶縁基板との密着力が低下する導体を用いることが好ましく、具体的には、前記絶縁基板としてポリイミド樹脂基板を用い、前記ポリイミド樹脂基板の表面に、ニッケル合金を用いた第１導体膜を形成することが好ましい。
【００２９】
前記ポリイミド樹脂基板の表面に前記ニッケル合金膜を形成した場合、例えば、１８０℃の雰囲気中に１時間ほど放置しておくと、前記ポリイミド樹脂基板と前記ニッケル合金薄膜の接着強度が０．１Ｎ／ｍ程度になる。一方、前記ポリイミド樹脂基板と前記封止用絶縁体との接着強度は１Ｎ／ｍ程度、前記第２導体膜（電解銅めっき膜）と前記封止用絶縁体との接着強度は１Ｎ／ｍ程度であるため、前記剥離工程において、前記絶縁基板を前記導体端子から剥離する際に、前記導体端子にかかる負荷が小さく、前記導体配線が前記封止用絶縁体から剥離しにくいため、装置の信頼性及び製造歩留まりを向上させることができる。
【００３０】
また、前記絶縁基板としてポリイミド樹脂基板を用い、前記第１導体膜としてニッケル合金膜を用いた場合、加熱したときの前記ポリイミド樹脂基板との密着力を低下させやすくするために、前記ニッケル合金膜を薄く形成することが好ましいが、前記ニッケル合金膜を薄くすることにより前記導体端子の強度が低下するため、前記第２導体膜として、例えば、電解銅めっき膜を厚付けすることにより、前記導体端子の強度を保つことができる。
【００３１】
また、前記封止工程は、一般的に、前記封止用絶縁体として、エポキシ系などの熱硬化性樹脂が用いられており、金型を用いて溶融した前記熱硬化性樹脂を流し込み、成形した後、前記熱硬化性樹脂を所定の温度で所定時間加熱して硬化させている。このとき、前記熱硬化性樹脂の硬化は、例えば、約１８０℃の温度雰囲気中で５時間から６時間加熱して行うため、前記絶縁基板としてポリイミド樹脂基板を用い、前記第１導体膜としてニッケル合金膜を用いることにより、前記熱硬化性樹脂を硬化させる過程で前記絶縁基板と前記第１導体膜の密着性を低下させることができる。そのため、前記剥離工程において、前記絶縁基板と前記第１導体膜の密着力を低下させるための工程が不要であり、前記半導体装置の製造コストが上昇することを防げる。
【００３２】
また、前記絶縁基板としてポリイミド樹脂基板を用いた場合は、従来、ＴＡＢテープなどの配線板（テープキャリア）の製造に用いられているリールツーリール方式で、一度に大量の半導体装置を製造することができるため、従来のリードフレームを用いた製造方法に比べ、生産性が向上し、前記半導体装置の製造コストを低減させることができる。
【００３３】
また、前記絶縁基板は、前記剥離工程で前記半導体装置を剥離した後、再利用が可能であるため、前記絶縁基板を用いることにより製造コストはほとんど上昇しない。さらに、前記テープキャリアの製造方法と同様の製造方法を用いることにより、前記リードフレームを用いた製造方法に比べ、前記導体端子を形成する導体材料の無駄が少なくなり、装置の製造コストを低減させることができる。
【００３４】
また、前記絶縁基板上に平坦な導体端子を形成し、前記半導体チップを前記絶縁基板上にフェースアップ実装して、前記半導体チップの外部電極と前記導体端子をボンディングワイヤで接続することにより、従来のリードフレームを用いた場合に比べ、前記半導体装置を薄型化できる。
【００３５】
また、前記導体端子が形成された絶縁基板上に前記半導体チップを接着することにより、前記導体端子の配置に関する自由度が高くなるため、多ピン化が容易になる。
【００３６】
以下、本発明について、図面を参照して実施の形態（実施例）とともに詳細に説明する。
【００３７】
なお、実施例を説明するための全図において、同一機能を有するものは、同一符号をつけ、その繰り返しの説明は省略する。
【００３８】
【発明の実施の形態】
（実施例）
図１は、本発明による一実施例の半導体装置の概略構成を示す模式図であり、図１（ａ）は半導体装置を導体端子（外部接続端子）側から見た平面図、図１（ｂ）は図１（ａ）のＡ−Ａ’線での断面図である。
【００３９】
図１において、１は半導体チップ、１０１は半導体チップの外部電極（ボンディングパッド）、２は導体端子、２０１は第１導体膜（ニッケル合金膜）、２０２は第２導体膜（電解銅めっき膜）、２０３は端子めっき（金めっき）、３はボンディングワイヤ、４は絶縁体、５は接着剤（ダイペースト）である。
【００４０】
本実施例の半導体装置は、ＱＦＮ型の半導体装置であり、図１（ａ）及び図１（ｂ）に示すように、半導体チップ１と、前記半導体チップ１の外周に沿って設けられ、前記半導体チップの外部端子１０１と電気的に接続される導体端子２と、前記半導体チップの外部端子１０１と前記導体端子２を電気的に接続するボンディングワイヤ３と、前記半導体チップ１、前記ボンディングワイヤ３、及び前記ボンディングワイヤ３と前記導体端子２の接続部を封止する絶縁体４により構成されている。また、前記半導体チップ１の前記外部電極１０１が設けられた面と対向する面（非回路形成面）には、半導体装置を製造する際に用いた接着剤５が残っており、前記半導体チップ１は前記絶縁体４及び前記接着剤５により封止されている。
【００４１】
また、前記導体端子２は、図１（ｂ）に示すように、第１導体膜２０１、第２導体膜２０２、及び端子めっき２０３が積層されており、前記導体端子２の一面、言い換えると前記第１導体膜２０１が前記絶縁体４の表面に露出している。また、本実施例の半導体装置では、前記第１導体膜２０１としてニッケル合金膜を用い、前記第２導体膜２０２として電解銅めっき膜を用い、前記端子めっき２０３として金めっきを用いている。
【００４２】
図２乃至図８は、本実施例の半導体装置の製造方法を説明するための模式図であり、図２（ａ）、図２（ｂ）、図３はそれぞれ導体端子形成工程における各工程での断面図、図４は半導体チップ実装工程の平面図、図５及び図６は半導体チップ実装工程の断面図、図７は封止工程の断面図、図８は剥離工程の断面図である。
【００４３】
本実施例の半導体装置の製造方法は、大まかに分けると、所定の基板上に前記導体端子２を形成する導体端子形成工程、前記導体端子２が形成された前記基板上に半導体チップ１を実装する半導体チップ実装工程、前記基板上に実装された前記半導体チップ１を封止する封止工程、前記封止工程のあと、封止された半導体チップ１及び導体端子２を前記基板から剥離する剥離工程の４つの工程からなる。以下、図２乃至図８に沿って、本実施例の半導体装置の製造方法について説明する。
【００４４】
まず、前記導体端子形成工程では、図２（ａ）に示すように、例えば、ポリイミド樹脂からなる絶縁基板６の表面に、第１導体膜２０１及び第２導体膜２０２を積層する。このとき、前記第１導体膜２０１は、後の剥離工程において、前記絶縁基板６から剥離するため、前記絶縁基板６との密着力が弱い導体を用いるのが好ましいが、途中の工程あるいは搬送時などの外力での剥離を防ぐために、前記半導体チップ実装工程や前記封止工程では、ある程度の密着力が必要である。そのため、前記第１導体膜２０１には、例えば、所定の温度に加熱したときに前記絶縁基板６との密着力が低下するニッケル合金を用い、例えば、スパッタリングにより、厚さが５ｎｍ（５０オングストローム）以下になるように形成する。またこのとき、前記ニッケル合金膜は、例えば、クロム（Cr）の重量パーセントが５パーセントから１０パーセントのニッケル・クロム合金が好ましく、前記ニッケル・クロム合金の場合、１８０℃の雰囲気中に１時間程度放置すると、前記絶縁基板（ポリイミド樹脂基板）６との密着力（接着力）は０．１Ｎ／ｍ程度に低下する。またこのとき、前記酸素透過率が高い絶縁基板６ほど、加熱したときに前記第１導体膜２０１との密着力が低下しやすくなる。
【００４５】
また、前記第２導体膜２０２は、例えば、電解銅めっき膜であり、前記第１導体膜（ニッケル合金膜）２０１を陰極とした電解めっきで形成する。
【００４６】
またこのとき、前記絶縁基板６は、従来のテープキャリアの製造に用いられているテープ材料のように、一方向に長尺なテープ状をしており、前記第１導体膜２０１及び前記第２導体膜２０２はリール方式で形成する。
【００４７】
次に、例えば、図２（ｂ）に示すように、前記第２導体膜（電解銅めっき膜）２０２上に、図１（ａ）に示したような導体端子２を形成する部分が開口したレジスト（めっきレジスト）７を形成し、前記めっきレジスト７の開口部、すなわち、前記第２導体膜２０２の露出面に端子めっき２０３を形成する。前記めっきレジスト７は、例えば、フィルム状レジストを接着して所定のパターンを露光、現像する写真法や、スクリーン版を用いてレジストインクを印刷する印刷法により形成する。また、前記端子めっき２０３は、例えば、無電解ニッケルめっきを下地として無電解金めっきを形成する。
【００４８】
またこのとき、前記めっきレジスト７及び前記端子めっき２０３は、リール法により形成するため、１個の半導体装置を形成する領域Ｌ１内に、図１（ａ）に示したようなパターンの端子めっき２０３が形成されており、前記領域Ｌ１内のパターンと同様のパターンが前記絶縁基板６上に連続的に形成される。
【００４９】
次に、前記めっきレジスト７を除去した後、前記端子めっき２０３をマスク（エッチングレジスト）として、図３に示すように、前記第２導体膜２０２及び前記第１導体膜２０１をエッチング処理して導体端子２を形成する。このとき、エッチング溶液としては、例えば、塩化第二鉄（FeCl3）溶液や塩化第二銅（CuCl2・２H2O）溶液が用いられる。
【００５０】
前記導体端子形成工程の次に行われる半導体チップ実装工程では、まず、図４及び図５に示すように、前記導体端子形成工程で前記導体端子２を形成した基板６のチップ搭載領域に、例えば、銀ペーストなどの接着剤５を塗布して半導体チップ１を接着する。
【００５１】
次に、図６に示すように、前記半導体チップ１の外部電極１０１と前記導体端子２をボンディングワイヤ３で電気的に接続する。このとき、前記ボンディングワイヤ３のループ高さを低くするために、例えば、前記導体端子２を第１ボンドとして超音波を併用した熱圧着で接続し、前記半導体チップの外部電極１０１を第２ボンドとして熱圧着する逆ボンディングにより接続する。
【００５２】
前記半導体チップ実装工程の次に行われる封止工程では、前記半導体チップ１、前記ボンディングワイヤ３、及び前記ボンディングワイヤ３と前記導体端子２の接続部を絶縁体４で封止する。このとき、前記半導体チップ１が実装された絶縁基板６は、図７に示すように、所定の形状の空間（キャビティ）８０１Ａが設けられた上金型８Ａと、前記基板１を支持する平板状の下金型８Ｂの間に設置、固定し、前記上金型８Ａのキャビティ８０１Ａ内に、前記絶縁体４として、例えば、溶融させた熱硬化性樹脂、あるいは未硬化の熱硬化性樹脂などを流し込んで充満させ、成形した後、前記絶縁体４を所定の条件、例えば、１８０℃の雰囲気中で５時間から６時間加熱して硬化させる。またこのとき、前記絶縁体４を加熱して硬化させている過程で、前記第１導体膜（ニッケル合金膜）２０１と前記絶縁基板（ポリイミド樹脂基板）６との密着力が低下する。
【００５３】
前記封止工程において、前記絶縁体４を流し込んで成形するときの温度は１８０℃程度で、所要時間は２分程度であるため、前記絶縁体４を流し込んでいる際には、前記第１導体膜（ニッケル合金膜）２０１と前記絶縁基板（ポリイミド樹脂基板）６との密着力は低下しない。そのため、前記絶縁体４を流し込んだときの外力で前記導体端子２が前記絶縁基板１から剥離する可能性はほとんどなく、前記第１導体膜２０１と前記絶縁基板６の接着界面に前記絶縁体４が流れ込むことはない。
【００５４】
前記封止工程の次に行われる剥離工程では、例えば、図８に示すように、ローラー９を用いて前記絶縁基板６に曲げ変形を加えて、半導体装置、すなわち前記絶縁体４で封止された前記半導体チップ１、前記ボンディングワイヤ３、及び前記導体端子２を前記絶縁基板６から剥離する。このとき、前記封止工程において、前記絶縁体４を加熱して硬化させる過程で前記導体端子２と前記絶縁基板６との密着力が低下していることを利用し、前記絶縁体４を硬化させる高温炉から取り出した直後に、図８で示したように前記絶縁基板６に曲げ変形を加えることにより、前記半導体装置を容易に剥離することができる。
【００５５】
前記ポリイミド樹脂基板６の表面に前記ニッケル合金膜２０１を形成した場合、例えば、１８０℃の雰囲気中に１時間ほど放置しておくと、前記ポリイミド樹脂基板６と前記ニッケル合金薄膜２０１の接着強度が０．１Ｎ／ｍ程度になる。一方、前記ポリイミド樹脂基板６と前記封止用絶縁体４との接着強度は１Ｎ／ｍ程度、前記第２導体膜（電解銅めっき膜）２０２と前記封止用絶縁体４との接着強度は１Ｎ／ｍ程度であるため、前記剥離工程において、前記絶縁基板６を前記導体端子２から剥離する際に、前記導体配線２が前記封止用絶縁体４から剥離されにくいため、装置の信頼性及び製造歩留まりを向上させることができる。
【００５６】
また、前記絶縁基板６を剥離する際に前記導体配線２にかかる負荷は、１０ｇｆ程度であり、従来のリードフレームを切断する際の負荷に比べて小さいため、個片化する際の負荷（衝撃）で前記導体端子２が前記絶縁体４から剥離し、抜け落ちることを防げる。
【００５７】
以上のような手順で、図１（ａ）及び図１（ｂ）に示したようなＱＦＮ型の半導体装置を製造した後、前記絶縁基板６は再利用され、図２に示したように、第１導体２０１及び前記第２導体２０２を形成し、前記各工程を繰り返す。
【００５８】
以上説明したように、本実施例の半導体装置の製造方法によれば、前記絶縁基板（ポリイミド樹脂基板）６の表面に、所定の条件で加熱したときに前記絶縁基板６との密着性（接着性）が低下する第１導体膜（ニッケル合金膜）２０１を下地とした前記導体端子２を形成しておくことにより、封止工程の際には、前記絶縁基板６と前記導体端子２の密着力を高くしておき、前記導体端子２と前記絶縁基板６の接着界面に前記絶縁体４が流れ込むのを防ぎ、前記封止工程のあと、前記所定の条件で加熱し、前記絶縁基板６と前記導体端子２の密着力を低下させて剥離することで、前記導体端子２の一面、すなわち、前記第１導体層２０１の露出不良を低減することができる。
【００５９】
また、前記所定の条件で加熱したときに前記絶縁基板（ポリイミド樹脂基板）６との密着力が低下する第１導体膜（ニッケル合金膜）２０１を下地とした前記導体端子２を形成することにより、前記剥離工程で前記導体端子２を前記絶縁基板６から剥離する際にかかる負荷を低減させることができ、前記導体端子２が前記半導体チップ１を封止する絶縁体４から剥離しにくくすることができる。
【００６０】
また、前記導体端子２の露出面積が所定の面積より狭くなる、あるいはふさがれることがないため、前記導体端子２の露出面の不良による半導体装置の不良が低減し、製造歩留まりが向上するため、半導体装置の製造コストを低減することができる。
【００６１】
また、封止後の半導体装置の前記導体端子２は、前記剥離工程において前記絶縁基板６を剥離するまで、前記絶縁基板６に保護されているため、前記導体端子２の露出面、すなわち前記第１導体膜２０１の表面に傷が付き、実装性が悪くなることを防げる。
【００６２】
また、テープ状の絶縁基板６を用いて、従来からテープキャリアの製造に用いられているリールツーリール方式で半導体装置を製造することができるため、一度に大量の半導体装置を製造でき、生産性が向上するため、装置の製造コストを低減することができる。
【００６３】
また、前記絶縁基板６は、剥離工程の後で再利用ができるため、前記絶縁基板６を用いることによる製造コストの上昇はほとんどない。また、前記絶縁基板６上に前記導体端子２を効率よく形成できるため、従来のリードフレームを用いた製造方法に比べ、前記導体端子２の材料費を低減し、半導体装置の製造コストを低減することができる。
【００６４】
また、本実施例の半導体装置のように、前記絶縁基板６上に前記半導体チップ１を接着し、前記導体端子２と前記半導体チップの外部電極１０１を逆ボンディングで接続することにより、従来の、図１１（ｂ）に示したような、リードフレームを用いた半導体装置に比べ、薄型化することができる。
【００６５】
また、本実施例の半導体装置では、図２（ａ）に示したように、前記絶縁基板６の表面に、前記第１導体膜（ニッケル合金膜）２０１及び前記第２導体膜（電解銅めっき膜）２０２を形成した後、前記端子めっき２０３を形成し、前記端子めっき２０３をエッチングレジストとして用いて前記第１導体膜２０１及び前記第２導体膜２０２をエッチング処理し、前記導体端子２を形成したが、これに限らず、例えば、前記端子めっき２０３を形成する代わりに、他のエッチングレジストを形成してエッチング処理してもよいことは言うまでもない。また、前記導体端子２を微細化した場合には、前記絶縁基板６の表面に前記第１導体膜２０１を形成し、アディティブ法により、前記導体端子２を形成する部分のみに前記第２導体（電解銅めっき）２０２を形成した後、クイックエッチングで前記第１導体２０１の不要な部分を除去してもよい。
【００６６】
図９は、前記実施例の半導体装置の変形例を示す模式図であり、図９（ａ）は半導体装置の導体端子２側から見た平面図、図９（ｂ）は図９（ａ）のＢ−Ｂ’線での断面図である。なお、図９（ｂ）の断面図は、図９（ａ）の半導体装置の断面を上下反転させて示している。
【００６７】
前記実施例の半導体装置では、図４及び図５に示したように、前記絶縁基板６の半導体チップ１が搭載される領域の外側に前記導体端子２を配置し、前記絶縁基板６上に前記接着剤（銀ペースト）５を用いて前記半導体チップ１を接着しているため、前記接着剤５が前記封止用の絶縁体４の表面に露出しているが、これに限らず、例えば、図９（ａ）及び図９（ｂ）に示すように、前記導体端子２の一端が前記半導体チップ１を搭載する領域内に突出するように設け、フィルム状接着剤５’を用いて前記導体端子２上に前記半導体チップ１を接着してもよい。この場合には、前記導体端子２の高さ分だけ、前記絶縁基板６と前記半導体チップ１の間に隙間ができ、図７で示した前記封止工程で、前記絶縁基板６と前記半導体チップ１の間に前記封止用の絶縁体４が入り込み、前記フィルム状接着剤５’は露出しない。
【００６８】
図１（ａ）及び図１（ｂ）に示したような、前記接着剤（銀ペースト）５が露出した半導体装置では、前記剥離工程で前記絶縁基板６を剥離する際、あるいはその後に前記接着剤５が剥離して前記半導体チップ１が露出し、前記半導体チップ１に傷が付く可能性があるが、図９（ａ）及び図９（ｂ）に示したように、前記接着剤５も前記封止用の絶縁体４の内部に封止することで、前記半導体チップ１が露出し、傷が付くことを防げ、半導体装置の信頼性をさらに向上させることができる。
【００６９】
図１０は、前記実施例の半導体装置の他の変形例を示す模式図であり、図１０（ａ）は半導体チップ側から見た平面図、図１０（ｂ）は図１０（ａ）の半導体装置を側面方向から見た断面図である。なお、図１０（ａ）では、前記半導体チップを封止する絶縁体は省略して示している。
【００７０】
前記実施例の半導体装置では、図１（ａ）及び図１（ｂ）に示したように、前記導体端子２が装置の端部に沿って一列に配置されているが、これに限らず、例えば、図１０（ａ）に示すように、前記半導体チップ１の外部電極１０１および前記導体端子２を千鳥配列にしてもよい。この場合は、前記導体端子２の数が増えて密に配置されるため、例えば、図１０（ｂ）に示すように、ループ高さの異なるワイヤボンディングをすることにより、前記ボンディングワイヤ３同士の接触によるショート不良を防ぐ。
【００７１】
図１（ａ）及び図１（ｂ）に示したように、前記導体端子２を一列配列にした場合、前記半導体チップ上の外部電極（ボンディングパッド）１０１の数が増えると前記半導体装置が大型化してしまうが、図１０（ａ）及び図１０（ｂ）に示すように、前記導体端子２を千鳥配列にすることにより、多ピン化、すなわち前記導体端子２の数を増やしたときに前記半導体装置が大型化する割合を低減させることができる。
【００７２】
また、図１０（ａ）及び図１０（ｂ）に示した半導体装置では、前記導体端子２を千鳥配列にしているが、これに限らず、従来のＬＧＡ（Land Grid Array）型の半導体装置のように、前記導体端子２を２列以上の格子状に配置してもよいことは言うまでもない。
【００７３】
以上、本発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることはもちろんである。
【００７４】
例えば、前記実施例では、前記外部端子が前記半導体装置の４辺に沿って配列されたＱＦＮ型の半導体装置を例にあげているが、これに限らず、例えば、半導体装置の対向する２辺に前記外部端子が配列されたＳＯＮ型の半導体装置でもよい。
【００７５】
また、前記実施例の半導体装置の製造方法では、前記封止工程において、前記絶縁体4を硬化させる際の加熱で前記第1導体膜（ニッケル合金膜）２０１と前記絶縁基板（ポリイミド樹脂基板）６の密着力を低下させ、その直後に前記絶縁基板６を剥離していたが、これに限らず、例えば、前記封止工程とは別の工程で加熱して、前記第1導体膜２０１と前記絶縁基板６の密着力を低下させてもよいことは言うまでもない。
【００７６】
【発明の効果】
本発明において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。
【００７７】
（１）本発明によれば、封止用絶縁体で封止された半導体チップ及び導体端子を絶縁基板から剥離する構成を採用したため、導体端子の実装面を封止用絶縁体の中にもぐり込ませることなく、確実に外部に露出させることができ、また、絶縁基板としてポリイミドを、導体端子としてニッケル合金を用いたことにより、封止工程の後に、絶縁基板と導体端子の密着力を低下させて剥離しやすくすることができる。
【００７８】
（２）ＱＦＮ型あるいはＳＯＮ型の半導体装置において、装置の製造歩留まりを向上させ、製造コストを低減することができる。
【００７９】
（３）ＱＦＮ型あるいはＳＯＮ型の半導体装置において、装置の生産性を向上させ、製造コストを低減することができる。
【００８０】
（４）ＱＦＮ型あるいはＳＯＮ型の半導体装置において、装置を薄型化することができる。
【００８１】
（５）ＱＦＮ型あるいはＳＯＮ型の半導体装置において、多ピン化による装置の大型化を防ぐことできる。
【図面の簡単な説明】
【図１】本発明による一実施例の半導体装置の概略構成を示す模式図であり、図１（ａ）は半導体装置を導体端子側から見た平面図、図１（ｂ）は図１（ａ）のＡ−Ａ’線での断面図である。
【図２】本実施例の半導体装置の製造方法を説明するための模式図であり、図２（ａ）及び図２（ｂ）はそれぞれ、導体端子形成工程における各工程での断面図である。
【図３】本実施例の半導体装置の製造方法を説明するための模式図であり、導体端子形成工程における断面図である。
【図４】本実施例の半導体装置の製造方法を説明するための模式図であり、半導体チップ実装工程における平面図である。
【図５】本実施例の半導体装置の製造方法を説明するための模式図であり、図４の側面方向から見た断面図である。
【図６】本実施例の半導体装置の製造方法を説明するための模式図であり、ワイヤボンディング工程の断面図である。
【図７】本実施例の半導体装置の製造方法を説明するための模式図であり、封止工程における断面図である。
【図８】本実施例の半導体装置の製造方法を説明するための模式図であり、剥離工程における断面図である。
【図９】前記実施例の半導体装置の変形例を示す模式図であり、図９（ａ）は半導体装置の導体端子側から見た平面図、図９（ｂ）は図９（ａ）のＢ−Ｂ’線での断面図である。
【図１０】前記実施例の半導体装置の他の変形例を示す模式図であり、図１０（ａ）は半導体装置のチップ側から見た平面図、図１０（ｂ）は図１０（ａ）の側面方向から見た断面図である。
【図１１】従来のＱＦＮ型の半導体装置の概略構成を示す模式図であり、図１１（ａ）は装置の導体端子（リード）側から見た平面図、図１１（ｂ）は図１１（ａ）のＣ−Ｃ’線での断面図である。
【図１２】従来のＱＦＮ型の半導体装置の製造方法を説明するための模式図であり、使用するリードフレームの概略構成を示す平面図である。
【図１３】従来のＱＦＮ型の半導体装置の製造方法を説明するための模式図であり、図１３（ａ）、図１３（ｂ）はそれぞれ、半導体チップを実装する工程の断面図である。
【図１４】従来のＱＦＮ型の半導体装置の製造方法を説明するための模式図であり、図１４（ａ）は封止工程の断面図、図１４（ｂ）は個片化工程の断面図である。
【図１５】従来のＱＦＮ型の半導体装置の問題点を説明するための模式図である。
【図１６】従来のＱＦＮ型の半導体装置の他の問題点を説明するための模式図である。
【符号の説明】
１ 半導体チップ
１０１ 外部電極（ボンディングパッド）
２ 導体端子（リード）
２０１ 第１導体膜（ニッケル合金膜）
２０２ 第２導体膜（電解銅めっき膜）
２０３ 端子めっき
３ ボンディングワイヤ
４ 絶縁体
５ 接着剤（ダイペースト）
５’ フィルム状接着剤
６ 絶縁基板（ポリイミド樹脂基板）
７ レジスト（めっきレジスト）
８Ａ 上金型
８０１Ａ キャビティ
８Ｂ 下金型
９ ローラー
１０ リードフレーム
１１ ６角形状の導体端子[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device.SetWith regard to the manufacturing method, it is particularly effective when applied to a semiconductor device in which the conductor terminal (lead) does not protrude from the outer shape of the device, such as the QFN (Quad Flat Non-leaded package) type or SON (Small Outline Non-leaded package) type. Technology.
[0002]
[Prior art]
Conventionally, an external electrode (bonding pad) of a semiconductor chip and a conductor terminal (lead) are electrically connected by a bonding wire, and the semiconductor chip, the bonding wire, and the bonding wire and the lead connection portion are sealed with an insulator. Among the stopped semiconductor devices, there are semiconductor devices in which the lead does not protrude from the insulator and is exposed on the surface of the insulator, such as QFN type and SON type.
[0003]
In the QFN type semiconductor device, for example, as shown in FIG. 11A, conductor terminals (leads) 2 connected to a mounting substrate or an external device are arranged along the outer peripheral portion of the semiconductor chip 1. As shown in FIG. 11B, the semiconductor chip 1 and the conductor terminal 2 are bonded by, for example, a film adhesive 5 ′. Further, as shown in FIG. 11B, the external electrode (bonding pad) 101 of the semiconductor chip 1 and the conductor terminal 2 are electrically connected by a bonding wire 3, and the semiconductor chip 1, The bonding wire 3 and the connection portion between the bonding wire 3 and the conductor terminal 2 are sealed with an insulator 4 such as a thermosetting resin such as an epoxy resin. At this time, the conductor terminal 2 is deformed in a direction away from the semiconductor chip 1 in the region outside the semiconductor chip 1, for example, as shown in FIG. Is exposed on the surface of the insulator 4.
[0004]
The manufacturing method of the QFN type semiconductor device will be briefly described. First, as shown in FIG. 12, a lead frame 10 having a lead pattern formed at a predetermined position of a metal plate such as a copper plate is prepared. At this time, the lead pattern is provided with conductor terminals 2 extending from the outside of the region L1 cut out as a semiconductor device (package) toward the region L2 on which the semiconductor chip is mounted. The lead pattern is formed by, for example, a punching process using a mold or an etching process. Further, after forming the lead pattern, the tip of the conductor terminal 2 is deformed as shown in FIG. At this time, the lead frame 10 has a strip shape or a strip shape, and several to dozens of lead patterns shown in FIG. 12 are repeatedly formed on one lead frame 10.
[0005]
Next, as shown in FIG. 13A, the semiconductor chip 1 is bonded onto the conductor terminal 2 of the lead frame 10 using a film adhesive 5 ′, and as shown in FIG. The external electrodes (bonding pads) 101 of the semiconductor chip 1 and the conductor terminals 2 of the lead frame 10 are electrically connected by bonding wires 3.
[0006]
Next, as shown in FIG. 14A, the lead frame 10 on which the semiconductor chip 1 is mounted is divided into an upper mold 8A provided with a predetermined shape space (cavity) 801A and a flat lower mold. 8B, as the sealing insulator 4, for example, uncured thermosetting resin is poured into the space surrounded by the cavity 801A of the upper mold 8A and the lower mold 8B, and molding is performed. After that, the insulator 4 (thermosetting resin) is cured by heating at a predetermined temperature for a predetermined time, and the semiconductor chip 1, the bonding wire 3, and the connection portion between the bonding wire 3 and the conductor terminal 2 are formed. Seal. At this time, since one surface of the conductor terminal 2 is in contact with the lower mold 8B as shown in FIG. 14A, after the insulator 4 is cured and sealed, the conductor terminal 2 As shown in FIG. 14B, a part of the surface is exposed on the surface of the insulator 4.
[0007]
After that, the region L1 of the lead frame 10 shown in FIG. 12 is cut out, that is, when the portion of the conductor terminal 2 protruding from the insulator 4 is cut into individual pieces, FIG. 11A and FIG. A QFN type semiconductor device as shown in FIG.
[0008]
[Problems to be solved by the invention]
However, in the conventional technique, the semiconductor chip 1, the bonding wire 3, and the bonding wire 3 are formed by transfer molding using the upper mold 8A and the lower mold 8B as shown in FIG. The connection portion of the conductor terminal 2 is sealed, but the conductor wiring 2 of the lead frame 10 has an external force applied at the time of molding or transporting the tip portion or wire bonding, or the upper mold 8A and the lower mold. It is easy to be deformed by pressurization when it is fixed with the mold 8B, and as shown in FIGS. 15A and 15B, a gap is formed between the lower mold 8B and the deformed conductor terminal 2 ′. May end up. Here, FIG. 15B is a cross-sectional view taken along line D-D ′ of FIG.
[0009]
As shown in FIGS. 15A and 15B, when a gap is formed between the deformed conductor terminal 2 ′ and the lower mold 8B, the insulator 4 (thermosetting resin) is poured. At this time, since the insulator 4 also flows into the gap, after the insulator 4 is cured and sealed, as shown in FIG. 15C, the deformed conductor terminal 2 ' There was a problem that it was covered with the body 4, that is, it was poorly exposed.
[0010]
If, for example, the exposed surface of the conductor terminal 2 becomes narrow due to poor exposure of the conductor terminal 2, there is a problem that mountability when the semiconductor device is mounted is lowered and connection reliability with the mounting substrate is lowered. . In addition, when the area covered with the insulator 4 of the conductor terminal 2 is large, the semiconductor device becomes a defective product, and the manufacturing yield of the semiconductor device is reduced, so that the manufacturing cost of the semiconductor device increases. was there.
[0011]
Further, when a QFN type semiconductor device is manufactured using the lead frame 10 as shown in FIG. 12, the protruding portion 2A of the conductor terminal 2 is formed in the singulation step after the sealing step. When the outer shape of the conductor terminal 2 is rectangular as shown in FIG. 16A, the conductor terminal 2 is peeled off from the insulator 4 due to stress (load) applied to the conductor terminal 2 at the time of cutting. There is a problem that it is easy. Therefore, for example, as shown in FIG. 16 (b), there is a method in which the hexagonal conductor terminal 11 is used to improve the catch on the insulator 4. In this case, it is difficult to form the lead frame by punching with a mold, and the lead frame is formed by etching. However, in the case of etching, there is a problem that the processing time becomes long and productivity is lowered. It was.
[0012]
Also, in the case of the hexagonal conductor terminal 11 as shown in FIG. 16B, deformation is likely to occur during the transportation or the process of mounting the semiconductor chip. There is a problem that the insulator 4 is likely to be a defective product because it is covered with the insulator 4, the manufacturing yield decreases, and the manufacturing cost increases.
[0013]
Further, when manufacturing using the lead frame, the lead frame has a strip shape, and only a few to a dozen semiconductor devices can be manufactured with one lead frame, so that the productivity is low and the manufacturing cost is low. There was a problem of rising.
[0014]
In the case of the QFN type semiconductor device as shown in FIGS. 11A and 11B, the bonding wire 3 is sealed with the insulator 4 and the conductor terminal 2 is connected to the insulator 4. The conductor terminal 2 is deformed so as to be exposed on the surface. For this reason, the semiconductor device becomes thicker by the height of the conductor terminal 2, which makes it difficult to reduce the thickness of the semiconductor device.
[0015]
In the case of a conventional QFN type semiconductor device, the semiconductor chip 1 is bonded onto the conductor terminal 2. However, it is necessary to secure a certain distance between the conductor terminals 2 so as not to be short-circuited. Therefore, there is a problem that miniaturization and high density are difficult. In addition, when the number of pins is increased, there is a problem that the semiconductor device is increased in size.
[0016]
An object of the present invention is to provide a technique capable of reducing lead (conductor terminal) exposure failure in a QFN type or SON type semiconductor device.
[0017]
Another object of the present invention is to provide a technique capable of improving the manufacturing yield of a device and reducing the manufacturing cost in a QFN type or SON type semiconductor device.
[0018]
Another object of the present invention is to provide a technique capable of improving the productivity of a QFN type or SON type semiconductor device and reducing the manufacturing cost.
[0019]
Another object of the present invention is to provide a technique capable of reducing the thickness of a QFN type or SON type semiconductor device.
[0020]
Another object of the present invention is to provide a technique capable of preventing an increase in size of the device due to the increase in the number of pins in a QFN type or SON type semiconductor device.
[0021]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0022]
[Means for Solving the Problems]
The outline of the invention disclosed in the present invention will be described as follows.
[0023]
  That is, using a polyimide resin substrate as an insulating substrate,Forming conductor terminals with a predetermined pattern on the surface of an insulating substrateA conductor terminal forming step,Adhering a semiconductor chip on an insulating substrate on which the conductor terminals are formed, and external electrodes of the semiconductor chip(Bonding pad)And electrically connecting the conductor terminalsA semiconductor chip mounting process,The connection portion between the semiconductor chip, the conductor terminal, and the external electrode of the semiconductor chip and the conductor terminalInsulatorSealed withSealing step to perform,After the sealing step,InsulatorThe semiconductor chip and the conductor terminal sealed with are peeled off from the insulating substrate.With a peeling processA method for manufacturing a semiconductor device, comprising:The conductor terminal forming step forms the conductor terminal on the surface of the insulating substrate using a conductor made of a nickel alloy whose adhesion to the insulating substrate is reduced when heated to a predetermined temperature, and the peeling step Peels after heating to the predetermined temperature to reduce the adhesion between the insulating substrate and the conductor terminalManufacturing method of semiconductor deviceIs.
[0024]
  the aboveAccording to the above means, the conductor terminal is formed on the surface of the insulating substrate by using a conductor whose adhesion (adhesion) with the insulating substrate is lowered when a predetermined condition is satisfied. In the stopping step, the adhesive force between the insulating substrate and the conductor terminal is increased to prevent the insulator from flowing into the adhesive interface between the conductor terminal and the insulating substrate, and after the sealing step, By peeling off the insulating substrate and the conductor terminal by reducing the adhesive force under the predetermined condition, it is possible to reduce the exposure failure of one surface of the conductor terminal, that is, the adhesive interface with the insulating substrate.
[0025]
In addition, by forming the conductor terminal using a conductor whose adhesion to the insulating substrate is reduced under the predetermined condition, a load applied when the conductor terminal is peeled from the insulating substrate in the peeling step is reduced. The conductor terminal can be made difficult to peel from the insulator that seals the semiconductor chip.
[0026]
At this time, the conductor terminal is formed on the surface of the insulating substrate, for example, by forming a first conductor film whose adhesion to the insulating substrate is reduced when a predetermined condition is satisfied, and on the first conductor film. A second conductor film is formed, and the first conductor film and the second conductor film are formed by etching. At this time, in the step of etching the first conductor film and the second conductor film, a resist (etching resist) is formed on a portion of the second conductor where the conductor terminal is formed. In addition to resin-based materials, for example, gold plating is used. When gold plating is used for the etching resist, the gold plating can be left after the etching process and used as terminal plating for improving the connectivity with the bonding wire.
[0027]
In addition to the method of etching the first conductor film and the second conductor film, the conductor terminal has, for example, an adhesion force to the insulating substrate when the insulating substrate is subjected to a predetermined condition on the surface. After the first conductor film is formed and the second conductor film having a predetermined pattern is formed on the first conductor film formed on the surface of the insulating substrate, unnecessary portions of the first conductor film are formed. There is also a forming method using an additive method in which the conductor terminal is formed by removing the conductor.
[0028]
The first conductor film formed on the insulating substrate is preferably a conductor whose adhesion with the insulating substrate is reduced when heated at a predetermined temperature for a predetermined time. Preferably, a polyimide resin substrate is used as the insulating substrate, and a first conductor film using a nickel alloy is formed on the surface of the polyimide resin substrate.
[0029]
When the nickel alloy film is formed on the surface of the polyimide resin substrate, for example, if it is left in an atmosphere at 180 ° C. for about 1 hour, the adhesion strength between the polyimide resin substrate and the nickel alloy thin film is 0.1 N / m. On the other hand, the adhesive strength between the polyimide resin substrate and the sealing insulator is about 1 N / m, and the adhesive strength between the second conductor film (electrolytic copper plating film) and the sealing insulator is about 1 N / m. Therefore, in the peeling step, when the insulating substrate is peeled from the conductor terminal, the load applied to the conductor terminal is small, and the conductor wiring is difficult to peel from the sealing insulator. And the manufacturing yield can be improved.
[0030]
In addition, when a polyimide resin substrate is used as the insulating substrate and a nickel alloy film is used as the first conductor film, the nickel alloy film is used to easily reduce the adhesive force with the polyimide resin substrate when heated. However, since the strength of the conductor terminal is reduced by reducing the thickness of the nickel alloy film, the conductor may be formed by thickening, for example, an electrolytic copper plating film as the second conductor film. The strength of the terminal can be maintained.
[0031]
The sealing step generally uses an epoxy-based thermosetting resin as the sealing insulator, and pours the molten thermosetting resin using a mold. After that, the thermosetting resin is cured by heating at a predetermined temperature for a predetermined time. At this time, since the thermosetting resin is cured by heating in a temperature atmosphere of about 180 ° C. for 5 to 6 hours, for example, a polyimide resin substrate is used as the insulating substrate, and nickel is used as the first conductor film. By using the alloy film, the adhesion between the insulating substrate and the first conductor film can be reduced in the process of curing the thermosetting resin. Therefore, in the peeling step, a step for reducing the adhesion between the insulating substrate and the first conductor film is unnecessary, and the manufacturing cost of the semiconductor device can be prevented from increasing.
[0032]
In addition, when a polyimide resin substrate is used as the insulating substrate, a large number of semiconductor devices are manufactured at once by a reel-to-reel method that is conventionally used for manufacturing a wiring board (tape carrier) such as a TAB tape. Therefore, productivity can be improved and the manufacturing cost of the semiconductor device can be reduced as compared with a manufacturing method using a conventional lead frame.
[0033]
In addition, since the insulating substrate can be reused after the semiconductor device is peeled in the peeling step, the manufacturing cost is hardly increased by using the insulating substrate. Furthermore, by using a manufacturing method similar to the manufacturing method of the tape carrier, the waste of the conductor material forming the conductor terminals is reduced compared to the manufacturing method using the lead frame, thereby reducing the manufacturing cost of the device. be able to.
[0034]
Further, by forming a flat conductor terminal on the insulating substrate, mounting the semiconductor chip face up on the insulating substrate, and connecting the external electrode of the semiconductor chip and the conductor terminal with a bonding wire, The semiconductor device can be made thinner as compared with the case of using the lead frame.
[0035]
Further, by adhering the semiconductor chip on the insulating substrate on which the conductor terminals are formed, the degree of freedom regarding the arrangement of the conductor terminals is increased, so that it is easy to increase the number of pins.
[0036]
Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.
[0037]
In all the drawings for explaining the embodiments, parts having the same function are given the same reference numerals, and repeated explanation thereof is omitted.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
(Example)
FIG. 1 is a schematic diagram illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view of the semiconductor device viewed from a conductor terminal (external connection terminal) side, and FIG. ) Is a cross-sectional view taken along line AA ′ of FIG.
[0039]
In FIG. 1, 1 is a semiconductor chip, 101 is an external electrode (bonding pad) of the semiconductor chip, 2 is a conductor terminal, 201 is a first conductor film (nickel alloy film), and 202 is a second conductor film (electrolytic copper plating film). , 203 is terminal plating (gold plating), 3 is a bonding wire, 4 is an insulator, and 5 is an adhesive (die paste).
[0040]
The semiconductor device of the present embodiment is a QFN type semiconductor device, and is provided along the semiconductor chip 1 and the outer periphery of the semiconductor chip 1 as shown in FIGS. A conductor terminal 2 electrically connected to the external terminal 101 of the semiconductor chip; a bonding wire 3 electrically connecting the external terminal 101 of the semiconductor chip and the conductor terminal 2; and the semiconductor chip 1 and the bonding wire 3 And an insulator 4 that seals the connecting portion between the bonding wire 3 and the conductor terminal 2. In addition, the adhesive 5 used when manufacturing the semiconductor device remains on the surface (non-circuit forming surface) facing the surface on which the external electrode 101 is provided of the semiconductor chip 1. Is sealed by the insulator 4 and the adhesive 5.
[0041]
Further, as shown in FIG. 1 (b), the conductor terminal 2 is formed by laminating a first conductor film 201, a second conductor film 202, and a terminal plating 203. The first conductor film 201 is exposed on the surface of the insulator 4. In the semiconductor device of this example, a nickel alloy film is used as the first conductor film 201, an electrolytic copper plating film is used as the second conductor film 202, and gold plating is used as the terminal plating 203.
[0042]
2 to 8 are schematic views for explaining the method of manufacturing the semiconductor device of this embodiment. FIGS. 2 (a), 2 (b), and 3 are respectively steps in the conductor terminal forming step. 4 is a plan view of the semiconductor chip mounting process, FIGS. 5 and 6 are cross-sectional views of the semiconductor chip mounting process, FIG. 7 is a cross-sectional view of the sealing process, and FIG. 8 is a cross-sectional view of the peeling process.
[0043]
The semiconductor device manufacturing method of this embodiment can be roughly divided into a conductor terminal forming step for forming the conductor terminal 2 on a predetermined substrate, and the semiconductor chip 1 is mounted on the substrate on which the conductor terminal 2 is formed. A semiconductor chip mounting step, a sealing step for sealing the semiconductor chip 1 mounted on the substrate, and a peeling step for peeling the sealed semiconductor chip 1 and the conductor terminal 2 from the substrate after the sealing step. It consists of four steps. A method for manufacturing the semiconductor device according to this embodiment will be described below with reference to FIGS.
[0044]
First, in the conductor terminal forming step, as shown in FIG. 2A, for example, a first conductor film 201 and a second conductor film 202 are laminated on the surface of an insulating substrate 6 made of polyimide resin. At this time, since the first conductor film 201 is peeled off from the insulating substrate 6 in a subsequent peeling step, it is preferable to use a conductor having a weak adhesion to the insulating substrate 6. In order to prevent peeling by an external force such as the above, a certain degree of adhesion is required in the semiconductor chip mounting step and the sealing step. Therefore, for the first conductor film 201, for example, a nickel alloy whose adhesion to the insulating substrate 6 is lowered when heated to a predetermined temperature is used. For example, the thickness is 5 nm (50 angstroms) by sputtering. It forms so that it may become the following. At this time, the nickel alloy film is preferably a nickel-chromium alloy with a chromium (Cr) weight percentage of 5% to 10%, for example. In the case of the nickel-chromium alloy, the nickel alloy film is in an atmosphere of 180 ° C. for about 1 hour. If left untreated, the adhesion (adhesion) with the insulating substrate (polyimide resin substrate) 6 is reduced to about 0.1 N / m. Further, at this time, the insulating substrate 6 having a higher oxygen permeability is more likely to have a lower adhesion with the first conductor film 201 when heated.
[0045]
The second conductor film 202 is, for example, an electrolytic copper plating film, and is formed by electrolytic plating using the first conductor film (nickel alloy film) 201 as a cathode.
[0046]
At this time, the insulating substrate 6 has a tape shape that is long in one direction like a tape material used in the manufacture of a conventional tape carrier, and the first conductive film 201 and the second conductive film 201 The conductor film 202 is formed by a reel method.
[0047]
Next, for example, as shown in FIG. 2B, a portion for forming the conductor terminal 2 as shown in FIG. 1A is opened on the second conductor film (electrolytic copper plating film) 202. A resist (plating resist) 7 is formed, and terminal plating 203 is formed on the opening of the plating resist 7, that is, on the exposed surface of the second conductor film 202. The plating resist 7 is formed by, for example, a photographic method in which a film resist is bonded to expose and develop a predetermined pattern, or a printing method in which a resist ink is printed using a screen plate. The terminal plating 203 is formed by electroless gold plating, for example, using electroless nickel plating as a base.
[0048]
At this time, since the plating resist 7 and the terminal plating 203 are formed by a reel method, the terminal plating 203 having a pattern as shown in FIG. 1A is formed in a region L1 where one semiconductor device is formed. A pattern similar to the pattern in the region L1 is continuously formed on the insulating substrate 6.
[0049]
Next, after removing the plating resist 7, the terminal plating 203 is used as a mask (etching resist), and the second conductor film 202 and the first conductor film 201 are etched as shown in FIG. Terminal 2 is formed. At this time, as an etching solution, for example, ferric chloride (FeClThree) Solution or cupric chloride (CuCl)2・ 2H2O) A solution is used.
[0050]
In the semiconductor chip mounting step performed next to the conductor terminal forming step, first, as shown in FIGS. 4 and 5, for example, in the chip mounting region of the substrate 6 on which the conductor terminal 2 is formed in the conductor terminal forming step, Then, the semiconductor chip 1 is bonded by applying an adhesive 5 such as a silver paste.
[0051]
Next, as shown in FIG. 6, the external electrode 101 of the semiconductor chip 1 and the conductor terminal 2 are electrically connected by a bonding wire 3. At this time, in order to reduce the loop height of the bonding wire 3, for example, the conductor terminal 2 is connected as a first bond by thermocompression bonding using ultrasonic waves, and the external electrode 101 of the semiconductor chip is connected to the second bond. As shown in FIG.
[0052]
In the sealing step performed after the semiconductor chip mounting step, the semiconductor chip 1, the bonding wire 3, and the connection portion between the bonding wire 3 and the conductor terminal 2 are sealed with an insulator 4. At this time, as shown in FIG. 7, the insulating substrate 6 on which the semiconductor chip 1 is mounted has an upper mold 8A provided with a space (cavity) 801A of a predetermined shape, and a flat plate shape that supports the substrate 1. For example, a melted thermosetting resin or an uncured thermosetting resin is used as the insulator 4 in the cavity 801A of the upper mold 8A. After pouring and filling and forming, the insulator 4 is heated and cured in a predetermined condition, for example, in an atmosphere of 180 ° C. for 5 to 6 hours. At this time, in the process of heating and curing the insulator 4, the adhesion between the first conductor film (nickel alloy film) 201 and the insulating substrate (polyimide resin substrate) 6 is reduced.
[0053]
In the sealing step, since the temperature when the insulator 4 is poured and molded is about 180 ° C. and the required time is about two minutes, the first conductor is poured when the insulator 4 is poured. The adhesion between the film (nickel alloy film) 201 and the insulating substrate (polyimide resin substrate) 6 does not decrease. Therefore, there is almost no possibility that the conductor terminal 2 is peeled off from the insulating substrate 1 by an external force when the insulator 4 is poured, and the insulator 4 is not bonded to the bonding interface between the first conductor film 201 and the insulating substrate 6. Will not flow.
[0054]
In the peeling step performed after the sealing step, for example, as shown in FIG. 8, the insulating substrate 6 is subjected to bending deformation using a roller 9 and sealed with a semiconductor device, that is, the insulator 4. The semiconductor chip 1, the bonding wire 3, and the conductor terminal 2 are peeled off from the insulating substrate 6. At this time, in the sealing step, the insulator 4 is cured by utilizing the fact that the adhesion force between the conductor terminal 2 and the insulating substrate 6 is reduced in the process of heating and curing the insulator 4. Immediately after taking out from the high-temperature furnace, the semiconductor device can be easily peeled by applying bending deformation to the insulating substrate 6 as shown in FIG.
[0055]
When the nickel alloy film 201 is formed on the surface of the polyimide resin substrate 6, for example, if the nickel alloy film 201 is left in an atmosphere of 180 ° C. for about 1 hour, the adhesion strength between the polyimide resin substrate 6 and the nickel alloy thin film 201 is increased. It will be about 0.1 N / m. On the other hand, the adhesive strength between the polyimide resin substrate 6 and the sealing insulator 4 is about 1 N / m, and the adhesive strength between the second conductor film (electrolytic copper plating film) 202 and the sealing insulator 4 is Since it is about 1 N / m, when the insulating substrate 6 is peeled from the conductor terminal 2 in the peeling step, the conductor wiring 2 is not easily peeled off from the sealing insulator 4. In addition, the manufacturing yield can be improved.
[0056]
Further, when the insulating substrate 6 is peeled off, the load applied to the conductor wiring 2 is about 10 gf, which is smaller than the load when cutting the conventional lead frame. ) Prevents the conductor terminal 2 from peeling off from the insulator 4 and falling off.
[0057]
After manufacturing the QFN type semiconductor device as shown in FIGS. 1A and 1B by the above procedure, the insulating substrate 6 is reused, and as shown in FIG. The first conductor 201 and the second conductor 202 are formed, and the above steps are repeated.
[0058]
As described above, according to the method of manufacturing a semiconductor device of this embodiment, the surface of the insulating substrate (polyimide resin substrate) 6 has adhesion (adhesion) with the insulating substrate 6 when heated on predetermined conditions. By forming the conductor terminal 2 with the first conductor film (nickel alloy film) 201, which is reduced in performance, as a base, the insulating substrate 6 and the conductor terminal 2 are in close contact during the sealing process. The force is increased to prevent the insulator 4 from flowing into the bonding interface between the conductor terminal 2 and the insulating substrate 6. After the sealing step, the insulating substrate 6 is heated under the predetermined conditions. By reducing the adhesion of the conductor terminal 2 and separating it, it is possible to reduce the exposure of the one surface of the conductor terminal 2, that is, the first conductor layer 201.
[0059]
In addition, by forming the conductor terminal 2 on the basis of the first conductor film (nickel alloy film) 201 whose adhesion with the insulating substrate (polyimide resin substrate) 6 is reduced when heated under the predetermined conditions. The load applied when the conductor terminal 2 is peeled from the insulating substrate 6 in the peeling step can be reduced, and the conductor terminal 2 is difficult to peel from the insulator 4 that seals the semiconductor chip 1. Can do.
[0060]
In addition, since the exposed area of the conductor terminal 2 is not narrowed or blocked from a predetermined area, the defect of the semiconductor device due to the defect of the exposed surface of the conductor terminal 2 is reduced, and the manufacturing yield is improved. The manufacturing cost of the semiconductor device can be reduced.
[0061]
In addition, since the conductor terminal 2 of the semiconductor device after sealing is protected by the insulating substrate 6 until the insulating substrate 6 is peeled in the peeling step, the exposed surface of the conductor terminal 2, that is, the first It is possible to prevent the surface of the one conductor film 201 from being damaged and the mountability from being deteriorated.
[0062]
In addition, since a semiconductor device can be manufactured by a reel-to-reel method that has been conventionally used for manufacturing tape carriers by using the tape-like insulating substrate 6, a large amount of semiconductor devices can be manufactured at a time, and productivity Therefore, the manufacturing cost of the device can be reduced.
[0063]
Further, since the insulating substrate 6 can be reused after the peeling step, there is almost no increase in manufacturing cost due to the use of the insulating substrate 6. Further, since the conductor terminal 2 can be efficiently formed on the insulating substrate 6, the material cost of the conductor terminal 2 can be reduced and the manufacturing cost of the semiconductor device can be reduced as compared with a conventional manufacturing method using a lead frame. be able to.
[0064]
Further, as in the semiconductor device of this embodiment, the semiconductor chip 1 is bonded onto the insulating substrate 6 and the conductor terminals 2 and the external electrodes 101 of the semiconductor chip are connected by reverse bonding, Compared to a semiconductor device using a lead frame as shown in FIG. 11B, the thickness can be reduced.
[0065]
In the semiconductor device of this embodiment, as shown in FIG. 2A, the first conductor film (nickel alloy film) 201 and the second conductor film (electrolytic copper plating) are formed on the surface of the insulating substrate 6. Film) 202 is formed, then the terminal plating 203 is formed, the first conductor film 201 and the second conductor film 202 are etched using the terminal plating 203 as an etching resist, and the conductor terminal 2 is formed. However, the present invention is not limited to this. For example, instead of forming the terminal plating 203, it is needless to say that other etching resists may be formed and etched. When the conductor terminal 2 is miniaturized, the first conductor film 201 is formed on the surface of the insulating substrate 6, and the second conductor (only the portion where the conductor terminal 2 is formed is formed by an additive method. After forming (electrolytic copper plating) 202, unnecessary portions of the first conductor 201 may be removed by quick etching.
[0066]
FIG. 9 is a schematic view showing a modified example of the semiconductor device of the embodiment, FIG. 9A is a plan view seen from the conductor terminal 2 side of the semiconductor device, and FIG. 9B is FIG. 9A. It is sectional drawing in the BB 'line | wire. Note that the cross-sectional view of FIG. 9B shows the semiconductor device of FIG. 9A upside down.
[0067]
In the semiconductor device of the embodiment, as shown in FIGS. 4 and 5, the conductor terminal 2 is disposed outside the region of the insulating substrate 6 where the semiconductor chip 1 is mounted, and the conductor terminal 2 is disposed on the insulating substrate 6. Since the semiconductor chip 1 is bonded using an adhesive (silver paste) 5, the adhesive 5 is exposed on the surface of the sealing insulator 4. As shown in FIGS. 9 (a) and 9 (b), one end of the conductor terminal 2 is provided so as to protrude into a region where the semiconductor chip 1 is mounted, and the conductor is formed using a film adhesive 5 ′. The semiconductor chip 1 may be bonded onto the terminal 2. In this case, a gap is formed between the insulating substrate 6 and the semiconductor chip 1 by the height of the conductor terminal 2, and the insulating substrate 6 and the semiconductor chip are formed in the sealing step shown in FIG. 1, the sealing insulator 4 enters and the film adhesive 5 ′ is not exposed.
[0068]
In the semiconductor device where the adhesive (silver paste) 5 is exposed as shown in FIG. 1A and FIG. 1B, the bonding is performed when the insulating substrate 6 is peeled off or after the peeling step. The adhesive 5 may be peeled off to expose the semiconductor chip 1, and the semiconductor chip 1 may be scratched. As shown in FIGS. 9A and 9B, the adhesive 5 may also be damaged. By sealing the inside of the sealing insulator 4, the semiconductor chip 1 can be prevented from being exposed and damaged, and the reliability of the semiconductor device can be further improved.
[0069]
FIG. 10 is a schematic view showing another modification of the semiconductor device of the embodiment, FIG. 10 (a) is a plan view seen from the semiconductor chip side, and FIG. 10 (b) is the semiconductor of FIG. 10 (a). It is sectional drawing which looked at the apparatus from the side surface direction. In FIG. 10A, the insulator for sealing the semiconductor chip is omitted.
[0070]
In the semiconductor device of the embodiment, as shown in FIGS. 1A and 1B, the conductor terminals 2 are arranged in a line along the end portion of the device. For example, as shown in FIG. 10A, the external electrodes 101 and the conductor terminals 2 of the semiconductor chip 1 may be arranged in a staggered arrangement. In this case, since the number of the conductor terminals 2 is increased and densely arranged, for example, as shown in FIG. 10B, by performing wire bonding with different loop heights, the bonding wires 3 can be connected to each other. Prevent short-circuit failure due to contact.
[0071]
As shown in FIGS. 1A and 1B, when the conductor terminals 2 are arranged in a line, the semiconductor device becomes larger as the number of external electrodes (bonding pads) 101 on the semiconductor chip increases. As shown in FIGS. 10 (a) and 10 (b), the conductor terminals 2 are arranged in a staggered arrangement to increase the number of pins, that is, when the number of the conductor terminals 2 is increased. The rate at which the semiconductor device increases in size can be reduced.
[0072]
Further, in the semiconductor device shown in FIGS. 10A and 10B, the conductor terminals 2 are arranged in a staggered arrangement. However, the present invention is not limited to this, and a conventional LGA (Land Grid Array) type semiconductor device is used. Thus, it goes without saying that the conductor terminals 2 may be arranged in a grid of two or more rows.
[0073]
The present invention has been specifically described above based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. .
[0074]
For example, in the above embodiment, the QFN type semiconductor device in which the external terminals are arranged along the four sides of the semiconductor device is taken as an example. However, the present invention is not limited to this, for example, two opposing sides of the semiconductor device. Alternatively, a SON type semiconductor device in which the external terminals are arranged may be used.
[0075]
Further, in the method of manufacturing a semiconductor device of the embodiment, in the sealing step, the first conductor film (nickel alloy film) 201 and the insulating substrate (polyimide resin substrate) are heated by heating when the insulator 4 is cured. 6, and the insulating substrate 6 was peeled off immediately after that. However, the present invention is not limited to this. For example, the first conductive film 201 is heated by a process different from the sealing process. Needless to say, the adhesion of the insulating substrate 6 may be reduced.
[0076]
【The invention's effect】
The effects obtained by typical ones of the inventions disclosed in the present invention will be briefly described as follows.
[0077]
  (1)According to the present invention, since the semiconductor chip and the conductor terminal sealed with the sealing insulator are separated from the insulating substrate, the mounting surface of the conductor terminal is inserted into the sealing insulator. Can be reliably exposed to the outside, and after using the polyimide as the insulating substrate and the nickel alloy as the conductor terminal, the adhesion between the insulating substrate and the conductor terminal is reduced after the sealing process and peeling Can be easier.
[0078]
(2) In a QFN type or SON type semiconductor device, the manufacturing yield of the device can be improved and the manufacturing cost can be reduced.
[0079]
(3) In a QFN type or SON type semiconductor device, the productivity of the device can be improved and the manufacturing cost can be reduced.
[0080]
(4) In a QFN type or SON type semiconductor device, the device can be thinned.
[0081]
(5) In a QFN type or SON type semiconductor device, an increase in size of the device due to an increase in the number of pins can be prevented.
[Brief description of the drawings]
1A and 1B are schematic views showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view of the semiconductor device viewed from a conductor terminal side, and FIG. It is sectional drawing in the AA 'line of a).
FIGS. 2A and 2B are schematic views for explaining a method for manufacturing a semiconductor device according to the present embodiment, and FIGS. 2A and 2B are cross-sectional views at respective steps in a conductor terminal forming step. FIGS. .
FIG. 3 is a schematic view for explaining the method for manufacturing the semiconductor device of this example, and is a cross-sectional view in a conductor terminal forming step.
FIG. 4 is a schematic view for explaining the method for manufacturing the semiconductor device of the present embodiment, and is a plan view in the semiconductor chip mounting step.
5 is a schematic view for explaining the method for manufacturing the semiconductor device of the present embodiment, and is a cross-sectional view seen from the side surface direction of FIG. 4;
FIG. 6 is a schematic view for explaining the method for manufacturing the semiconductor device of this example, and is a cross-sectional view of a wire bonding step.
FIG. 7 is a schematic view for explaining the method for manufacturing the semiconductor device of this example, and is a cross-sectional view in a sealing step.
FIG. 8 is a schematic view for explaining the method for manufacturing the semiconductor device of this example, and is a cross-sectional view in a peeling step;
9A and 9B are schematic views showing a modification of the semiconductor device of the embodiment, FIG. 9A is a plan view seen from the conductor terminal side of the semiconductor device, and FIG. 9B is a plan view of FIG. 9A. It is sectional drawing in a BB 'line.
10 is a schematic diagram showing another modification of the semiconductor device of the embodiment, FIG. 10 (a) is a plan view seen from the chip side of the semiconductor device, and FIG. 10 (b) is FIG. 10 (a). It is sectional drawing seen from the side surface direction.
11A and 11B are schematic views showing a schematic configuration of a conventional QFN type semiconductor device, in which FIG. 11A is a plan view seen from the conductor terminal (lead) side of the device, and FIG. It is sectional drawing in the CC 'line | wire of a).
FIG. 12 is a schematic view for explaining a conventional method for manufacturing a QFN type semiconductor device, and is a plan view showing a schematic configuration of a lead frame used;
FIGS. 13A and 13B are schematic views for explaining a conventional method of manufacturing a QFN type semiconductor device, and FIGS. 13A and 13B are cross-sectional views of a process for mounting a semiconductor chip, respectively. FIGS.
14A and 14B are schematic views for explaining a conventional method for manufacturing a QFN type semiconductor device, in which FIG. 14A is a cross-sectional view of a sealing process, and FIG. 14B is a cross-sectional view of an individualization process; It is.
FIG. 15 is a schematic diagram for explaining a problem of a conventional QFN type semiconductor device.
FIG. 16 is a schematic diagram for explaining another problem of the conventional QFN type semiconductor device.
[Explanation of symbols]
1 Semiconductor chip
101 External electrode (bonding pad)
2 Conductor terminal (lead)
201 First conductor film (nickel alloy film)
202 2nd conductor film (electrolytic copper plating film)
203 Contact plating
3 Bonding wire
4 Insulator
5 Adhesive (die paste)
5 'film adhesive
6 Insulating substrate (polyimide resin substrate)
7 resist (plating resist)
8A Upper mold
801A cavity
8B Lower mold
9 Roller
10 Lead frame
11 Hexagonal conductor terminals

Claims (3)

ポリイミド樹脂基板を絶縁基板として用い、前記絶縁基板の表面に所定のパターンの導体端子を形成する導体端子形成工程と、前記導体端子が形成された絶縁基板上に半導体チップを接着し、前記半導体チップの外部電極（ボンディングパッド）と前記導体端子を電気的に接続する半導体チップ実装工程と、前記半導体チップ、前記導体端子、及び前記半導体チップの外部電極と前記導体端子との接続部分を絶縁体で封止する封止工程と、前記封止工程の後、前記絶縁体で封止された前記半導体チップ及び前記導体端子を前記絶縁基板から剥離する剥離工程とを備える半導体装置の製造方法であって、前記導体端子形成工程は、前記絶縁基板の表面に、所定の温度に加熱したときに前記絶縁基板との密着力が低下するニッケル合金からなる導体を用いて前記導体端子を形成し、前記剥離工程は、前記所定の温度に加熱して前記絶縁基板と前記導体端子との密着力を低下させてから剥離することを特徴とする半導体装置の製造方法。 Using a polyimide resin substrate as an insulating substrate , forming a conductor terminal of a predetermined pattern on the surface of the insulating substrate, bonding a semiconductor chip on the insulating substrate on which the conductor terminal is formed, and the semiconductor chip A semiconductor chip mounting step for electrically connecting the external electrode (bonding pad) and the conductor terminal, and the semiconductor chip, the conductor terminal, and a connection portion between the external electrode and the conductor terminal of the semiconductor chip with an insulator . A method for manufacturing a semiconductor device , comprising: a sealing step for sealing ; and a peeling step for peeling the semiconductor chip and the conductor terminal sealed with the insulator from the insulating substrate after the sealing step. the conductor terminal forming step, composed of the surface of the insulating substrate, a nickel alloy adhesion between the insulating substrate when heated to a predetermined temperature is lowered guide Wherein forming a conductive terminal using, the peeling step is the manufacture of semiconductor devices, which comprises peeling and thus reduce the adhesion between the predetermined said insulating substrate is heated to a temperature between the conductor terminal Method. 前記導体端子形成工程は、前記絶縁基板上に、所定の温度で所定時間加熱したときに前記絶縁基板との密着力が低下するニッケル合金からなる第１導体膜を形成し、前記第１導体膜上に、第２導体膜を積層して前記導体端子を形成することを特徴とする請求項１に記載の半導体装置の製造方法。 The conductor terminal forming step forms, on the insulating substrate, a first conductor film made of a nickel alloy whose adhesion to the insulating substrate decreases when heated at a predetermined temperature for a predetermined time, and the first conductor film The method of manufacturing a semiconductor device according to claim 1, wherein the conductor terminal is formed by laminating a second conductor film thereon. 前記封止工程は、前記絶縁体として熱硬化性樹脂を用い、溶融した前記熱硬化性樹脂を成形した後、所定の温度で所定時間加熱して前記熱硬化性樹脂を硬化させるとともに、前記導体端子と前記絶縁基板との密着力を低下させることを特徴とする請求項１または請求項２に記載の半導体装置の製造方法。In the sealing step, a thermosetting resin is used as the insulator , and after the molten thermosetting resin is molded, the thermosetting resin is cured by heating at a predetermined temperature for a predetermined time, and the conductor The method for manufacturing a semiconductor device according to claim 1, wherein adhesion between the terminal and the insulating substrate is reduced.
JP2001268413A 2001-09-05 2001-09-05 Manufacturing method of semiconductor device Expired - Fee Related JP3869693B2 (en)

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