JP2016029724A - Electronic circuit and electronic component - Google Patents

Electronic circuit and electronic component Download PDF

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Publication number
JP2016029724A
JP2016029724A JP2015180586A JP2015180586A JP2016029724A JP 2016029724 A JP2016029724 A JP 2016029724A JP 2015180586 A JP2015180586 A JP 2015180586A JP 2015180586 A JP2015180586 A JP 2015180586A JP 2016029724 A JP2016029724 A JP 2016029724A
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electronic component
external electrode
electronic
electrode terminals
circuit board
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Inventor
玲 米山
Rei Yoneyama
玲 米山
西田　信也
Shinya Nishida
信也 西田
浩之 岡部
Hiroyuki Okabe
浩之 岡部
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an electronic circuit on which an electronic component is mounted, the electronic component having an insulation distance between external electrode terminals reduced further more, and to provide an electronic component having an insulation distance between external electrode terminals reduced further more.SOLUTION: An electronic component 400 according to the present invention includes a plurality of external electrode terminals 11 having different potentials with each other on a package surface. In the electronic component, a thermosetting resin 4B is provided along the surface of a package between the external electrode terminals 11.SELECTED DRAWING: Figure 4

Description

本発明は、表面実装部品が実装された電子回路および表面実装部品に関する。   The present invention relates to an electronic circuit on which a surface mount component is mounted and a surface mount component.

従来、表面実装部品をプリント基板上に実装する際に、表面実装部品の外部電極端子間に電位差がある場合は、その電位差に応じて、絶縁のために外部電極端子間に適切な絶縁距離が確保される。   Conventionally, when a surface mount component is mounted on a printed circuit board, if there is a potential difference between the external electrode terminals of the surface mount component, an appropriate insulation distance is provided between the external electrode terminals for insulation according to the potential difference. Secured.

また、空気による絶縁では不十分な場合、外部電極端子間に絶縁性の樹脂を注入することにより、絶縁性の向上が行われている（例えば、特許文献１）。   In addition, when insulation with air is insufficient, the insulation is improved by injecting an insulating resin between the external electrode terminals (for example, Patent Document 1).

特開２０００−２４４０７７号公報（第５頁、第３図）Japanese Unexamined Patent Publication No. 2000-244077 (page 5, FIG. 3)

上述した様に、表面実装部品において、外部電極端子間の絶縁を空気ではなく樹脂で行うことにより、絶縁距離を小さくすることが可能となるため、表面実装部品の小型化の観点から好ましい。ところが、外部電極端子間の隙間は一般に狭いため、樹脂の注入が困難な場合があった。   As described above, in the surface mount component, insulation between the external electrode terminals is performed with resin instead of air, so that the insulation distance can be reduced, which is preferable from the viewpoint of miniaturization of the surface mount component. However, since the gap between the external electrode terminals is generally narrow, it may be difficult to inject the resin.

本発明は以上の課題を解決するためになされたものであり、外部電極端子間の絶縁距離がより小さい電子部品が実装された電子回路および外部電極端子間の絶縁距離がより小さい電子部品の提供を目的とする。   The present invention has been made to solve the above problems, and provides an electronic circuit in which an electronic component having a smaller insulation distance between external electrode terminals and an electronic component having a smaller insulation distance between external electrode terminals are provided. With the goal.

本発明に係る電子部品は、電位の異なる複数の外部電極端子をパッケージ表面に備え、外部電極端子間には、熱硬化性樹脂がパッケージの表面に沿って設けられていることを特徴とする。   The electronic component according to the present invention includes a plurality of external electrode terminals having different potentials on a package surface, and a thermosetting resin is provided between the external electrode terminals along the surface of the package.

また、本発明に係る電子回路は、電位の異なる複数の外部電極端子をパッケージ上面に備える電子部品と、電子部品のパッケージ下面と接着されたプリント基板と、外部電極端子の各々とプリント基板を電気的に接合するワイヤとを備え、電子部品、ワイヤ、電子部品とプリント基板の接着部およびワイヤとプリント基板との接合部は絶縁性樹脂で封止されることを特徴とする。   The electronic circuit according to the present invention includes an electronic component having a plurality of external electrode terminals having different potentials on the upper surface of the package, a printed circuit board bonded to the lower surface of the electronic component, and each of the external electrode terminals and the printed circuit board. And a bonding part between the electronic component and the printed circuit board and a bonding part between the wire and the printed circuit board are sealed with an insulating resin.

本発明によれば、電子部品の電位の異なる外部電極端子間に、パッケージ表面に沿って熱硬化性樹脂が塗布されているため、電子部品をプリント基板に実装すると、電子部品とプリント基板の隙間において、外部電極端子間が熱硬化性樹脂により充填される。よって、電位の異なる外部電極端子間の絶縁性が向上するため、電位の異なる外部電極端子間の絶縁距離を小さくすることが可能であり、電子部品を小型化することができる。また、電子部品の小型化により、電子部品を実装したプリント基板の小型化も可能である。   According to the present invention, since the thermosetting resin is applied along the package surface between the external electrode terminals having different electric potentials of the electronic component, when the electronic component is mounted on the printed board, the gap between the electronic component and the printed board is The space between the external electrode terminals is filled with a thermosetting resin. Therefore, since the insulation between the external electrode terminals having different potentials is improved, the insulation distance between the external electrode terminals having different potentials can be reduced, and the electronic component can be miniaturized. In addition, by downsizing the electronic component, the printed circuit board on which the electronic component is mounted can be downsized.

また、本発明によれば、電子部品のパッケージ上面に外部電極端子を設けたことにより、電子部品を絶縁性樹脂で封止すると、パッケージ上面に備わる外部電極端子も樹脂封止される。よって、外部電極端子間の絶縁性が向上する。つまり、絶縁距離をより小さくすることが可能である。このため、電子部品の小型化が可能であり、電子部品が実装される電子回路を小型化することが可能である。また、外部電極端子が電子部品のパッケージ上面に設けられるため、接合部分の外観を検査することが可能であり、製造工程において歩留まりが向上する。   According to the present invention, since the external electrode terminal is provided on the upper surface of the package of the electronic component, when the electronic component is sealed with the insulating resin, the external electrode terminal provided on the upper surface of the package is also resin-sealed. Therefore, the insulation between the external electrode terminals is improved. That is, the insulation distance can be further reduced. For this reason, the electronic component can be downsized, and the electronic circuit on which the electronic component is mounted can be downsized. Further, since the external electrode terminal is provided on the upper surface of the package of the electronic component, it is possible to inspect the appearance of the joint portion, and the yield is improved in the manufacturing process.

実施の形態１に係る電子回路の断面図および平面図である。FIG. 2 is a cross-sectional view and a plan view of the electronic circuit according to the first embodiment. 実施の形態２に係る電子回路の断面図である。FIG. 6 is a cross-sectional view of an electronic circuit according to a second embodiment. 実施の形態３に係る電子回路の断面図である。FIG. 6 is a cross-sectional view of an electronic circuit according to a third embodiment. 実施の形態４に係る電子部品および電子回路の断面図である。FIG. 6 is a cross-sectional view of an electronic component and an electronic circuit according to a fourth embodiment. 実施の形態５に係る電子回路の断面図である。FIG. 10 is a cross-sectional view of an electronic circuit according to a fifth embodiment. 前提技術に係る電子回路の断面図である。It is sectional drawing of the electronic circuit which concerns on a premise technique.

＜前提技術＞
本発明の実施の形態を説明する前に、本発明の前提となる技術の説明をする。図６（ａ）および図６（ｂ）に、前提技術となる電子回路の断面図を示す。 <Prerequisite technology>
Prior to describing the embodiments of the present invention, the technology which is the premise of the present invention will be described. FIG. 6A and FIG. 6B are cross-sectional views of an electronic circuit as a prerequisite technology.

図６（ａ）は、プリント基板２上に電子部品１を実装した電子回路である。電子部品１は、例えば、ＱＦＮ（Ｑｕａｄ Ｆｌａｔ Ｎｏｎ−ｌｅａｄｅｄ Ｐａｃｋａｇｅ）やＳＯＮ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｎｏｎ−ｌｅａｄｅｄ Ｐａｃｋａｇｅ）などのフラットパッケージである。   FIG. 6A shows an electronic circuit in which the electronic component 1 is mounted on the printed circuit board 2. The electronic component 1 is, for example, a flat package such as QFN (Quad Flat Non-leaded Package) or SON (Small Outline Non-leaded Package).

電子部品１に備わる外部電極端子１１は、はんだ３を介して、プリント基板２に備わるプリント基板側ランド２１にはんだ接合されている。電子部品１とプリント基板２の間には隙間５が設けられている。   The external electrode terminal 11 provided in the electronic component 1 is soldered to the printed circuit board side land 21 provided in the printed circuit board 2 via the solder 3. A gap 5 is provided between the electronic component 1 and the printed board 2.

一般に、電子部品１をプリント基板２に実装した後、図６（ａ）の様に、電子部品１は絶縁性樹脂４により封止される。この際、電子部品１とプリント基板２の間の隙間５にも絶縁性樹脂４が注入されることが絶縁の観点から望ましい。ところが、絶縁性樹脂４の粘性が高い場合には、電子部品１とプリント基板２の隙間５が狭いため、隙間５に絶縁性樹脂４が充填されないことがあった。   In general, after the electronic component 1 is mounted on the printed circuit board 2, the electronic component 1 is sealed with an insulating resin 4 as shown in FIG. At this time, it is desirable from the viewpoint of insulation that the insulating resin 4 is also injected into the gap 5 between the electronic component 1 and the printed board 2. However, when the viscosity of the insulating resin 4 is high, the gap 5 between the electronic component 1 and the printed circuit board 2 is narrow, and the gap 5 may not be filled with the insulating resin 4 in some cases.

隙間５に絶縁性樹脂４が充填されない場合、電子部品１の外部電極端子１１間の絶縁を考慮して外部電極端子１１間の絶縁距離Ｌを設計する必要がある。つまり、外部電極端子１１間の電位差が大きい場合、絶縁距離Ｌを大きくとって電子部品１を設計する必要がある。絶縁距離Ｌが大きくなることによって、電子部品１が大型化し、電子部品１が実装される電子回路も大型化する問題があった。   When the gap 5 is not filled with the insulating resin 4, it is necessary to design the insulation distance L between the external electrode terminals 11 in consideration of the insulation between the external electrode terminals 11 of the electronic component 1. That is, when the potential difference between the external electrode terminals 11 is large, it is necessary to design the electronic component 1 with a large insulation distance L. As the insulation distance L is increased, the electronic component 1 is increased in size and the electronic circuit on which the electronic component 1 is mounted is also increased in size.

また、図６（ｂ）に、電子部品１が、外部に露呈したダイパッド１１Ａを有する場合の例を示す。ダイパッド１１Ａは、外部電極端子１１と同様に、プリント基板側ランド２１にはんだ接合されている。例えば、図６（ｂ）において、左側の外部電極端子１１とダイパッド１１Ａとの間に電位差がある場合を考える。この場合、隙間５に絶縁性樹脂４が充填されない場合、絶縁のために、この間の絶縁距離Ｌを考慮して電子部品１を設計する必要がある。つまり、外部電極端子１１とダイパッド１１Ａとの電位差が大きい場合、絶縁距離Ｌを大きくとって電子部品１を設計する必要がある。絶縁距離Ｌが大きくなることによって、電子部品１が大型化し、電子部品１が実装される電子回路も大型化する問題があった。   FIG. 6B shows an example in which the electronic component 1 has a die pad 11A exposed to the outside. Similarly to the external electrode terminal 11, the die pad 11 </ b> A is soldered to the printed circuit board side land 21. For example, in FIG. 6B, consider a case where there is a potential difference between the left external electrode terminal 11 and the die pad 11A. In this case, when the insulating resin 4 is not filled in the gap 5, it is necessary to design the electronic component 1 in consideration of the insulation distance L between them for insulation. That is, when the potential difference between the external electrode terminal 11 and the die pad 11A is large, it is necessary to design the electronic component 1 with a large insulation distance L. As the insulation distance L is increased, the electronic component 1 is increased in size and the electronic circuit on which the electronic component 1 is mounted is also increased in size.

＜実施の形態１＞
＜構成＞
図１（ａ）に、本実施の形態における電子回路１００の断面図を示す。また、図１（ｂ）は、図１（ａ）において絶縁性樹脂６を除いた電子回路１００の断面図である。本実施の形態において、電子部品１は、前提技術（図６（ｂ））と同様に、例えばＱＦＮまたはＳＯＮであり、外部に露呈したダイパッド１１Ａと、外部電極端子１１を有するとする。電子部品１には、ワイドバンドギャップ半導体として、例えばＳｉＣ半導体素子が搭載されている。 <Embodiment 1>
<Configuration>
FIG. 1A shows a cross-sectional view of an electronic circuit 100 in the present embodiment. FIG. 1B is a cross-sectional view of the electronic circuit 100 from which the insulating resin 6 is removed in FIG. In the present embodiment, the electronic component 1 is, for example, QFN or SON, as in the base technology (FIG. 6B), and has a die pad 11A exposed to the outside and an external electrode terminal 11. For example, a SiC semiconductor element is mounted on the electronic component 1 as a wide band gap semiconductor.

プリント基板２はプリント基板側ランド２１を備える。電子部品１の外部電極端子１１およびダイパッド１１Ａと、プリント基板２のプリント基板側ランド２１は、はんだ３を介してはんだ接合されている。   The printed circuit board 2 includes a printed circuit board side land 21. The external electrode terminal 11 and the die pad 11 </ b> A of the electronic component 1 and the printed circuit board side land 21 of the printed circuit board 2 are soldered via the solder 3.

図１（ａ），（ｂ）において、左側の外部電極端子１１とダイパッド１１Ａとの間に電位差がある場合を考える。この場合、図１（ｂ）に示すように、プリント基板２には、平面視で、左側の外部電極端子１１とダイパッド１１Ａの間に、穴７が設けられる。また、電子部品１とプリント基板２の間には隙間５が設けられている。   1A and 1B, consider a case where there is a potential difference between the left external electrode terminal 11 and the die pad 11A. In this case, as shown in FIG. 1B, the printed board 2 is provided with a hole 7 between the left external electrode terminal 11 and the die pad 11A in plan view. A gap 5 is provided between the electronic component 1 and the printed board 2.

本実施の形態における電子回路１００の製造方法は、電子部品１をプリント基板２にはんだ接合する工程と、この工程の後に、プリント基板２に設けられた穴７を通して、プリント基板２裏側から、隙間５に絶縁性樹脂６を注入する工程を備える。この結果、隙間５に絶縁性樹脂６が充填されて、図１（ａ）の状態となる。   The manufacturing method of the electronic circuit 100 according to the present embodiment includes a step of soldering the electronic component 1 to the printed board 2 and a gap 7 from the back side of the printed board 2 through the hole 7 provided in the printed board 2 after this step. 5 is provided with a step of injecting an insulating resin 6. As a result, the gap 5 is filled with the insulating resin 6, and the state shown in FIG.

なお、図１（ａ）に示す様に、絶縁性樹脂６を注入する際に、同時にプリント基板２の裏面を絶縁性樹脂６でコーティングしてもよい。   As shown in FIG. 1A, when the insulating resin 6 is injected, the back surface of the printed circuit board 2 may be coated with the insulating resin 6 at the same time.

また、前提技術において電子部品１の表側を絶縁性樹脂４により封止したのと同様に、本実施の形態においても、電子部品１の表側を絶縁性樹脂により封止しても良い。   Further, similarly to the base technology in which the front side of the electronic component 1 is sealed with the insulating resin 4, in this embodiment, the front side of the electronic component 1 may be sealed with the insulating resin.

本実施の形態では、電位差のあるダイパッド１１Ａと外部電極端子１１間の隙間５に絶縁性樹脂６が充填されることにより、ダイパッド１１Ａと外部電極端子１１間がより確実に絶縁される。よって、電子部品１において、ダイパッド１１Ａと外部電極端子１１間の絶縁距離Ｌを前提技術よりも小さく設計することが可能である。   In the present embodiment, the gap 5 between the die pad 11A having a potential difference and the external electrode terminal 11 is filled with the insulating resin 6, so that the die pad 11A and the external electrode terminal 11 are more reliably insulated. Therefore, in the electronic component 1, it is possible to design the insulation distance L between the die pad 11A and the external electrode terminal 11 to be smaller than that of the base technology.

なお、本実施の形態において、絶縁性樹脂６は、図１（ａ）の様に、隙間５を完全に充填している。このように、隙間５が絶縁性樹脂６によって完全に充填されるのが絶縁の観点から最も好ましいが、隙間５の一部を充填した場合であっても、ダイパッド１１Ａと外部電極端子１１間の沿面距離を大きくすることが可能であるため、ダイパッド１１Ａと外部電極端子１１間の絶縁性を高めて、絶縁距離Ｌを小さくすることができる。   In the present embodiment, the insulating resin 6 completely fills the gap 5 as shown in FIG. As described above, it is most preferable from the viewpoint of insulation that the gap 5 is completely filled with the insulating resin 6. However, even when a part of the gap 5 is filled, the gap between the die pad 11 </ b> A and the external electrode terminal 11 is satisfied. Since the creepage distance can be increased, the insulation between the die pad 11A and the external electrode terminal 11 can be improved, and the insulation distance L can be reduced.

また、本実施の形態における電子回路１００の平面図の一例を図１（ｃ）に示す。例えば、左側の列の外部電極端子１１とダイパッド１１Ａとの間に電位差がある場合、穴７をスリット形状とすることによって、左側の列の外部電極端子１１とダイパッド１１Ａとの間に、効率よく絶縁性樹脂６を注入することが可能となる。   An example of a plan view of the electronic circuit 100 in this embodiment is shown in FIG. For example, when there is a potential difference between the external electrode terminal 11 in the left column and the die pad 11A, the hole 7 is formed in a slit shape so that the hole 7 can be efficiently connected between the external electrode terminal 11 in the left column and the die pad 11A. It becomes possible to inject the insulating resin 6.

なお、本実施の形態において、電子部品１は、ワイドバンドギャップ半導体素子として、ＳｉＣ半導体素子を搭載するとしたが、ＧａＮ半導体素子等でもよい。   In the present embodiment, the electronic component 1 is mounted with a SiC semiconductor element as a wide band gap semiconductor element, but may be a GaN semiconductor element or the like.

＜効果＞
本実施の形態における電子回路１００は、プリント基板２と、プリント基板２上にはんだ接合された電子部品１とを備え、電子部品１は、外部に露呈したダイパッド１１Ａと、外部電極端子１１とを有するフラットパッケージであり、プリント基板２と電子部品１との間には隙間５が設けられ、プリント基板２には、平面視でダイパッド１１Ａと、外部電極端子１１との間に穴７が設けられており、隙間５において、絶縁性樹脂６は、ダイパッド１１Ａと、外部電極端子１１との間の少なくとも一部に充填されており、絶縁性樹脂６は、穴７から注入されたものであることを特徴とする。 <Effect>
The electronic circuit 100 according to the present embodiment includes a printed circuit board 2 and an electronic component 1 soldered on the printed circuit board 2. The electronic component 1 includes a die pad 11A exposed to the outside and an external electrode terminal 11. A gap 5 is provided between the printed circuit board 2 and the electronic component 1, and the printed circuit board 2 is provided with a hole 7 between the die pad 11 </ b> A and the external electrode terminal 11 in plan view. In the gap 5, the insulating resin 6 is filled in at least a part between the die pad 11 </ b> A and the external electrode terminal 11, and the insulating resin 6 is injected from the hole 7. It is characterized by.

従って、プリント基板２に設けられた穴７から絶縁性樹脂６を注入することにより、ダイパッド１１Ａと、外部電極端子１１との間の隙間５の少なくとも一部に絶縁性樹脂６が確実に充填されるため、ダイパッド１１Ａと外部電極端子１１との間の絶縁性が向上する。よって、電子部品１において、ダイパッド１１Ａと外部電極端子１１間の絶縁距離Ｌを前提技術（図６（ｂ））よりも小さく設計することが可能であるため、電子部品１の小型化が可能である。また、電子部品１の小型化により電子部品１が実装される電子回路１００の小型化が可能である。   Therefore, by injecting the insulating resin 6 from the hole 7 provided in the printed circuit board 2, the insulating resin 6 is reliably filled in at least a part of the gap 5 between the die pad 11 </ b> A and the external electrode terminal 11. Therefore, the insulation between the die pad 11A and the external electrode terminal 11 is improved. Therefore, in the electronic component 1, the insulation distance L between the die pad 11 </ b> A and the external electrode terminal 11 can be designed to be smaller than that of the base technology (FIG. 6B), and thus the electronic component 1 can be downsized. is there. Further, the electronic circuit 100 on which the electronic component 1 is mounted can be downsized by downsizing the electronic component 1.

また、本実施の形態における電子回路１００において、電子部品１は、ワイドバンドギャップ半導体素子を備えることを特徴とする。   In the electronic circuit 100 according to the present embodiment, the electronic component 1 includes a wide band gap semiconductor element.

従って、一般に、ワイドバンドギャップ半導体素子は一般に高電圧が印加されて使用されるため、ダイパッド１１Ａと外部電極端子１１との間には、大きな電位差が生じる。よって、ダイパッド１１Ａと、ダイパッド１１Ａと大きな電位差の生じる外部電極端子１１間の隙間５を絶縁性樹脂６で充填することにより、絶縁性の向上が顕著に現れるため、特に効果的に絶縁距離Ｌを小さくすることが可能である。   Accordingly, in general, since a wide band gap semiconductor element is generally used with a high voltage applied, a large potential difference is generated between the die pad 11A and the external electrode terminal 11. Therefore, by filling the gap 5 between the die pad 11A and the external electrode terminal 11 in which a large potential difference with the die pad 11A is filled with the insulating resin 6, the improvement of the insulating property appears remarkably. It can be made smaller.

また、本実施の形態における電子回路１００の製造方法は、電子部品１を穴７が設けられたプリント基板２にはんだ接合する工程と、この工程の後に、穴７から絶縁性樹脂６を注入する工程とを備える。   In addition, the method of manufacturing the electronic circuit 100 according to the present embodiment includes a step of soldering the electronic component 1 to the printed circuit board 2 provided with the holes 7, and an insulating resin 6 is injected from the holes 7 after this step. A process.

従って、プリント基板２に穴７を設けて、穴７を通して隙間５に絶縁性樹脂６を注入することにより、隙間５に絶縁性樹脂６を容易に充填することが可能となる。   Therefore, by providing the hole 7 in the printed circuit board 2 and injecting the insulating resin 6 into the gap 5 through the hole 7, the gap 5 can be easily filled with the insulating resin 6.

＜実施の形態２＞
図２に、本実施の形態における電子回路２００の断面図を示す。本実施の形態における電子回路２００は、実施の形態１における電子回路１００を、筐体４０内部に収納したものである。 <Embodiment 2>
FIG. 2 shows a cross-sectional view of the electronic circuit 200 in the present embodiment. The electronic circuit 200 according to the present embodiment is obtained by housing the electronic circuit 100 according to the first embodiment in the housing 40.

本実施の形態において、実施の形態１と同じく、ダイパッド１１Ａと、図２左側の外部電極端子１１との間に電位差があるものとする。   In the present embodiment, as in the first embodiment, it is assumed that there is a potential difference between the die pad 11A and the external electrode terminal 11 on the left side of FIG.

筐体４０内部および電子回路１００とプリント基板２の隙間５には絶縁性樹脂６が充填されている。本実施の形態における電子回路２００を製造する際、筐体４０に絶縁性樹脂６を注入する工程において、同時に、電子回路１００の隙間５にも穴７を通して絶縁性樹脂６が注入される。   An insulating resin 6 is filled in the housing 40 and the gap 5 between the electronic circuit 100 and the printed circuit board 2. When manufacturing the electronic circuit 200 in the present embodiment, in the process of injecting the insulating resin 6 into the housing 40, the insulating resin 6 is simultaneously injected into the gap 5 of the electronic circuit 100 through the hole 7.

本実施の形態における電子回路２００は、プリント基板２および電子部品１を収納する筐体４０をさらに備え、絶縁性樹脂６は、筐体４０に充填された絶縁性樹脂であることを特徴とする。   The electronic circuit 200 in the present embodiment further includes a housing 40 that houses the printed circuit board 2 and the electronic component 1, and the insulating resin 6 is an insulating resin filled in the housing 40. .

従って、筐体４０に絶縁性樹脂６を充填する際に、筐体４０に収納された電子回路１００の隙間５にも穴７を通して、同時に絶縁性樹脂６が充填される。よって、電子回路１００を筐体８に収納する場合、樹脂封止工程を簡素化することが可能である。   Therefore, when the housing 40 is filled with the insulating resin 6, the insulating resin 6 is simultaneously filled into the gap 5 of the electronic circuit 100 accommodated in the housing 40 through the hole 7. Therefore, when the electronic circuit 100 is housed in the housing 8, the resin sealing process can be simplified.

＜実施の形態３＞
図３に、本実施の形態における電子回路３００の断面図を示す。本実施の形態における電子回路３００は、実施の形態１の電子回路１００と、この電子回路１００と電気的に接続された半導体モジュールとを備える。半導体モジュールには、パワー半導体素子３０Ｉとして、例えばＳｉＣ半導体素子が備わっている。 <Embodiment 3>
FIG. 3 is a cross-sectional view of the electronic circuit 300 in this embodiment. The electronic circuit 300 in the present embodiment includes the electronic circuit 100 of the first embodiment and a semiconductor module that is electrically connected to the electronic circuit 100. The semiconductor module includes, for example, a SiC semiconductor element as the power semiconductor element 30I.

まず、半導体モジュールの構成について説明する。半導体モジュールの筐体は、ケース３０Ａとベース板３０Ｂから構成される。ケース３０Ａには、中継端子３０Ｃと電力端子３０Ｄが一体化され、あるいは埋め込まれている。   First, the configuration of the semiconductor module will be described. The housing of the semiconductor module includes a case 30A and a base plate 30B. In the case 30A, the relay terminal 30C and the power terminal 30D are integrated or embedded.

ベース板３０Ｂ上には、両面に配線パターン３０Ｇが形成された絶縁基板３０Ｊが、はんだ３０Ｆにより接合されている。絶縁基板３０Ｊ上には、はんだ３０Ｆを介して、ＳｉＣ半導体素子３０Ｉが接合されている。   On the base plate 30B, an insulating substrate 30J having wiring patterns 30G formed on both surfaces is joined by solder 30F. A SiC semiconductor element 30I is joined to the insulating substrate 30J via a solder 30F.

電子回路は、半導体モジュールの筐体に収納されている。電子回路１００のプリント基板２とパワー半導体素子３０Ｉは、中継端子３０Ｃおよびワイヤ３０Ｈを介して接続されている。電子回路１００のプリント基板２にはインターフェース端子３０Ｅが設けられる。   The electronic circuit is housed in the housing of the semiconductor module. The printed circuit board 2 of the electronic circuit 100 and the power semiconductor element 30I are connected via a relay terminal 30C and a wire 30H. The printed circuit board 2 of the electronic circuit 100 is provided with an interface terminal 30E.

また、パワー半導体素子３０Ｉと電力端子は、配線パターン３０Ｇを介して、ワイヤ３０Ｈにより接続されている。   The power semiconductor element 30I and the power terminal are connected by a wire 30H through the wiring pattern 30G.

また、半導体モジュールのケース３０Ａ内部は、例えばシリコンゲル４Ａにより充填されている。   Further, the inside of the case 30A of the semiconductor module is filled with, for example, silicon gel 4A.

なお、本実施の形態における電子回路３００は、電子回路１００が半導体モジュールのケース３０Ａに収納される構成としたが、電子回路１００が半導体モジュールと電気的に接続される構成であれば、この限りでは無い。   Note that the electronic circuit 300 in the present embodiment is configured such that the electronic circuit 100 is housed in the case 30A of the semiconductor module. However, as long as the electronic circuit 100 is configured to be electrically connected to the semiconductor module, this limitation is not applied. Not.

＜効果＞
本実施の形態における電子回路３００は、プリント基板２と電気的に接続された半導体モジュールをさらに備え、半導体モジュールは、パワー半導体素子３０Ｉを含むことを特徴とする。 <Effect>
The electronic circuit 300 according to the present embodiment further includes a semiconductor module electrically connected to the printed circuit board 2, and the semiconductor module includes a power semiconductor element 30I.

従って、半導体モジュールに備わるパワー半導体素子３０Ｉの電位差が、電子回路１００に備わる電子部品１のダイパッド１１Ａと、例えば図３左側の外部電極端子１１との間に生じる場合であっても、隙間５に絶縁性樹脂６が充填されているため、隙間５に絶縁性樹脂６が充填されていない場合よりも、絶縁距離Ｌを小さくすることができる。よって、電子部品１の小型化が可能であり、電子部品１を備える電子回路１００の小型化が可能となる。つまり、電子回路１００を備える電子回路３００の小型化が可能である。また、電子回路１００が半導体モジュールのケースに収納される場合、半導体モジュール自体の小型化が可能である。   Therefore, even if the potential difference of the power semiconductor element 30I included in the semiconductor module occurs between the die pad 11A of the electronic component 1 included in the electronic circuit 100 and the external electrode terminal 11 on the left side of FIG. Since the insulating resin 6 is filled, the insulating distance L can be made smaller than when the gap 5 is not filled with the insulating resin 6. Therefore, the electronic component 1 can be downsized, and the electronic circuit 100 including the electronic component 1 can be downsized. That is, the electronic circuit 300 including the electronic circuit 100 can be downsized. In addition, when the electronic circuit 100 is housed in a semiconductor module case, the semiconductor module itself can be downsized.

また、本実施の形態における電子回路３００において、パワー半導体素子３０Ｉは、ＳｉＣ半導体素子を含むことを特徴とする。   In the electronic circuit 300 according to the present embodiment, the power semiconductor element 30I includes a SiC semiconductor element.

従って、一般に、ＳｉＣ半導体素子は高電圧が印加されて使用されることが多いため、電子部品１の絶縁距離Ｌをより小さくすることが可能であり、電子回路１００および電子回路３００をより小型化することが可能となる。   Therefore, generally, since a SiC semiconductor element is often used with a high voltage applied, the insulation distance L of the electronic component 1 can be further reduced, and the electronic circuit 100 and the electronic circuit 300 can be further downsized. It becomes possible to do.

＜実施の形態４＞
図４（ａ）に、本実施の形態における電子部品４００の断面図を示す。また、図４（ｂ）に、本実施の形態における電子部品４００を実装したプリント基板２の断面図を示す。 <Embodiment 4>
FIG. 4A shows a cross-sectional view of electronic component 400 in the present embodiment. FIG. 4B shows a cross-sectional view of the printed circuit board 2 on which the electronic component 400 according to the present embodiment is mounted.

本実施の形態における電子部品４００は、例えばＱＦＮまたはＳＯＮなどのフラットパッケージであり、電子部品４００のパッケージ表面には外部電極端子１１が備わっている。   The electronic component 400 in the present embodiment is a flat package such as QFN or SON, for example, and the external electrode terminal 11 is provided on the package surface of the electronic component 400.

図４（ａ）において、左右の外部電極端子１１間に電位差がある場合を考える。左右の外部電極端子１１の間には、電子部品４００のパッケージの表面に沿って、熱硬化性樹脂４Ｂが塗布されている。なお、外部電極端子１１表面にも、はんだ３と接合する一部を残して、熱硬化性樹脂４Ｂが塗布される。   In FIG. 4A, a case where there is a potential difference between the left and right external electrode terminals 11 is considered. A thermosetting resin 4B is applied between the left and right external electrode terminals 11 along the surface of the package of the electronic component 400. The thermosetting resin 4B is also applied to the surface of the external electrode terminal 11 leaving a part to be joined to the solder 3.

以上の構成を有する電子部品４００を、プリント基板２上に実装する。プリント基板２上には、プリント基板側ランド２１が設けられており、外部電極端子１１とプリント基板側ランド２１は、はんだ３によりはんだ接合される。はんだ接合の際の熱処理により、熱硬化性樹脂４Ｂが硬化して、電子部品４００とプリント基板２の隙間が、熱硬化性樹脂４Ｂにより充填される。   The electronic component 400 having the above configuration is mounted on the printed circuit board 2. A printed circuit board side land 21 is provided on the printed circuit board 2, and the external electrode terminal 11 and the printed circuit board side land 21 are soldered together by solder 3. The heat-curable resin 4B is cured by the heat treatment at the time of soldering, and the gap between the electronic component 400 and the printed board 2 is filled with the thermosetting resin 4B.

このように、左右の外部電極端子１１間が熱硬化性樹脂４Ｂにより充填されるため、左右の外部電極端子１１間の絶縁性が向上する。つまり、外部電極端子１１間の絶縁距離Ｌを小さくすることが可能であり、電子部品４００の小型化が可能である。   Thus, since the space between the left and right external electrode terminals 11 is filled with the thermosetting resin 4B, the insulation between the left and right external electrode terminals 11 is improved. That is, the insulation distance L between the external electrode terminals 11 can be reduced, and the electronic component 400 can be downsized.

なお、本実施の形態において、実施の形態１の様に、電子部品１が外部に露呈したダイパッドを備えてもよい。外部電極端子１１とダイパッドとの間に電位差がある場合は、外部電極端子１１とダイパッドとの間に、電子部品１のパッケージの表面に沿って熱硬化性樹脂４Ｂを塗布することにより、上述した効果と同様の効果を得ることが可能である。   In the present embodiment, as in the first embodiment, the electronic component 1 may be provided with a die pad exposed to the outside. When there is a potential difference between the external electrode terminal 11 and the die pad, the thermosetting resin 4B is applied along the surface of the package of the electronic component 1 between the external electrode terminal 11 and the die pad as described above. It is possible to obtain an effect similar to the effect.

＜効果＞
本実施の形態における電子部品４００は、電位の異なる複数の外部電極端子１１をパッケージ表面に備え、外部電極端子１１間には、熱硬化性樹脂４Ｂがパッケージの表面に沿って設けられていることを特徴とする。 <Effect>
Electronic component 400 in the present embodiment includes a plurality of external electrode terminals 11 having different potentials on the package surface, and thermosetting resin 4B is provided between the external electrode terminals 11 along the surface of the package. It is characterized by.

従って、電子部品４００の電位の異なる外部電極端子１１間に、パッケージ表面に沿って熱硬化性樹脂４Ｂが塗布されているため、電子部品４００をプリント基板２に実装すると、電子部品４００とプリント基板２の隙間において、外部電極端子１１間が熱硬化性樹脂４Ｂにより充填される。よって、電位の異なる外部電極端子１１間の絶縁性が向上するため、電位の異なる外部電極端子１１間の絶縁距離Ｌを小さくすることが可能であり、電子部品４００を小型化することができる。また、電子部品４００の小型化により、電子部品４００を実装したプリント基板２の小型化も可能である。   Accordingly, since the thermosetting resin 4B is applied along the package surface between the external electrode terminals 11 having different electric potentials of the electronic component 400, when the electronic component 400 is mounted on the printed circuit board 2, the electronic component 400 and the printed circuit board are mounted. In the gap of 2, the space between the external electrode terminals 11 is filled with the thermosetting resin 4B. Therefore, since the insulation between the external electrode terminals 11 having different potentials is improved, the insulation distance L between the external electrode terminals 11 having different potentials can be reduced, and the electronic component 400 can be downsized. In addition, due to the miniaturization of the electronic component 400, the printed circuit board 2 on which the electronic component 400 is mounted can be miniaturized.

＜実施の形態５＞
図５に、本実施の形態における電子回路５００の側面図を示す。電子回路５００は、外部電極端子１１をパッケージ上面に備える電子部品１０と、電子部品１０のパッケージ下面と接着されたプリント基板２と、外部電極端子１１とプリント基板２を電気的に接合するワイヤ８とを備える。プリント基板２表面には、ワイヤパッド２２が形成されている。 <Embodiment 5>
FIG. 5 shows a side view of electronic circuit 500 in the present embodiment. The electronic circuit 500 includes an electronic component 10 having the external electrode terminal 11 on the upper surface of the package, a printed circuit board 2 bonded to the lower surface of the electronic component 10, and a wire 8 that electrically connects the external electrode terminal 11 and the printed circuit board 2. With. Wire pads 22 are formed on the surface of the printed circuit board 2.

また、図５における電子部品１０において、左右の外部電極端子１１間の電位が異なるとする。   Further, in the electronic component 10 in FIG. 5, it is assumed that the potential between the left and right external electrode terminals 11 is different.

電子回路５００の製造方法について説明する。まず、電子部品１０の外部電極端子１１が形成されていない側の面、即ちパッケージ下面を、プリント基板２に接着部９を介して接着する。接着には、電子部品１０の動作時の発熱に耐えることが可能な接着剤を用いる。   A method for manufacturing the electronic circuit 500 will be described. First, the surface of the electronic component 10 on which the external electrode terminal 11 is not formed, that is, the lower surface of the package is bonded to the printed circuit board 2 via the bonding portion 9. For the bonding, an adhesive capable of withstanding heat generated during operation of the electronic component 10 is used.

次に、ワイヤ８の一端を外部電極端子１１とはんだ接合し、ワイヤ８の他端をワイヤパッド２２とはんだ接合することにより、電子部品１０の外部電極端子１１とプリント基板２とを電気的に接合する。ワイヤ８は例えば銅線である。   Next, one end of the wire 8 is soldered to the external electrode terminal 11, and the other end of the wire 8 is soldered to the wire pad 22 to electrically connect the external electrode terminal 11 of the electronic component 10 and the printed board 2. Join. The wire 8 is a copper wire, for example.

なお、ワイヤ８をワイヤボンディングにより接合することも可能である。この場合、ワイヤ８は例えばアルミワイヤであり、超音波により接合される。   It is also possible to join the wire 8 by wire bonding. In this case, the wire 8 is an aluminum wire, for example, and is joined by ultrasonic waves.

次に、図５に示す様に、電子回路５００の表側を絶縁性樹脂４により封止する。つまり、電子部品１０、ワイヤ８、電子部品１０とプリント基板２の接着部９およびワイヤ８とプリント基板２との接合部（即ちワイヤパッド２２）が絶縁性樹脂４により封止される。以上の製造工程を経て、本実施の形態における電子回路５００が製造される。   Next, as shown in FIG. 5, the front side of the electronic circuit 500 is sealed with an insulating resin 4. That is, the electronic component 10, the wire 8, the bonding portion 9 between the electronic component 10 and the printed board 2, and the joint portion (that is, the wire pad 22) between the wire 8 and the printed board 2 are sealed with the insulating resin 4. Through the above manufacturing process, electronic circuit 500 in the present embodiment is manufactured.

本実施の形態における電子回路５００において、電圧の異なる外部電極端子１１間が絶縁性樹脂４により封止されるため、外部電極端子１１間の絶縁性が向上する。このため、外部電極端子１１間の絶縁距離Ｌを小さくすることが可能である。   In the electronic circuit 500 according to the present embodiment, since the space between the external electrode terminals 11 having different voltages is sealed with the insulating resin 4, the insulation between the external electrode terminals 11 is improved. For this reason, the insulation distance L between the external electrode terminals 11 can be reduced.

＜効果＞
本実施の形態に係る電子回路５００は、電位の異なる複数の外部電極端子１１をパッケージ上面に備える電子部品１０と、電子部品１０のパッケージ下面と接着されたプリント基板２と、外部電極端子１１の各々とプリント基板２を電気的に接合するワイヤ８とを備え、電子部品１０、ワイヤ８、電子部品１０とプリント基板２の接着部９およびワイヤ８とプリント基板２との接合部（即ちワイヤパッド２２）は絶縁性樹脂４で封止されることを特徴とする。 <Effect>
The electronic circuit 500 according to the present embodiment includes an electronic component 10 having a plurality of external electrode terminals 11 having different potentials on the upper surface of the package, a printed circuit board 2 bonded to the lower surface of the electronic component 10, and the external electrode terminals 11. And an electronic component 10, a wire 8, a bonding portion 9 between the electronic component 10 and the printed circuit board 2, and a bonded portion between the wire 8 and the printed circuit board 2 (that is, a wire pad). 22) is characterized by being sealed with an insulating resin 4.

従って、電子部品１０のパッケージ上面に外部電極端子１１を設けたことにより、電子部品１０を絶縁性樹脂４で封止すると、パッケージ上面に備わる外部電極端子１１も樹脂封止される。よって、外部電極端子１１間の絶縁性が向上する。つまり、外部電極端子１１間の隙間が絶縁性樹脂により充填されない前提技術（図６（ａ））と比較して、絶縁距離Ｌを小さくすることが可能である。このため、電子部品１０の小型化が可能であり、電子部品１０が実装される電子回路５００を小型化することが可能である。また、外部電極端子１１が電子部品１０のパッケージ上面に設けられるため、接合部分の外観を検査することが可能であり、製造工程において歩留まりが向上する。   Therefore, by providing the external electrode terminals 11 on the upper surface of the package of the electronic component 10, when the electronic component 10 is sealed with the insulating resin 4, the external electrode terminals 11 provided on the upper surface of the package are also resin-sealed. Therefore, the insulation between the external electrode terminals 11 is improved. That is, it is possible to reduce the insulation distance L as compared with the base technology (FIG. 6A) in which the gap between the external electrode terminals 11 is not filled with the insulating resin. For this reason, the electronic component 10 can be reduced in size, and the electronic circuit 500 on which the electronic component 10 is mounted can be reduced in size. In addition, since the external electrode terminal 11 is provided on the upper surface of the package of the electronic component 10, the appearance of the joint portion can be inspected, and the yield is improved in the manufacturing process.

また、本実施の形態における電子回路５００において、ワイヤ８は、銅であり、はんだにより接合されることを特徴とする。従って、はんだにより接合を行うことによって、接合の強度を高めることが可能である。   In the electronic circuit 500 according to the present embodiment, the wire 8 is copper and is joined by solder. Therefore, the bonding strength can be increased by bonding with solder.

また、本実施の形態における電子回路５００において、ワイヤ８は、アルミであり、超音波により接合されることを特徴とする。従って、電子部品１０が小型で、外部電極端子１１の接合面が小さい場合でも、ワイヤボンディングによりワイヤ８の接合を行うことが可能である。   Further, in the electronic circuit 500 in the present embodiment, the wire 8 is aluminum and is bonded by ultrasonic waves. Therefore, even when the electronic component 10 is small and the joint surface of the external electrode terminal 11 is small, the wire 8 can be joined by wire bonding.

なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。   It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

１，１０，４００ 電子部品、２ プリント基板、３，３０Ｆ はんだ、４，６ 絶縁性樹脂、４Ａ シリコンゲル、４Ｂ 熱硬化性樹脂、５ 隙間、７ 穴、８，３０Ｈ ワイヤ、９ 接着部、１１ 外部電極端子、１１Ａ ダイパッド、２１ プリント基板側ランド、２２ ワイヤパッド、３０Ａ ケース、３０Ｂ ベース板、３０Ｃ 中継端子、３０Ｄ 電力端子、３０Ｅ インターフェース端子、３０Ｇ 配線パターン、３０Ｉ パワー半導体素子、３０Ｊ 絶縁基板、４０ 筐体、１００，２００，３００，５００ 電子回路。   1,10,400 Electronic components, 2 Printed circuit board, 3,30F Solder, 4,6 Insulating resin, 4A Silicon gel, 4B Thermosetting resin, 5 Crevice, 7 holes, 8, 30H wire, 9 Adhesion, 11 External electrode terminal, 11A die pad, 21 printed circuit board side land, 22 wire pad, 30A case, 30B base plate, 30C relay terminal, 30D power terminal, 30E interface terminal, 30G wiring pattern, 30I power semiconductor element, 30J insulating substrate, 40 Case, 100, 200, 300, 500 Electronic circuit.

Claims (4)

電位の異なる複数の外部電極端子をパッケージ表面に備え、
前記外部電極端子間には、熱硬化性樹脂がパッケージの表面に沿って設けられていることを特徴とする、
電子部品。 A plurality of external electrode terminals with different potentials are provided on the package surface,
Between the external electrode terminals, a thermosetting resin is provided along the surface of the package,
Electronic components. 電位の異なる複数の外部電極端子をパッケージ上面に備える電子部品と、
前記電子部品のパッケージ下面と接着されたプリント基板と、
前記外部電極端子の各々と前記プリント基板を電気的に接合するワイヤと、
を備え、
前記電子部品、前記ワイヤ、前記電子部品と前記プリント基板との接着部および前記ワイヤと前記プリント基板との接合部は絶縁性樹脂で封止されることを特徴とする、
電子回路。 An electronic component having a plurality of external electrode terminals with different potentials on the upper surface of the package;
A printed circuit board bonded to the package lower surface of the electronic component;
A wire for electrically joining each of the external electrode terminals and the printed circuit board;
With
The electronic component, the wire, the bonding portion between the electronic component and the printed board, and the bonding portion between the wire and the printed board are sealed with an insulating resin.
Electronic circuit. 前記ワイヤは、銅であり、はんだにより接合されることを特徴とする、
請求項２に記載の電子回路。 The wire is copper and is joined by solder,
The electronic circuit according to claim 2. 前記ワイヤは、アルミであり、超音波により接合されることを特徴とする、
請求項２に記載の電子回路。 The wire is aluminum and is bonded by ultrasonic waves,
The electronic circuit according to claim 2.
JP2015180586A 2015-09-14 2015-09-14 Electronic circuit and electronic component Pending JP2016029724A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000244077A (en) * 1999-02-24 2000-09-08 Matsushita Electric Ind Co Ltd Resin-molded substrate and resin-molded substrate with built-in electronic part
JP2000294715A (en) * 1999-04-09 2000-10-20 Hitachi Ltd Semiconductor device and manufacture thereof
JP2003078076A (en) * 2001-09-05 2003-03-14 Hitachi Cable Ltd Semiconductor device and manufacturing method therefor
JP2010245434A (en) * 2009-04-09 2010-10-28 Panasonic Corp Solder bonding method and solder bonding structure
JP2012146995A (en) * 2012-03-06 2012-08-02 Toshiba Corp Method of manufacturing electronic apparatus, electronic component, and electronic apparatus
JP2012169440A (en) * 2011-02-14 2012-09-06 Fujitsu Semiconductor Ltd Semiconductor device and manufacturing method of the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000244077A (en) * 1999-02-24 2000-09-08 Matsushita Electric Ind Co Ltd Resin-molded substrate and resin-molded substrate with built-in electronic part
JP2000294715A (en) * 1999-04-09 2000-10-20 Hitachi Ltd Semiconductor device and manufacture thereof
JP2003078076A (en) * 2001-09-05 2003-03-14 Hitachi Cable Ltd Semiconductor device and manufacturing method therefor
JP2010245434A (en) * 2009-04-09 2010-10-28 Panasonic Corp Solder bonding method and solder bonding structure
JP2012169440A (en) * 2011-02-14 2012-09-06 Fujitsu Semiconductor Ltd Semiconductor device and manufacturing method of the same
JP2012146995A (en) * 2012-03-06 2012-08-02 Toshiba Corp Method of manufacturing electronic apparatus, electronic component, and electronic apparatus

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