JPH0982741A - Chip carrier structure and its manufacture - Google Patents

Chip carrier structure and its manufacture

Info

Publication number
JPH0982741A
JPH0982741A JP7240366A JP24036695A JPH0982741A JP H0982741 A JPH0982741 A JP H0982741A JP 7240366 A JP7240366 A JP 7240366A JP 24036695 A JP24036695 A JP 24036695A JP H0982741 A JPH0982741 A JP H0982741A
Authority
JP
Japan
Prior art keywords
lead frame
resin
semiconductor element
chip carrier
resin tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7240366A
Other languages
Japanese (ja)
Other versions
JP3304705B2 (en
Inventor
Yasuo Yamazaki
康男 山▲崎▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP24036695A priority Critical patent/JP3304705B2/en
Publication of JPH0982741A publication Critical patent/JPH0982741A/en
Application granted granted Critical
Publication of JP3304705B2 publication Critical patent/JP3304705B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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Abstract

PROBLEM TO BE SOLVED: To provide a chip carrier structure and its manufacturing method which supply a large quantity of small thin low-cost chip carriers. SOLUTION: On a lead frame 1, a plurality of areas 1a for mounting a semiconductor element 2 and areas 1b to be connected with the semiconductor element 2 by using a metal fine wire 4 are formed by photo-etching. On the rear plane of the lead frame 1, a resin tape 5 which has adhesive 5 is laminated by applying pressure. Then, the semiconductor element 2 is permitted to adhere on the area 1a on the lead frame 1 by using paste 3, and the semiconductor element 2 and the lead frame 1 are connected by wire bonding. Resin 6 is applied on the lead frame 1 by a potting-mold method and is hardened. Thus, the semiconductor element 2 and the metal fine wire 4 are covered and resin- sealed. Then, the resin tape 5 is removed and cut by a chip carrier.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体素子を搭載し、
樹脂封止して形成されるチップキャリアの構造およびそ
の製造方法に関わる。BACKGROUND OF THE INVENTION The present invention is equipped with a semiconductor element,
The present invention relates to a structure of a chip carrier formed by resin sealing and a manufacturing method thereof.

【０００２】[0002]

【従来の技術】この種のチップキャリアの一例として、
図８に示す構造がある。この技術は、図８に示すように
リードフレーム１０１上に半導体素子１０２をペースト
１０３を用いて設置し、金属細線１０４を用いて半導体
素子１０２とリードフレーム１０１を接続し、トランス
ファーモールドと呼ばれる技術を使い樹脂１０６で封止
し、リードフレーム１０１の樹脂１０６より突出した部
分を折り曲げる事によりチップキャリアを製造する。ト
ランスファーモールド技術とは、図９に示すように金型
１０７内に半導体素子１０２を搭載したリードフレーム
１０１を設置し、樹脂１０６を図中矢印で示した方向か
ら注入し、硬化させることにより、樹脂１０６で封止し
チップキャリアを製造する方法である。2. Description of the Related Art As an example of this type of chip carrier,
There is a structure shown in FIG. In this technique, as shown in FIG. 8, a semiconductor element 102 is placed on a lead frame 101 using a paste 103, and the semiconductor element 102 and the lead frame 101 are connected by using a metal thin wire 104. The chip carrier is manufactured by sealing with the resin 106 used and bending the part of the lead frame 101 protruding from the resin 106. As shown in FIG. 9, the transfer molding technique is to install a lead frame 101 on which a semiconductor element 102 is mounted in a mold 107, inject a resin 106 from a direction indicated by an arrow in the figure, and cure the resin to obtain a resin. This is a method of manufacturing a chip carrier by sealing with 106.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、このよ
うなチップキャリアは、以下のような課題を有する。However, such a chip carrier has the following problems.

【０００４】すなわち、トランスファーモールド技術を
用いるため、モールド用の金型やリードフレーム１０１
を折り曲げるための設備が必要であり、非常に大きな設
備投資が必要になる。また、リードフレーム１０１をチ
ップキャリア毎に折り曲げる為、工数が多くかかり、チ
ップキャリアが高価となる。また、リードフレーム１０
１が樹脂１０６より突出している事により、チップキャ
リアが厚く外形形状も大きくなる為、実装した場合に大
きな占有面積が必要となり、小型化、薄型化が困難であ
る。That is, since the transfer molding technique is used, a molding die or lead frame 101 is used.
Equipment for bending is required, and a very large capital investment is required. Moreover, since the lead frame 101 is bent for each chip carrier, a lot of man-hours are required and the chip carrier becomes expensive. In addition, the lead frame 10
Since 1 projects from the resin 106, the chip carrier becomes thick and the outer shape becomes large, so that a large occupied area is required when it is mounted, and it is difficult to reduce the size and thickness.

【０００５】本発明は、このような従来技術の課題を解
決するものであり、その目的とすることは、小型で薄型
のチップキャリアを簡便な設備により提供するところに
ある。The present invention solves the problems of the prior art as described above, and an object thereof is to provide a small and thin chip carrier with simple equipment.

【０００６】[0006]

【課題を解決するための手段】本発明のチップキャリア
は、半導体素子を搭載し、樹脂封止したチップキャリア
において、リードフレームの一平面上に前記半導体素子
を搭載し、前記半導体素子上の電極と前記電極と対応し
た前記リードフレームとを金属細線を用いて接続し、前
記半導体素子と前記金属細線と前記リードフレームの前
記半導体素子を搭載した平面を樹脂により封止した事を
特徴とする。A chip carrier of the present invention has a semiconductor element mounted thereon and is resin-sealed. In the chip carrier, the semiconductor element is mounted on one plane of a lead frame, and electrodes on the semiconductor element are mounted. And a lead frame corresponding to the electrode are connected by a metal thin wire, and a plane on which the semiconductor element, the metal thin wire and the semiconductor element of the lead frame are mounted is sealed with resin.

【０００７】また、本発明のチップキャリアの製造方法
は、複数の半導体素子搭載面を持つリードフレームの一
平面に樹脂テープをラミネートする工程と、前記リード
フレームの樹脂テープをラミネートした対面に半導体素
子を搭載する工程と、前記半導体素子上の電極と前記リ
ードフレームとを金属細線を用いて接続する工程と、前
記半導体素子と、前記金属細線と、前記リードフレーム
の前記半導体素子を搭載した面とを覆うように樹脂を滴
下し、樹脂を硬化させる工程と、前記樹脂テープを剥離
除去する工程と、前記樹脂で封止したリードフレームを
前記半導体素子毎に切断する工程とからなる事を特徴と
する。The method of manufacturing a chip carrier according to the present invention comprises a step of laminating a resin tape on one surface of a lead frame having a plurality of semiconductor element mounting surfaces, and a semiconductor element on the opposite surface of the lead frame on which the resin tape is laminated. And a step of connecting the electrodes on the semiconductor element and the lead frame with a metal thin wire, the semiconductor element, the metal thin wire, and a surface of the lead frame on which the semiconductor element is mounted. A step of dropping resin so as to cover the resin and curing the resin, a step of peeling and removing the resin tape, and a step of cutting the resin-sealed lead frame for each of the semiconductor elements. To do.

【０００８】また、本発明のチップキャリアの製造方法
は、複数の半導体素子搭載面を持つリードフレームの一
平面に樹脂テープをラミネートする工程と、前記リード
フレームの樹脂テープをラミネートした対面に半導体素
子を搭載する工程と、前記半導体素子上の電極と前記リ
ードフレームとを金属細線を用いて接続する工程と、前
記半導体素子と、前記金属細線と、前記リードフレーム
の前記半導体素子を搭載した面とを覆うように樹脂を滴
下し、樹脂を硬化させる工程と、前記樹脂テープを剥離
除去する工程と、前記リードフレームと前記樹脂の一部
を前記半導体素子毎に切断する工程と、前記リードフレ
ームの前記樹脂より露出している部位に金属メッキを施
す工程と、前記リードフレームに探針を接触させ電気的
動作を確認する工程と、前記樹脂を前記半導体素子毎に
切断する工程を含む事を特徴とする。The chip carrier manufacturing method of the present invention comprises a step of laminating a resin tape on one surface of a lead frame having a plurality of semiconductor element mounting surfaces, and a step of laminating the resin tape of the lead frame on the opposite surface of the semiconductor element. And a step of connecting the electrodes on the semiconductor element and the lead frame with a metal thin wire, the semiconductor element, the metal thin wire, and a surface of the lead frame on which the semiconductor element is mounted. A step of dropping a resin so as to cover the resin, a step of curing the resin, a step of peeling and removing the resin tape, a step of cutting the lead frame and a part of the resin for each of the semiconductor elements, and a step of cutting the lead frame. A step of metal plating the portion exposed from the resin and a step of contacting a probe with the lead frame to confirm the electrical operation. When, characterized in that comprising the step of cutting the resin for each of the semiconductor elements.

【０００９】また、本発明のチップキャリアの製造方法
は、複数の半導体素子搭載面を持つリードフレームの一
平面にエッチング法により突起を形成する工程と、前記
突起形成面に前記樹脂テープをラミネートする工程と、
前記リードフレームの樹脂テープをラミネートした対面
に半導体素子を搭載する工程と、前記半導体素子上の電
極と前記リードフレームとを金属細線を用いて接続する
工程と、前記半導体素子と、前記金属細線と、前記リー
ドフレームの前記半導体素子を搭載した面とを覆うよう
に樹脂を滴下し、樹脂を硬化させる工程と、前記樹脂テ
ープを剥離除去する工程と、前記樹脂より露出した前記
リードフレームの突起部に半田バンプを形成する工程
と、前記樹脂で封止した前記リードフレームを前記半導
体素子毎に切断する工程とからなる事を特徴とする。Further, in the method of manufacturing a chip carrier of the present invention, a step of forming protrusions on one plane of a lead frame having a plurality of semiconductor element mounting surfaces by an etching method, and laminating the resin tape on the protrusion forming surface. Process,
A step of mounting a semiconductor element on the opposite surface of the lead frame laminated with a resin tape; a step of connecting an electrode on the semiconductor element and the lead frame using a fine metal wire; the semiconductor element; and the fine metal wire. A step of dropping resin so as to cover the surface of the lead frame on which the semiconductor element is mounted and curing the resin, a step of peeling and removing the resin tape, and a protruding portion of the lead frame exposed from the resin And a step of cutting the lead frame sealed with the resin for each of the semiconductor elements.

【００１０】また、本発明のチップキャリアの製造方法
は、複数の半導体素子搭載面と複数の突起部を持つ射出
成形樹脂に金属メッキを施すことによりリードフレーム
を形成する工程と、前記突起形成面に樹脂テープをラミ
ネートする工程と、前記リードフレームの前記樹脂テー
プをラミネートした対面に半導体素子を搭載する工程
と、前記半導体素子上の電極と前記リードフレームとを
金属細線を用いて接続する工程と、前記半導体素子と、
前記金属細線と、前記リードフレームの前記半導体素子
を搭載した面とを覆うように樹脂を滴下し、樹脂を硬化
させる工程と、前記樹脂テープを剥離除去する工程と、
前記樹脂より露出した前記リードフレームの突起部に半
田バンプを形成する工程と、前記樹脂で封止した前記リ
ードフレームを前記半導体素子毎に切断する工程とから
なる事を特徴とする。Further, the method of manufacturing a chip carrier of the present invention comprises a step of forming a lead frame by metal plating an injection molding resin having a plurality of semiconductor element mounting surfaces and a plurality of protrusions, and the protrusion forming surface. A step of laminating a resin tape on the lead frame, a step of mounting a semiconductor element on the opposite side of the lead frame on which the resin tape is laminated, and a step of connecting the electrode on the semiconductor element and the lead frame using a fine metal wire. , The semiconductor element,
A step of dropping a resin so as to cover the thin metal wire and a surface of the lead frame on which the semiconductor element is mounted, and curing the resin; and a step of peeling and removing the resin tape,
It is characterized by comprising a step of forming a solder bump on a protrusion of the lead frame exposed from the resin and a step of cutting the resin-sealed lead frame into each of the semiconductor elements.

【００１１】[0011]

【実施例】【Example】

（実施例１）図１は本発明のチップキャリア１０００の
構造の一例である要部を拡大して示した断面図であり、
１はリードフレーム、２は半導体素子、３はペースト、
４は金属細線である。以下図１に示すチップキャリアの
製造方法を説明する。(Embodiment 1) FIG. 1 is an enlarged sectional view showing an essential part of a structure of a chip carrier 1000 of the present invention.
1 is a lead frame, 2 is a semiconductor element, 3 is a paste,
Reference numeral 4 is a thin metal wire. Hereinafter, a method for manufacturing the chip carrier shown in FIG. 1 will be described.

【００１２】図２は本発明による複数のチップキャリア
１０００を製造する過程を説明するためにリードフレー
ム１を模式化して示した斜視図である。１ａは半導体素
子２を搭載する領域、１ｂは金属細線４を接続する領域
である。リードフレーム１上には半導体素子２を搭載す
る領域１ａと金属細線４を接続する領域１ｂがフォトエ
ッチングにより形成されている。本発明によれば、一枚
のリードフレーム１により、多数のチップキャリアを形
成できるため、リードフレーム１上には、半導体素子２
を搭載する領域１ａと金属細線４を接続する領域１ｂを
複数回繰り返し形成している。FIG. 2 is a perspective view schematically showing the lead frame 1 for explaining a process of manufacturing a plurality of chip carriers 1000 according to the present invention. Reference numeral 1a is a region where the semiconductor element 2 is mounted, and 1b is a region where the metal thin wire 4 is connected. A region 1a for mounting the semiconductor element 2 and a region 1b for connecting the thin metal wires 4 are formed on the lead frame 1 by photoetching. According to the present invention, since a large number of chip carriers can be formed by one lead frame 1, the semiconductor element 2 is formed on the lead frame 1.
The region 1a for mounting the and the region 1b for connecting the thin metal wires 4 are repeatedly formed a plurality of times.

【００１３】図３（ａ）〜図３（ｄ）は本発明によるチ
ップキャリアの製造方法の一例を模式的に示した断面図
である。図３（ａ）に示すようにリードフレーム１に
は、図２と同様に半導体素子２を搭載する為の領域１ａ
と金属細線４を用いて接続する領域１ｂがフォトエッチ
ングにより多数形成されている。本実施例では、リード
フレーム１として、厚さが約０．３ｍｍであり材質がＣ
ｕによる金属板を用いている。従来例では、図８に示す
ようにリードフレーム１０１を折り曲げて使用するた
め、リードフレーム１０１に機械的強度が必要で有り、
Ｆｅ−Ｎｉ合金や燐青銅と呼ばれるＣｕとＳｎの合金を
用いている。しかし、本発明によれば、機械的強度はほ
とんど不要となるため、純銅、アルミニウム等機械的強
度の低い金属材料を用いることが出来る。3 (a) to 3 (d) are sectional views schematically showing an example of a method for manufacturing a chip carrier according to the present invention. As shown in FIG. 3A, the lead frame 1 has a region 1a for mounting the semiconductor element 2 similarly to FIG.
A large number of regions 1b that are connected to each other by using the metal thin wires 4 are formed by photoetching. In this embodiment, the lead frame 1 has a thickness of about 0.3 mm and a material of C
A metal plate made of u is used. In the conventional example, since the lead frame 101 is bent and used as shown in FIG. 8, the lead frame 101 needs to have mechanical strength.
An alloy of Cu and Sn called Fe-Ni alloy or phosphor bronze is used. However, according to the present invention, since mechanical strength is almost unnecessary, a metal material having low mechanical strength such as pure copper or aluminum can be used.

【００１４】このリードフレーム１に図３（ｂ）で示す
ように、粘着剤５ａを持つ樹脂テープ５を、リードフレ
ーム１の一方の面の全面に加圧しラミネートする。本実
施例では、樹脂テープ５として、粘着剤５ａを持つ樹脂
テープを用いているが、光硬化や熱硬化性または熱可塑
性の樹脂を用いても良い。本発明では、最も簡便な方法
でラミネートおよび剥離の可能な粘着剤を持つ樹脂テー
プを用いた。As shown in FIG. 3B, a resin tape 5 having an adhesive 5a is applied to the entire surface of one surface of the lead frame 1 by pressure and laminated on the lead frame 1. In this embodiment, the resin tape having the adhesive 5a is used as the resin tape 5, but a photocurable, thermosetting or thermoplastic resin may be used. In the present invention, a resin tape having an adhesive that can be laminated and peeled by the simplest method is used.

【００１５】次に図３（ｃ）に示すように半導体素子２
をペースト３を用いてリードフレーム１上の領域１ａに
接着固定する。ペースト３は半導体素子２を電気的及び
熱的に外部と導通させるためＡｇとＰｄの金属粉末を接
着剤に混入した物を用いている。ペースト３を硬化させ
た後、金属細線４をワイヤーボンディングと呼ばれる接
続技術を用いて、半導体素子２とリードフレーム１との
接続を行なう。金属細線４として、本実施例では直径が
約３０μｍのＡｕの細線を用いている。その他にはアル
ミニウム細線やＣｕ細線を用いて接続することも可能で
ある。Next, as shown in FIG. 3C, the semiconductor element 2
Is bonded and fixed to the region 1a on the lead frame 1 using the paste 3. The paste 3 is a mixture of a metal powder of Ag and Pd in an adhesive in order to electrically and thermally connect the semiconductor element 2 to the outside. After the paste 3 is cured, the thin metal wire 4 is connected to the semiconductor element 2 and the lead frame 1 by using a connection technique called wire bonding. As the metal thin wires 4, Au thin wires having a diameter of about 30 μm are used in this embodiment. Besides, it is also possible to use aluminum thin wires or Cu thin wires for connection.

【００１６】次に図３（ｄ）に示すようにリードフレー
ム１上にポッティングモールド技術により樹脂６を流し
込み、硬化させる事により半導体素子２や金属細線４を
覆い、樹脂封止させる。本発明では、樹脂６はポッティ
ングモールド技術と呼ばれる技術により形成するため、
トランスファモールド技術の様な高価な設備を必要とし
ない。また、樹脂６として液状樹脂を用いる事が出来る
ため、トランスファモールド技術を用いる従来例に比べ
比較的低温で、さらに短時間で硬化させる事が出来る。
本発明では、樹脂６としてエポキシ系の液状樹脂を用
い、８０℃の温度で約１時間で硬化を完了している。従
来例で用いられているトランスファモールド技術では、
１８０℃で約５時間のキュアが必要である。このため、
半導体素子１０１の高温による合金の劣化が大きく、ま
た樹脂１０６より突出しているリードフレーム１０１の
熱による酸化が激しいため、酸化した金属膜を除去する
等の工程が更に付加されることになる。本発明では常温
から１００℃以下の低温で硬化する樹脂を用いることが
出来るため、高温による劣化や酸化等の問題を生じる事
なくチップキャリアを製造することが出来る。Next, as shown in FIG. 3D, a resin 6 is poured onto the lead frame 1 by a potting molding technique, and is cured to cover the semiconductor element 2 and the thin metal wires 4 and seal them with a resin. In the present invention, since the resin 6 is formed by a technique called potting mold technique,
It does not require expensive equipment such as transfer mold technology. Further, since a liquid resin can be used as the resin 6, it can be cured at a relatively low temperature and in a shorter time as compared with the conventional example using the transfer molding technique.
In the present invention, an epoxy liquid resin is used as the resin 6, and the curing is completed at a temperature of 80 ° C. in about 1 hour. In the transfer mold technology used in the conventional example,
Cure at 180 ° C. for about 5 hours is required. For this reason,
The alloy is largely deteriorated by the high temperature of the semiconductor element 101, and the lead frame 101 protruding from the resin 106 is heavily oxidized by heat, so that a step such as removing the oxidized metal film is added. In the present invention, since a resin that cures at room temperature to a low temperature of 100 ° C. or lower can be used, a chip carrier can be manufactured without causing problems such as deterioration and oxidation due to high temperature.

【００１７】次に樹脂テープ５を剥離し、図３（ｄ）の
Ａ−Ａ’で示した一点鎖線に沿って、複数のチップキャ
リアをダイヤモンドカッターで各々切り放し、図１の構
造のチップキャリア１０００を製造する。さらに半田付
け性を良好にするため、樹脂６より露出しているリード
フレーム１上に無電解メッキ法によりＳｎ等のメッキを
施すことが出来る。このようにして複数のチップキャリ
アを同時に樹脂封止する事が出来るため、工数が削減さ
れ安価なチップキャリアを提供することが出来る。本実
施例では、３００ｍｍ角のリードフレーム上に１０ｍｍ
角のチップキャリアを２９行×２９列形成したことによ
り、８４１個のチップキャリアを同時に製造することが
出来た。また、その厚みは、リードフレーム１が約０．
３ｍｍ、半導体素子２が約０．２ｍｍ、金属細線４の半
導体素子２上からの高さが約０．１ｍｍであり、樹脂６
を含むチップキャリアの厚みは約０．７ｍｍの厚みであ
る。このような薄型のチップキャリアを本発明では容易
に供給できる。Next, the resin tape 5 is peeled off, and a plurality of chip carriers are cut off by a diamond cutter along the one-dot chain line indicated by AA 'in FIG. 3 (d), and the chip carrier 1000 having the structure shown in FIG. To manufacture. Furthermore, in order to improve the solderability, the lead frame 1 exposed from the resin 6 can be plated with Sn or the like by an electroless plating method. Since a plurality of chip carriers can be simultaneously resin-sealed in this manner, it is possible to provide an inexpensive chip carrier with reduced man-hours. In this embodiment, 10 mm is mounted on a 300 mm square lead frame.
By forming the square chip carriers in 29 rows × 29 columns, 841 chip carriers could be manufactured simultaneously. The lead frame 1 has a thickness of about 0.
3 mm, the semiconductor element 2 is about 0.2 mm, the height of the thin metal wire 4 from above the semiconductor element 2 is about 0.1 mm, and the resin 6
The thickness of the chip carrier including is about 0.7 mm. According to the present invention, such a thin chip carrier can be easily supplied.

【００１８】（実施例２）図４（ａ）および（ｂ）は、
本発明によるチップキャリア２０００のリードフレーム
へのメッキ方法および電気動作試験方法の一例を示した
断面図である。(Embodiment 2) FIGS. 4A and 4B show
FIG. 6 is a cross-sectional view showing an example of a method of plating the lead frame of the chip carrier 2000 and an electric operation test method according to the present invention.

【００１９】まず、実施例１の図３（ａ）〜図３（ｄ）
で示した方法と同様の方法で、樹脂封止されたリードフ
レーム１を得る。これを図４（ａ）に示すように、Ｂ−
Ｂ’で示した一点鎖線に沿ってリードフレーム１と樹脂
６の一部を切断する。この事により隣接するチップキャ
リアを電気的には切り放し、なおかつ機械的にはつなが
った状態を保持することが出来る。これをＳｎの無電解
メッキ浴に浸漬する事により樹脂６より露出したリード
フレーム１上にのみＳｎのメッキ膜７を約１〜１０μｍ
形成する。このメッキ膜７に半導体素子２の動作を確認
する試験器８と接続されているプローブ９を押し当てる
ことにより、チップキャリア２０００の動作を確認する
事ができる。チップキャリア２０００は、図４（ｂ）に
おいて、図中横方向及び奥行き方向に、チップキャリア
の寸法に従って、複数個のチップキャリアが等間隔に並
んでいる。このため、プローブ９をリードフレーム１に
押し当て、チップキャリア２０００の動作を確認し、プ
ローブ９をリードフレーム１より離し、プローブ９をチ
ップキャリア２０００の寸法に従って図中横または奥行
き方向に動かし、リードフレーム１に押し当てチップキ
ャリア２０００’の動作を確認することが出来る。この
ように複数のチップキャリアが一体で形成されているた
め、単純な動作の繰り返しにより、チップキャリアの電
気的動作試験を行なうことが出来るため、単体のチップ
キャリアを検査する方法に比較して、短時間で多くのチ
ップキャリアを検査することが出来る。電気的動作試験
後は、図４（ｂ）中Ｃで示した領域を切断することによ
り、単体のチップキャリアを得ることが出来る。First, FIG. 3A to FIG. 3D of the first embodiment.
The resin-sealed lead frame 1 is obtained by the same method as that shown in FIG. As shown in FIG.
A part of the lead frame 1 and the resin 6 is cut along the alternate long and short dash line indicated by B '. As a result, the adjacent chip carriers can be electrically disconnected and mechanically connected to each other. By immersing this in an electroless plating bath of Sn, the Sn plating film 7 is formed on the lead frame 1 exposed from the resin 6 by about 1 to 10 μm.
Form. The operation of the chip carrier 2000 can be confirmed by pressing the probe 9 connected to the tester 8 for confirming the operation of the semiconductor element 2 against the plated film 7. In the chip carrier 2000, in FIG. 4B, a plurality of chip carriers are arranged at equal intervals in the horizontal direction and the depth direction in the drawing according to the dimensions of the chip carrier. Therefore, the probe 9 is pressed against the lead frame 1, the operation of the chip carrier 2000 is confirmed, the probe 9 is separated from the lead frame 1, and the probe 9 is moved in the lateral or depth direction in the drawing in accordance with the dimensions of the chip carrier 2000. The operation of the chip carrier 2000 'pressed against the frame 1 can be confirmed. Since a plurality of chip carriers are integrally formed in this way, the electrical operation test of the chip carrier can be performed by repeating a simple operation, so compared with the method of inspecting a single chip carrier, Many chip carriers can be inspected in a short time. After the electrical operation test, a single chip carrier can be obtained by cutting the region indicated by C in FIG. 4B.

【００２０】（実施例３）図５（ａ）〜図５（ｃ）は、
本発明による他の一実施例を示す断面図である。実施例
１に示した図３（ａ）〜図３（ｄ）と同様な方法により
樹脂６で覆われたリードフレーム１を得る。その後、図
５（ａ）中Ｄで示す幅で図中上面より樹脂６とリードフ
レーム１の上面を切削除去する。次に図５（ｂ）中Ｅで
示す幅でリードフレーム１および樹脂６を切断し、単品
のチップキャリア３０００を得る。図５（ｃ）はチップ
キャリア３０００を基板１０上の配線パターン１１に半
田１２を用いて半田付けした状態を示している。この
際、図５（ａ）に示したように、リードフレーム１の上
面を切削することにより、図５（ｃ）のチップキャリア
３０００において、半田付けを行なうリードフレーム１
の露出面が、製品上面より容易に観察できる。これによ
って、チップキャリアを基板実装した際の半田付け性の
検査が簡便なチップキャリアを供給することが出来る。(Embodiment 3) FIGS. 5 (a) to 5 (c) show
It is sectional drawing which shows other one Example by this invention. The lead frame 1 covered with the resin 6 is obtained in the same manner as in FIGS. 3A to 3D shown in the first embodiment. After that, the resin 6 and the upper surface of the lead frame 1 are cut and removed from the upper surface in the drawing with a width indicated by D in FIG. 5A. Next, the lead frame 1 and the resin 6 are cut with a width indicated by E in FIG. 5B to obtain a single chip carrier 3000. FIG. 5C shows a state in which the chip carrier 3000 is soldered to the wiring pattern 11 on the substrate 10 using the solder 12. At this time, as shown in FIG. 5A, by cutting the upper surface of the lead frame 1, the lead frame 1 to be soldered in the chip carrier 3000 of FIG. 5C.
The exposed surface of can be observed more easily than the top surface of the product. As a result, it is possible to supply a chip carrier that can be easily tested for solderability when the chip carrier is mounted on a substrate.

【００２１】（実施例４）図６は、本発明による一実施
例であるチップキャリアの製造工程を示した断面図であ
る。まず、図６（ａ）に示すようにリードフレーム１と
なる例えば０．１５ｍｍのＣｕ箔の上面に配線形状に対
応した形、例えば図２の形状にレジスト１３を形成す
る。次にＣｕ箔の裏面に図中下面にもレジスト１３を形
成する。下面のレジスト１３は、チップキャリアに設け
るべき各端子の位置に対応するように配置してある。(Embodiment 4) FIG. 6 is a sectional view showing a manufacturing process of a chip carrier according to an embodiment of the present invention. First, as shown in FIG. 6A, a resist 13 having a shape corresponding to the wiring shape, for example, the shape shown in FIG. 2 is formed on the upper surface of a Cu foil of, for example, 0.15 mm to be the lead frame 1. Next, a resist 13 is formed on the back surface of the Cu foil and on the bottom surface in the figure. The resist 13 on the lower surface is arranged so as to correspond to the positions of the terminals to be provided on the chip carrier.

【００２２】次に、図６（ａ）を部材であるＣｕのエッ
チング液である塩化第二鉄溶液に浸漬し、パターンニン
グを行い図６（ｂ）に示すようなリードフレーム１の形
状を得る。この際、リードフレーム１は図中上面および
下面よりエッチングされ、本実施例の場合、エッチング
深さは０．０８〜０．０９ｍｍ程度になるように浸漬時
間によって制御しているため、図６（ｂ）の様な下面に
突起を持ったパターンとして形成されている。Next, FIG. 6A is dipped in a ferric chloride solution which is an etching solution of Cu which is a member, and patterning is performed to obtain a shape of the lead frame 1 as shown in FIG. 6B. . At this time, the lead frame 1 is etched from the upper surface and the lower surface in the figure, and in the case of this embodiment, the etching depth is controlled by the dipping time so as to be about 0.08 to 0.09 mm. It is formed as a pattern having protrusions on the lower surface as shown in b).

【００２３】次に、レジスト１３を水酸化カリウム水溶
液の剥離液に浸漬し除去する。その後、実施例１で述べ
た方法と同様な手法により、樹脂テープ５をリードフレ
ーム１の裏面にラミネートし、半導体素子１をリードフ
レーム１上に設置し、金属細線４を用いて接続し、さら
に、樹脂６で封止を行い図６（ｃ）の構造を得る。この
際、樹脂６は、リードフレーム１の裏面に形成した突起
の周囲に入り込む為、リードフレーム１の樹脂６より露
出した面は、リードフレーム１の突起面のみとなる。Next, the resist 13 is removed by immersing it in a stripping solution of an aqueous potassium hydroxide solution. After that, the resin tape 5 is laminated on the back surface of the lead frame 1 by the same method as that described in Example 1, the semiconductor element 1 is placed on the lead frame 1, and connected using the fine metal wires 4, and Then, the structure is sealed with resin 6 to obtain the structure shown in FIG. At this time, the resin 6 enters around the protrusion formed on the back surface of the lead frame 1, so that the surface of the lead frame 1 exposed from the resin 6 is only the protruding surface of the lead frame 1.

【００２４】次に、樹脂テープ５を剥離し、これをフロ
ー半田法により溶融半田に接触させることにより図６
（ｄ）に示すように裏面に露出したリードフレーム１の
突起部にのみ半田バンプ１４を形成することが出来る。
これを図６（ｄ）中、Ｆ−Ｆ’で示した一点鎖線上で切
断し、図６（ｅ）に示すチップキャリア４０００を得る
ことが出来る。Next, the resin tape 5 is peeled off and brought into contact with the molten solder by the flow soldering method, as shown in FIG.
As shown in (d), the solder bumps 14 can be formed only on the protrusions of the lead frame 1 exposed on the back surface.
This is cut along the alternate long and short dash line indicated by FF ′ in FIG. 6D to obtain the chip carrier 4000 shown in FIG. 6E.

【００２５】この方法により、半田バンプを持ったチッ
プキャリアが容易に形成できる。By this method, a chip carrier having solder bumps can be easily formed.

【００２６】（実施例５）実施例４に示したリードフレ
ーム１として、図７に示すように、図７中下面に突起を
形成した樹脂１５上に金属メッキ１６を施したリードフ
レームを用いることにより、エッチング法による実施例
４より、より安価で大量生産に適したチップキャリア５
０００を得ることが出来る。(Embodiment 5) As the lead frame 1 shown in Embodiment 4, as shown in FIG. 7, a lead frame in which metal plating 16 is applied on resin 15 having a projection formed on the lower surface in FIG. 7 is used. As a result, the chip carrier 5 which is cheaper and more suitable for mass production than the fourth embodiment by the etching method.
000 can be obtained.

【００２７】[0027]

【発明の効果】以上、本発明によれば、複数の半導体素
子搭載面を持つリードフレーム裏面に樹脂テープをラミ
ネートし、半導体素子を設置し、金属細線により接続を
行なった後、樹脂により封止し、樹脂テープを剥離し、
チップキャリア毎に切断する事によって、簡便な設備に
より、容易に大量のチップキャリアの構造と製造方法を
供給することが出来る。As described above, according to the present invention, a resin tape is laminated on the back surface of a lead frame having a plurality of semiconductor element mounting surfaces, the semiconductor element is installed, and the connection is made with a thin metal wire, followed by sealing with a resin. Then peel off the resin tape,
By cutting each chip carrier, it is possible to easily supply a large amount of chip carrier structures and manufacturing methods with simple equipment.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の一実施例を示す断面図。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図２】 本発明に用いるリードフレームの一実施例を
示す斜視図。FIG. 2 is a perspective view showing an embodiment of a lead frame used in the present invention.

【図３】 本発明の一製造方法を示す断面図。FIG. 3 is a cross-sectional view showing one manufacturing method of the present invention.

【図４】 本発明の一検査方法を示す断面図。FIG. 4 is a sectional view showing an inspection method of the present invention.

【図５】 本発明の一製造方法を示す断面図。FIG. 5 is a cross-sectional view showing one manufacturing method of the present invention.

【図６】 本発明の一製造方法を示す断面図。FIG. 6 is a cross-sectional view showing one manufacturing method of the present invention.

【図７】 本発明の一製造方法を示す断面図。FIG. 7 is a cross-sectional view showing one manufacturing method of the present invention.

【図８】 従来例を示す断面図。FIG. 8 is a sectional view showing a conventional example.

【図９】 従来例を示す断面図。FIG. 9 is a sectional view showing a conventional example.

【符号の説明】[Explanation of symbols]

１ リードフレーム １ａ リードフレーム１上の半導体素子搭載領域 １ｂ リードフレーム１上の端子領域 ２ 半導体素子 ３ ペースト ４ 金属細線 ５ 樹脂テープ ５ａ 樹脂テープ５上の粘着剤 ６ 樹脂 ７ 金属メッキ膜 ８ 電気動作試験器 ９ プローブ １０ 基板 １１ 配線パターン １２ 半田 １３ レジスト １４ 半田バンプ １５ 樹脂 １６ 金属メッキ １０１ リードフレーム １０２ 半導体素子 １０３ ペースト １０４ 金属細線 １０６ 樹脂 １０７ 金型 １０００〜５０００ チップキャリア 1 Lead Frame 1a Semiconductor Element Mounting Area on Lead Frame 1b Terminal Area on Lead Frame 1 Semiconductor Element 3 Paste 4 Metal Fine Wire 5 Resin Tape 5a Adhesive on Resin Tape 5 Resin 7 Metal Plated Film 8 Electrical Operation Test Container 9 Probe 10 Substrate 11 Wiring pattern 12 Solder 13 Resist 14 Solder bump 15 Resin 16 Metal plating 101 Lead frame 102 Semiconductor element 103 Paste 104 Metal fine wire 106 Resin 107 Mold 1000-5000 Chip carrier

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】半導体素子を搭載し、リードフレームの一
平面上に前記半導体素子を搭載し、前記半導体素子上の
電極と前記電極と対応した前記リードフレームとを金属
細線を用いて接続し、前記半導体素子と前記金属細線と
前記リードフレームの前記半導体素子を搭載した平面を
樹脂により封止した事を特徴とするチップキャリアの構
造。1. A semiconductor element is mounted, the semiconductor element is mounted on one plane of a lead frame, and an electrode on the semiconductor element and the lead frame corresponding to the electrode are connected using a thin metal wire. A structure of a chip carrier, wherein a plane on which the semiconductor element, the thin metal wire, and the semiconductor element of the lead frame are mounted is sealed with resin. 【請求項２】複数の半導体素子搭載面を持つリードフレ
ームの一平面に樹脂テープをラミネートする工程と、前
記リードフレームの前記樹脂テープをラミネートした対
面に半導体素子を搭載する工程と、前記半導体素子上の
電極と前記リードフレームとを金属細線を用いて接続す
る工程と、前記半導体素子と、前記金属細線と、前記リ
ードフレームの前記半導体素子を搭載した面とを覆うよ
うに樹脂を滴下し、樹脂を硬化させる工程と、前記樹脂
テープを剥離除去する工程と、前記樹脂で封止したリー
ドフレームを前記半導体素子毎に切断する工程とからな
る事を特徴とするチップキャリアの製造方法。2. A step of laminating a resin tape on one surface of a lead frame having a plurality of semiconductor element mounting surfaces, a step of mounting a semiconductor element on the opposite surface of the lead frame on which the resin tape is laminated, and the semiconductor element. A step of connecting the upper electrode and the lead frame by using a metal thin wire, the semiconductor element, the metal thin wire, and dropping resin so as to cover the surface of the lead frame on which the semiconductor element is mounted, A method of manufacturing a chip carrier, comprising a step of curing a resin, a step of peeling and removing the resin tape, and a step of cutting the lead frame sealed with the resin into each of the semiconductor elements. 【請求項３】複数の半導体素子搭載面を持つリードフレ
ームの一平面に樹脂テープをラミネートする工程と、前
記リードフレームの前記樹脂テープをラミネートした対
面に半導体素子を搭載する工程と、前記半導体素子上の
電極と前記リードフレームとを金属細線を用いて接続す
る工程と、前記半導体素子と、前記金属細線と、前記リ
ードフレームの前記半導体素子を搭載した面とを覆うよ
うに樹脂を滴下し、樹脂を硬化させる工程と、前記樹脂
テープを剥離除去する工程と、前記リードフレームと前
記樹脂の一部を前記半導体素子毎に切断する工程と、前
記リードフレームの前記樹脂より露出している部位に金
属メッキを施す工程と、前記リードフレームに探針を接
触させ電気的動作を確認する工程と、前記樹脂を前記半
導体素子毎に切断する工程を含む事を特徴とするチップ
キャリアの製造方法。3. A step of laminating a resin tape on one surface of a lead frame having a plurality of semiconductor element mounting surfaces, a step of mounting a semiconductor element on the opposite surface of the lead frame laminated with the resin tape, and the semiconductor element. A step of connecting the upper electrode and the lead frame by using a metal thin wire, the semiconductor element, the metal thin wire, and dropping resin so as to cover the surface of the lead frame on which the semiconductor element is mounted, A step of curing the resin, a step of peeling and removing the resin tape, a step of cutting a part of the lead frame and the resin for each of the semiconductor elements, and a part of the lead frame exposed from the resin. Metal plating step, step of contacting a probe to the lead frame to confirm electrical operation, cutting the resin into each semiconductor element Method for producing a chip carrier which comprises a that step. 【請求項４】複数の半導体素子搭載面を持つリードフレ
ームの一平面にエッチング法により突起を形成する工程
と、前記突起形成面に前記樹脂テープをラミネートする
工程と、前記リードフレームの樹脂テープをラミネート
した対面に半導体素子を搭載する工程と、前記半導体素
子上の電極と前記リードフレームとを金属細線を用いて
接続する工程と、前記半導体素子と、前記金属細線と、
前記リードフレームの前記半導体素子を搭載した面とを
覆うように樹脂を滴下し、樹脂を硬化させる工程と、前
記樹脂テープを剥離除去する工程と、前記樹脂より露出
した前記リードフレームの突起部に半田バンプを形成す
る工程と、前記樹脂で封止した前記リードフレームを前
記半導体素子毎に切断する工程とからなる事を特徴とす
るチップキャリアの製造方法。4. A step of forming projections on one surface of a lead frame having a plurality of semiconductor element mounting surfaces by an etching method, a step of laminating the resin tape on the projection forming surface, and a step of forming a resin tape of the lead frame. A step of mounting a semiconductor element on the laminated facing surface, a step of connecting the electrode on the semiconductor element and the lead frame using a thin metal wire, the semiconductor element, and the thin metal wire,
A step of dropping resin so as to cover the surface of the lead frame on which the semiconductor element is mounted and curing the resin, a step of peeling and removing the resin tape, and a protruding portion of the lead frame exposed from the resin. A method of manufacturing a chip carrier, comprising: a step of forming a solder bump; and a step of cutting the lead frame sealed with the resin into each of the semiconductor elements. 【請求項５】複数の半導体素子搭載面と複数の突起部を
持つ射出成形樹脂に金属メッキを施すことによりリード
フレームを形成する工程と、前記突起形成面に樹脂テー
プをラミネートする工程と、前記リードフレームの前記
樹脂テープをラミネートした対面に半導体素子を搭載す
る工程と、前記半導体素子上の電極と前記リードフレー
ムとを金属細線を用いて接続する工程と、前記半導体素
子と、前記金属細線と、前記リードフレームの前記半導
体素子を搭載した面とを覆うように樹脂を滴下し、樹脂
を硬化させる工程と、前記樹脂テープを剥離除去する工
程と、前記樹脂より露出した前記リードフレームの突起
部に半田バンプを形成する工程と、前記樹脂で封止した
前記リードフレームを前記半導体素子毎に切断する工程
とからなる事を特徴とするチップキャリアの製造方法。5. A step of forming a lead frame by metal plating an injection molding resin having a plurality of semiconductor element mounting surfaces and a plurality of protrusions, a step of laminating a resin tape on the protrusion forming surface, A step of mounting a semiconductor element on the opposite surface of the lead frame laminated with the resin tape; a step of connecting an electrode on the semiconductor element and the lead frame using a fine metal wire; the semiconductor element; and the fine metal wire. A step of dropping resin so as to cover the surface of the lead frame on which the semiconductor element is mounted and curing the resin, a step of peeling and removing the resin tape, and a protruding portion of the lead frame exposed from the resin It is characterized in that it comprises a step of forming solder bumps on the substrate and a step of cutting the lead frame sealed with the resin into the semiconductor elements. Method of manufacturing a chip carrier to be.
JP24036695A 1995-09-19 1995-09-19 Manufacturing method of chip carrier Expired - Lifetime JP3304705B2 (en)

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JP3304705B2 JP3304705B2 (en) 2002-07-22

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