JP2002083841A - Mounting structure and its manufacturing method - Google Patents
Mounting structure and its manufacturing methodInfo
- Publication number
- JP2002083841A JP2002083841A JP2000272188A JP2000272188A JP2002083841A JP 2002083841 A JP2002083841 A JP 2002083841A JP 2000272188 A JP2000272188 A JP 2000272188A JP 2000272188 A JP2000272188 A JP 2000272188A JP 2002083841 A JP2002083841 A JP 2002083841A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- terminal electrode
- circuit board
- input
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置を回路
基板上に実装した実装構造及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure in which a semiconductor device is mounted on a circuit board and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】携帯用電子機器の小型化、高性能化に伴
い、半導体デバイスなどの小型化、高性能化がますます
求められている。そのため端子ピン数が増加し、狭ピッ
チ化あるいはエリア配列にすることが重要となる。しか
し、狭ピッチ化にも限界があり、今以上の狭ピッチ化を
進める必要がある一方で、素子あるいは配線上にもパッ
ドを設けて実装することが重要となっている。これが可
能な技術として、ＩＢＭ社により開発された、半田バン
プによる通称Ｃ４（Controlled Collaps Chip Connecti
on）と呼ばれる実装技術がある。2. Description of the Related Art With miniaturization and high performance of portable electronic devices, miniaturization and high performance of semiconductor devices and the like are increasingly required. Therefore, the number of terminal pins increases, and it is important to reduce the pitch or to arrange the areas. However, there is a limit to narrowing the pitch, and while it is necessary to further narrow the pitch, it is important to provide a pad on an element or a wiring and mount it. As a technology that can achieve this, a so-called C4 (Controlled Collaps Chip Connecti
There is a mounting technology called on).
【０００３】図１８はその半田バンプの概略断面図であ
る。１１８はＩＣ基板であり、その表面はＳｉＯ2膜１
１７で被覆されている。１１５はＡｌのパッド電極であ
り、その上には、接続用の開口を残してガラス保護膜１
１６が形成されている。ＩＣチップのパッド電極１１５
の材料であるアルミニウムの表面には、アルミニウムの
酸化膜がついている。この酸化膜の除去処理を行った
後、真空蒸着によりバリアメタルを構成するＣｒ膜１１
４、Ｃｒ−Ｃｕ膜１１３、及びＣｕ−Ｓｎ金属間化合物
膜１１２を形成した後、Ｐｂ−Ｓｎ半田バンプ１１１を
形成する。これを回路基板の入出力端子電極上に当接し
てリフローすれば半田が溶融し接続が完了する。FIG. 18 is a schematic sectional view of the solder bump. Reference numeral 118 denotes an IC substrate whose surface is a SiO 2 film 1
17. Reference numeral 115 denotes an Al pad electrode, on which a glass protective film 1 is left with an opening for connection.
16 are formed. Pad electrode 115 of IC chip
An aluminum oxide film is provided on the surface of aluminum, which is a material of the above. After removing the oxide film, the Cr film 11 constituting the barrier metal is formed by vacuum evaporation.
4. After forming the Cr-Cu film 113 and the Cu-Sn intermetallic compound film 112, a Pb-Sn solder bump 111 is formed. If this is brought into contact with the input / output terminal electrodes of the circuit board and reflowed, the solder melts and the connection is completed.
【０００４】その他、バリアメタルを形成した後、Ａｕ
めっきバンプを形成した構造などもある。In addition, after forming a barrier metal, Au
There is also a structure in which plated bumps are formed.
【０００５】これらの従来技術によれば、ＩＣチップの
能動素子上に端子電極（パッド）を設けて、そこに突起
電極を形成してもＩＣチップの能動素子へのダメージが
ないことが期待できる。しかし、これらの技術はいずれ
もめっきもしくはそれに付随した処理がなされているた
め、めっきの装置、廃液処理、洗浄処理などに関係する
コスト高の問題、あるいは環境問題が常につきまとって
いる。そのため、民生機器では、実用化が難しい。ま
た、半田の場合、溶融するときフラックスが必要であ
り、溶融後の洗浄によるフラックス完全除去が困難であ
り、コスト高にもなる。According to these conventional techniques, even if a terminal electrode (pad) is provided on an active element of an IC chip and a protruding electrode is formed thereon, it can be expected that the active element of the IC chip will not be damaged. . However, since all of these techniques are subjected to plating or treatments associated therewith, there are always problems of high cost or environmental problems related to plating equipment, waste liquid treatment, cleaning treatment, and the like. For this reason, it is difficult to commercialize consumer appliances. Further, in the case of solder, a flux is required when the solder is melted, and it is difficult to completely remove the flux by washing after the melting, which increases the cost.
【０００６】一方、フリップチップ実装として、突起電
極が形成された半導体装置を、接合層を介して回路基板
の入出力端子電極上に実装する方式がある。この場合、
突起電極としては、電解めっき、あるいは無電解めっき
で生成された例えばＡｕ、Ｎｉなどで構成されたものを
用いる。また、接合層としては、半田、導電性接着剤
（等方的）、あるいは異方性導電膜（ACF:Anisotropic
Conductive Film）や異方性導電ペーストなどを用い
る。半田ペーストを用いる場合や導電性接着剤（等方
的）を用いる場合には、実装時にほとんど荷重を必要と
しないが、異方性導電膜（ＡＣＦ）や異方性導電ペース
トなどを用いる場合は、接続の安定性や信頼性を確保す
るためには、最大で２００ｇ／ピン程度の荷重を必要と
する場合もある。On the other hand, there is a method of flip-chip mounting in which a semiconductor device having a protruding electrode is mounted on an input / output terminal electrode of a circuit board via a bonding layer. in this case,
As the protruding electrode, an electrode made of, for example, Au, Ni or the like generated by electrolytic plating or electroless plating is used. Further, as the bonding layer, solder, conductive adhesive (isotropic), or anisotropic conductive film (ACF: Anisotropic conductive film)
Conductive Film) or anisotropic conductive paste. When using a solder paste or when using a conductive adhesive (isotropic), almost no load is required during mounting, but when using an anisotropic conductive film (ACF) or an anisotropic conductive paste, In order to ensure the stability and reliability of the connection, a load of about 200 g / pin may be required at the maximum.
【０００７】図１９に、異方性導電膜（ＡＣＦ）を用い
た場合の実装方法を示す。（ａ）に示すように、電極１
２２を有する第１基板１２１と、電極１２５を有する第
２基板１２６とを、導電粒子１２３と接着剤１２４から
なる異方性導電膜（ＡＣＦ）を挟んで重ね合わせて、加
熱・加圧する。それにより、（ｂ）に示すように、第１
基板１２１の電極１２２が、異方性導電膜（ＡＣＦ）を
介して、第２基板１２６の電極１２５と接続された実装
体を作成する。異方性導電膜（ＡＣＦ）の中に含まれて
いる導電粒子１２３としては、例えばＮｉ粒子、Ａｕ
（あるいはＮｉ−Ａｕ）コートされた樹脂ボールなどを
用いることができる。接着剤１２４としては、例えばエ
ポキシ系樹脂を用いる。熱と荷重を同時に作用させるこ
とにより、電極１２２と電極１２５の間に導電粒子１２
３が挟み込まれて接続が得られる。FIG. 19 shows a mounting method when an anisotropic conductive film (ACF) is used. As shown in FIG.
A first substrate 121 having an electrode 22 and a second substrate 126 having an electrode 125 are stacked with an anisotropic conductive film (ACF) made of conductive particles 123 and an adhesive 124 therebetween, and heated and pressed. As a result, as shown in FIG.
A package is formed in which the electrode 122 of the substrate 121 is connected to the electrode 125 of the second substrate 126 via an anisotropic conductive film (ACF). The conductive particles 123 contained in the anisotropic conductive film (ACF) include, for example, Ni particles and Au.
(Alternatively, Ni-Au) coated resin balls can be used. As the adhesive 124, for example, an epoxy resin is used. By applying heat and load simultaneously, the conductive particles 12 can be located between the electrodes 122 and 125.
3 is sandwiched to obtain a connection.
【０００８】あるいはＡｕからなる突起電極を、回路基
板の表面がＡｕからなる入出力端子電極に対して、Ａｕ
−Ａｕ接合させる場合も実装荷重と超音波が併用され
る。Alternatively, a bump electrode made of Au is connected to an input / output terminal electrode made of Au on the surface of the circuit board by Au.
-In the case of Au bonding, mounting load and ultrasonic waves are used together.
【０００９】[0009]
【発明が解決しようとする課題】以上のように実装のパ
ッケージ形態は、小型化、薄型化がますます追求されて
きている一方で、端子ピン数は今後も増加の一途であ
り、さらなる高性能化が求められてきている。そのため
現在以上の狭ピッチ接続が必要となり、その実現のため
の技術確立は一層難しくなってきている。そこで、従来
では半田でしか確立されていない、エリアアレイ配列な
どの素子上実装への展開も期待され、新たな要素技術の
開発が望まれている。また、低コスト化のために、今ま
で以上に実装工程における生産性をあげる必要がでてき
ており、タクト向上のために、ＡＣＦなどに代表される
熱圧着実装が注目を集めてきている。米国でも、半田の
樹脂先塗りのリフロー工法が主流となるとみられ、検討
がされ始めている。As described above, while the package form of mounting has been increasingly pursued to be smaller and thinner, the number of terminal pins will continue to increase in the future. Is required. For this reason, a narrower pitch connection than now is required, and it has become more difficult to establish a technology for realizing the connection. Therefore, development to on-device mounting such as an area array arrangement, which is conventionally established only with solder, is also expected, and development of a new element technology is desired. Further, it is necessary to increase the productivity in the mounting process more than ever for cost reduction, and thermocompression mounting represented by ACF or the like has been attracting attention for improving the tact time. In the United States, the reflow method of pre-coating solder resin is expected to be the mainstream, and studies have begun.
【００１０】しかし、異方性導電膜（ＡＣＦ）などの熱
圧着実装は、従来液晶分野では実績をあげてきたが、一
般的にはまだ普及しているとは言えない。それは、ＡＣ
Ｆの中に含まれている導電粒子や熱膨張係数を制御する
ために混入されているシリカフィラーが、実装時に素子
面に応力を及ぼし、素子にダメージを与えたり、Ａｌ配
線が断線するなどの不良を発生させていたからである。
また、突起電極が回路基板の入出力端子電極に導電性フ
ィラーをかみながらも直接接触しつつ樹脂が硬化するた
めに、応力を緩和する要素が存在せず素子特性を劣化さ
せることになる。また、樹脂基板の入出力端子電極上に
実装する場合には、実装時に入出力端子電極が変形し、
基板内のビアが断裂する不良が生じる場合などもあっ
た。However, thermocompression bonding of an anisotropic conductive film (ACF) or the like has hitherto been successful in the field of liquid crystal, but is not generally widespread. It is AC
The conductive particles contained in F and the silica filler mixed in to control the thermal expansion coefficient exert stress on the element surface during mounting, causing damage to the element and disconnection of the Al wiring. This is because a defect was generated.
In addition, since the resin is cured while the protruding electrode is in direct contact with the input / output terminal electrode of the circuit board while biting the conductive filler, there is no element for relaxing the stress, and the device characteristics are degraded. Also, when mounting on the input / output terminal electrodes of the resin substrate, the input / output terminal electrodes are deformed during mounting,
In some cases, there was a defect that a via in the substrate was broken.
【００１１】図２０は、図１９のような構造で従来の異
方性導電膜（ＡＣＦ）を用いて実装したときの結果を示
している。半導体装置の突起電極にはワイヤボンディン
グ法を用いて形成されたＡｕバンプ、基板にはセラミッ
ク基板とガラスエポキシ基板（ＦＲ４）、ＡＣＦには５
μｍφのＮｉフィラーを含んだ厚み７０μｍのものを用
いた。（ａ）は、実装後の１ピン当たりの初期接続抵抗
を示している。これには半導体装置の端子電極、Ａｕバ
ンプ、ＡＣＦの抵抗が含まれている。セラミックの場
合、実装荷重が８０ｇ／ｂｕｍｐないと初期の接続が得
られなかった。ガラスエポキシ基板でも８０ｇ／ｂｕｍ
ｐかけないと抵抗値が安定しなかった。また（ｂ）は、
各サンプルの温度に対する抵抗値変化を示す。ガラスエ
ポキシ基板（ＦＲ４）の実装荷重が４０、８０ｇ／ｂｕ
ｍｐのものが安定している。セラミック基板に実装した
場合では、高温になると実装荷重が８０ｇ／ｂｕｍｐの
ものでも接続不良が発生した。そして（ｃ）の熱衝撃試
験（液相−５５〜１２５℃）に投入した結果では、実装
荷重が４０ｇ／ｂｕｍｐの場合と８０ｇ／ｂｕｍｐの場
合の間にも差が生じている。FIG. 20 shows the result when mounting is performed using a conventional anisotropic conductive film (ACF) with the structure shown in FIG. Au bumps formed by a wire bonding method are used for the bump electrodes of the semiconductor device, a ceramic substrate and a glass epoxy substrate (FR4) are used for the substrate, and 5 are used for the ACF.
A 70 μm-thick one containing a μmφ Ni filler was used. (A) shows the initial connection resistance per pin after mounting. This includes the terminal electrodes of the semiconductor device, the Au bumps, and the resistance of the ACF. In the case of ceramic, an initial connection could not be obtained unless the mounting load was 80 g / bump. 80g / bum even on glass epoxy board
Unless p was applied, the resistance value was not stabilized. (B)
The change in resistance value with respect to the temperature of each sample is shown. Mounting load of glass epoxy board (FR4) is 40, 80g / bu
mp's are stable. In the case of mounting on a ceramic substrate, connection failure occurred at high temperatures even when the mounting load was 80 g / bump. As a result of the thermal shock test (liquid phase −55 to 125 ° C.) of (c), there is a difference between the case where the mounting load is 40 g / bump and the case where the mounting load is 80 g / bump.
【００１２】さらに、図２１は各実装荷重における断面
構造を調べた写真である。（ａ）〜（ｅ）はガラスエポ
キシ基板（ＦＲ４）を用いた場合、（ｆ）はセラミック
基板を用いた場合を示す。ガラスエポキシ基板（ＦＲ
４）の場合、入出力端子電極の変形が実装荷重１５ｇ／
ｂｕｍｐ付近から生じていることがわかる。セラミック
基板では基板に剛性があるため、実装荷重が８０ｇ／ｂ
ｕｍｐでも入出力端子電極の変形は起きていないが、初
期の接続が不安定で、図２０（ｂ）の温度特性では接続
不良を引き起こしてしまう。FIG. 21 is a photograph showing the cross-sectional structure at each mounting load. (A) to (e) show the case where a glass epoxy substrate (FR4) is used, and (f) shows the case where a ceramic substrate is used. Glass epoxy board (FR
In the case of 4), the deformation of the input / output terminal electrode is 15 g /
It can be seen that it occurs near the bump. In the case of a ceramic substrate, the mounting load is 80 g / b because the substrate is rigid.
Although no deformation of the input / output terminal electrode occurs even in the case of “ump”, the initial connection is unstable, and a connection failure is caused in the temperature characteristic of FIG.
【００１３】本発明は、実装時にフラックスを供給する
ことなく、低抵抗で信頼性の高い接続ができ、また、実
装荷重も小さくてすむ高生産に適した熱圧着実装を可能
とする実装構造及びその製造方法を提供することを目的
とする。According to the present invention, there is provided a mounting structure capable of performing a thermocompression bonding suitable for high production, which can provide a low-resistance and highly reliable connection without supplying a flux at the time of mounting and which requires a small mounting load. It is an object of the present invention to provide a manufacturing method thereof.
【００１４】[0014]
【課題を解決するための手段】本発明は、半田を熱と荷
重を併用して実装することにより、半田と端子電極の界
面における拡散により金属間化合物を形成して、良好な
接続状態を得ることを特徴とする。SUMMARY OF THE INVENTION The present invention provides a good connection state by forming an intermetallic compound by diffusion at the interface between a solder and a terminal electrode by mounting the solder using both heat and a load. It is characterized by the following.
【００１５】すなわち、本発明の実装構造は、端子電極
を有する半導体装置を入出力端子電極を有する回路基板
上に実装した実装構造であって、端子電極と入出力端子
電極の間は、入出力端子電極上に設けられた半田、およ
び半田と端子電極の界面に形成された金属間化合物によ
り接続され、少なくとも半田と金属間化合物の周囲が封
止樹脂に囲まれて接続が補強された構成である。金属間
化合物は、半田と端子電極が熱圧着されたときに形成さ
れたものである。That is, the mounting structure of the present invention is a mounting structure in which a semiconductor device having terminal electrodes is mounted on a circuit board having input / output terminal electrodes. It is connected by the solder provided on the terminal electrode, and the intermetallic compound formed at the interface between the solder and the terminal electrode, and at least the periphery of the solder and the intermetallic compound is surrounded by the sealing resin and the connection is reinforced. is there. The intermetallic compound is formed when the solder and the terminal electrode are thermocompression bonded.
【００１６】この構成によれば、接触によるよりもより
低抵抗で信頼性の高い接続ができ、また、実装荷重も小
さくてすむ高生産に適した熱圧着実装が可能になる。According to this configuration, a highly reliable connection can be achieved with lower resistance than by contact, and a thermocompression bonding suitable for high production requiring a small mounting load can be realized.
【００１７】上記構成を一部変更して、半田を半導体装
置の端子電極上に設け、回路基板の入出力端子電極と半
田の界面に金属間化合物を形成するようにしてもよい。The above structure may be partially modified so that solder is provided on the terminal electrode of the semiconductor device and an intermetallic compound is formed at the interface between the input / output terminal electrode of the circuit board and the solder.
【００１８】さらに、接続部を補強する樹脂に空気を発
生する成分を含ませることにより、実装構造に気泡を含
み高周波特性にも優れた構造にすることができる。Furthermore, by including a component that generates air in the resin that reinforces the connection portion, it is possible to provide a structure having bubbles in the mounting structure and having excellent high-frequency characteristics.
【００１９】本発明の実装構造の製造方法は、端子電極
を有する半導体装置を入出力端子電極を有する回路基板
に実装するための製造方法であって、入出力端子電極上
に半田が形成され、少なくとも半田の周囲の表面部に樹
脂膜が設けられて、樹脂膜の厚さが半田の高さ以下であ
る回路基板を用いる。半導体装置を、その端子電極が半
田に対向するように回路基板上に載置して熱圧着を施す
ことにより、まず半田が端子電極に接触して界面に金属
間化合物を形成し、その後溶けた樹脂膜が少なくとも半
田及び金属間化合物の周囲を取り囲む。この製造方法に
おいて、半田を半導体装置の端子電極上に設け、回路基
板の入出力端子電極と半田の界面に金属間化合物を形成
するようにしてもよい。A method of manufacturing a mounting structure according to the present invention is a method for mounting a semiconductor device having terminal electrodes on a circuit board having input / output terminal electrodes, wherein solder is formed on the input / output terminal electrodes, A circuit board is used in which a resin film is provided at least on the surface around the solder and the thickness of the resin film is equal to or less than the height of the solder. The semiconductor device was placed on a circuit board so that its terminal electrodes face the solder and subjected to thermocompression bonding, so that the solder first contacted the terminal electrodes to form an intermetallic compound at the interface, and then melted. A resin film surrounds at least the solder and the intermetallic compound. In this manufacturing method, the solder may be provided on the terminal electrode of the semiconductor device, and an intermetallic compound may be formed at the interface between the input / output terminal electrode of the circuit board and the solder.
【００２０】上記の製造方法において、封止樹脂は、樹
脂膜の形態に限らず、実装部位を含む回路基板の一部に
供給する等、必要に応じた自由な形態をとって配置する
ことができる。In the above-described manufacturing method, the sealing resin is not limited to the form of the resin film, and may be arranged in any form as required, such as supplying the sealing resin to a part of the circuit board including the mounting portion. it can.
【００２１】[0021]
【発明の実施の形態】（実施の形態１）図１は、本発明
の実施の形態１にかかる実装構造の概略断面図である。
回路基板１４の入出力端子電極１３上に存在する半田１
２が、半導体装置１６の端子電極１７との熱圧着で、界
面に金属間化合物１８を形成し、接続部の周りが封止樹
脂１１で補強された構造になっている。封止樹脂１１中
には、気泡１０が存在する。(Embodiment 1) FIG. 1 is a schematic sectional view of a mounting structure according to Embodiment 1 of the present invention.
Solder 1 existing on input / output terminal electrode 13 of circuit board 14
2 has a structure in which an intermetallic compound 18 is formed at the interface by thermocompression bonding with the terminal electrode 17 of the semiconductor device 16, and the periphery of the connection portion is reinforced by the sealing resin 11. Bubbles 10 are present in the sealing resin 11.
【００２２】このようにすれば、実装時にフラックスを
供給することなく、半田１２を熱と荷重を併用して実装
することで、界面における拡散により金属間化合物１８
が形成される。それにより、接触による場合よりもより
低抵抗で信頼性の高い接続を実現できる。また、実装荷
重も小さくてすみ、樹脂基板はもちろんのこと、剛性の
高いセラミック基板でも適用できる。また、気泡１０の
存在により、空気の方が樹脂よりも誘電率が明らかに低
いので、高周波特性に有利な構造とすることができる。In this way, the solder 12 is mounted by using both heat and load without supplying flux at the time of mounting.
Is formed. Thereby, a highly reliable connection with lower resistance can be realized as compared with the case of contact. Further, the mounting load can be small, and the present invention can be applied not only to a resin substrate but also to a highly rigid ceramic substrate. In addition, the presence of the air bubbles 10 allows air to have a significantly lower dielectric constant than resin, thereby providing a structure advantageous for high-frequency characteristics.
【００２３】ここで、半田１２の材料としては、例えば
Ａｕ、Ａｌ、Ｐｄ、Ｐｂ、Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔ
ｉ、Ｎｉ、Ｃｒ、Ａｇ、Ｐｔ、Ｓｂの少なくとも１種を
用いることができる。そして、半田１２を形成するため
には、例えば蒸着、めっき、溶射（溶かした半田をふき
つける方法）など、どのような方法を用いても良い。Here, as a material of the solder 12, for example, Au, Al, Pd, Pb, Sn, Cu, In, Bi, T
At least one of i, Ni, Cr, Ag, Pt, and Sb can be used. In order to form the solder 12, any method such as vapor deposition, plating, and thermal spraying (a method of wiping the melted solder) may be used.
【００２４】また、封止樹脂１１としては、エポキシ系
樹脂を主成分として含み、ＳｉＯ2やＡｌ2Ｏ3、ＳｉＮ
などの無機物の粒子だけを含んだ絶縁樹脂を用いること
ができる。含まれる粒子は無機物であれば何でもよい。
また、気泡１０の量は、封止樹脂１１が反応して硬化す
るときに気泡１０を発生させるような成分、例えば反応
性希釈剤などの量を制御することにより変えることがで
きる。The sealing resin 11 contains an epoxy resin as a main component, and is made of SiO 2 , Al 2 O 3 , SiN
For example, an insulating resin containing only inorganic particles can be used. The contained particles may be any inorganic materials.
Further, the amount of the bubble 10 can be changed by controlling the amount of a component that generates the bubble 10 when the sealing resin 11 reacts and cures, for example, a reactive diluent.
【００２５】金属間化合物１８の形成については、金属
どうしは少なからず熱により拡散する性質があり、互い
の拡散係数の違いにより組成や厚みなどは変化するが、
互いに拡散しうるあらゆる金属の組み合わせが可能であ
る。Regarding the formation of the intermetallic compound 18, the metals have the property of diffusing due to heat to a considerable extent, and the composition and thickness vary depending on the difference in their diffusion coefficients.
Any combination of metals that can diffuse with each other is possible.
【００２６】（実施の形態２）図２は、本発明の実施の
形態２にかかる実装構造の概略断面図である。半導体装
置２６の端子電極２７上に存在する半田２２が、回路基
板２４の入出力端子電極２３との熱圧着で界面に金属間
化合物２８を形成し、接続部の周りが封止樹脂２１で補
強された構造になっている。封止樹脂２１中には気泡２
０が存在する。(Embodiment 2) FIG. 2 is a schematic sectional view of a mounting structure according to Embodiment 2 of the present invention. The solder 22 present on the terminal electrode 27 of the semiconductor device 26 forms an intermetallic compound 28 at the interface by thermocompression bonding with the input / output terminal electrode 23 of the circuit board 24, and the periphery of the connection portion is reinforced with the sealing resin 21. The structure has been. Bubbles 2 in the sealing resin 21
0 exists.
【００２７】このようにすれば、実装時にフラックスを
供給することなく、半田２２を熱と荷重を併用して実装
することで、界面における拡散により金属間化合物２８
が形成され、接触によるよりもより低抵抗で信頼性の高
い接続ができる。また、実装荷重も小さくてすみ、樹脂
基板はもちろんのこと剛性の高いセラミック基板でも適
用できる。また、気泡２０の存在により、空気の方が樹
脂よりも誘電率が明らかに低いので、高周波特性に有利
な構造とすることができる。In this manner, the solder 22 is mounted by using both heat and load without supplying a flux at the time of mounting, whereby the intermetallic compound 28 is diffused at the interface.
Is formed, and a connection with lower resistance and higher reliability than by contact can be made. Further, the mounting load can be reduced, and the present invention can be applied to not only a resin substrate but also a ceramic substrate having high rigidity. In addition, since the presence of the bubbles 20 makes air have a significantly lower dielectric constant than resin, a structure advantageous for high-frequency characteristics can be obtained.
【００２８】ここで、半田２２の材料としては、例えば
Ａｕ、Ａｌ、Ｐｄ、Ｐｂ、Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔ
ｉ、Ｎｉ、Ｃｒ、Ａｇ、Ｐｔ、Ｓｂの少なくとも１種を
用いることができる。そして、半田２２を形成するため
には、例えば蒸着、めっき、溶射（溶かした半田をふき
つける方法）など、どのような方法を用いても良い。Here, as a material of the solder 22, for example, Au, Al, Pd, Pb, Sn, Cu, In, Bi, T
At least one of i, Ni, Cr, Ag, Pt, and Sb can be used. To form the solder 22, any method such as vapor deposition, plating, and thermal spraying (a method of wiping the melted solder) may be used.
【００２９】また、封止樹脂２１としては、エポキシ系
樹脂を主成分として含み、ＳｉＯ2やＡｌ2Ｏ3、ＳｉＮ
などの無機物の粒子だけを含んだ絶縁樹脂を用いること
ができる。含まれる粒子は無機物であれば何でもよい。
また、気泡２０の量は封止樹脂２１が反応して硬化する
ときに気泡を発生させるような成分、例えば反応性希釈
剤などの量を制御することにより変えることができる。The sealing resin 21 contains an epoxy resin as a main component, and is made of SiO 2 , Al 2 O 3 , SiN
For example, an insulating resin containing only inorganic particles can be used. The contained particles may be any inorganic materials.
Further, the amount of the bubbles 20 can be changed by controlling the amount of a component that generates bubbles when the sealing resin 21 reacts and cures, for example, a reactive diluent.
【００３０】金属間化合物２８の形成については、金属
どうしは少なからず熱により拡散する性質があり、互い
の拡散係数の違いにより組成や厚みなどは変化するが、
互いに拡散しうるあらゆる金属の組み合わせが可能であ
る。Regarding the formation of the intermetallic compound 28, the metals have the property of diffusing due to heat to a considerable extent, and the composition and thickness vary depending on the difference in their diffusion coefficients.
Any combination of metals that can diffuse with each other is possible.
【００３１】（実施の形態３）図３は本発明の実施の形
態３にかかる回路基板の概略断面図である。回路基板３
４の入出力端子電極３３上に半田３２が存在し、そのま
わりを樹脂膜３１（フィルム）で取り囲まれている。こ
こで、樹脂膜３１の厚みに対して、半田３２の高さが等
しいか高い構造になっている。これは、フラックスを供
給することなく、半田３２を半導体装置の端子電極と熱
圧着させることにより実装することを想定している。(Embodiment 3) FIG. 3 is a schematic sectional view of a circuit board according to Embodiment 3 of the present invention. Circuit board 3
The solder 32 is present on the input / output terminal electrode 33 of No. 4 and is surrounded by a resin film 31 (film). Here, the height of the solder 32 is equal to or higher than the thickness of the resin film 31. This assumes that the solder 32 is mounted by thermocompression bonding with the terminal electrode of the semiconductor device without supplying a flux.
【００３２】このような構造にすることにより、熱圧着
時にまず半田３２が半導体装置の端子電極に到達し、拡
散により金属間化合物を生成して接続を得ることができ
る。その後溶けた樹脂膜３１が接続部を補強する。これ
により、より安定な接続を得ることができる。With such a structure, the solder 32 first reaches the terminal electrode of the semiconductor device at the time of thermocompression bonding, and the connection can be obtained by generating an intermetallic compound by diffusion. Thereafter, the melted resin film 31 reinforces the connection portion. Thereby, a more stable connection can be obtained.
【００３３】ここで、半田３２の材料としては、例えば
Ａｕ、Ａｌ、Ｐｄ、Ｐｂ、Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔ
ｉ、Ｎｉ、Ｃｒ、Ａｇ、Ｐｔ、Ｓｂの少なくとも１種を
用いることができる。また、樹脂膜３１としては、エポ
キシ系樹脂を主成分として含み、ＳｉＯ2やＡｌ2Ｏ3、
ＳｉＮなどの無機物の粒子だけを含んだ絶縁膜を用いる
ことができる。含まれる粒子は無機物であれば何でもよ
い。Here, as a material of the solder 32, for example, Au, Al, Pd, Pb, Sn, Cu, In, Bi, T
At least one of i, Ni, Cr, Ag, Pt, and Sb can be used. The resin film 31 includes an epoxy resin as a main component, and includes SiO 2 , Al 2 O 3 ,
An insulating film containing only inorganic particles such as SiN can be used. The contained particles may be any inorganic materials.
【００３４】（実施の形態４）図４は本発明の実施の形
態４にかかる半導体装置の概略断面図である。半導体装
置４６の端子電極４７上に半田４２が存在し、そのまわ
りを樹脂膜４１（フィルム）で取り囲まれている。ここ
で、樹脂膜４１の厚みに対して、半田４２の高さが等し
いか高い構造になっている。これは、フラックスを供給
することなく、半田４２を回路基板の入出力端子電極と
熱圧着させることにより実装することを想定している。(Fourth Embodiment) FIG. 4 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the present invention. The solder 42 exists on the terminal electrode 47 of the semiconductor device 46 and is surrounded by the resin film 41 (film). Here, the height of the solder 42 is equal to or higher than the thickness of the resin film 41. This assumes that the solder 42 is mounted by thermocompression bonding with the input / output terminal electrodes of the circuit board without supplying a flux.
【００３５】このような構造にすることにより、熱圧着
時にまず半田４２が回路基板の入出力端子電極に到達
し、拡散により金属間化合物を生成して接続を得ること
ができる。その後溶けた樹脂膜４１が接続部を補強す
る。これにより、より安定な接続を得ることができる。With such a structure, the solder 42 first reaches the input / output terminal electrodes of the circuit board during thermocompression bonding, and an intermetallic compound is generated by diffusion to obtain a connection. Thereafter, the melted resin film 41 reinforces the connection portion. Thereby, a more stable connection can be obtained.
【００３６】ここで、半田の材料としては、例えばＡ
ｕ、Ａｌ、Ｐｄ、Ｐｂ、Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔ
ｉ、Ｎｉ、Ｃｒ、Ａｇ、Ｐｔ、Ｓｂの少なくとも１種を
用いることができる。また、樹脂膜４１としては、エポ
キシ系樹脂を主成分として含み、ＳｉＯ2やＡｌ2Ｏ3、
ＳｉＮなどの無機物の粒子だけを含んだ絶縁膜を用いる
ことができる。含まれる粒子は無機物であれば何でもよ
い。Here, as a material of the solder, for example, A
u, Al, Pd, Pb, Sn, Cu, In, Bi, T
At least one of i, Ni, Cr, Ag, Pt, and Sb can be used. The resin film 41 includes an epoxy-based resin as a main component, and includes SiO 2 , Al 2 O 3 ,
An insulating film containing only inorganic particles such as SiN can be used. The contained particles may be any inorganic materials.
【００３７】（実施の形態５）図５は、本発明の実施の
形態５にかかる実装構造の製造方法を示す概略断面図で
ある。図５（ａ）に示すように、回路基板５４の入出力
端子電極５３上に半田５２を設け、さらにその周囲をと
り囲む樹脂膜５１（フィルム）を設ける。樹脂膜５１の
厚みは、半田５２の高さに等しいかそれより低くする。
また、端子電極５７が設けられた半導体装置５６を準備
し、端子電極５７が半田５２に当接するように、回路基
板５４上に載置する。次に、図５（ｂ）に示すように、
フラックスを供給することなく、半田５２を半導体装置
５６の端子電極５７と熱圧着させる。それにより、半田
５２と端子電極５７の界面に金属間化合物５８を形成す
る。(Fifth Embodiment) FIG. 5 is a schematic sectional view showing a method of manufacturing a mounting structure according to a fifth embodiment of the present invention. As shown in FIG. 5A, a solder 52 is provided on an input / output terminal electrode 53 of a circuit board 54, and a resin film 51 (film) surrounding the periphery is provided. The thickness of the resin film 51 is equal to or lower than the height of the solder 52.
Further, a semiconductor device 56 provided with a terminal electrode 57 is prepared, and placed on the circuit board 54 such that the terminal electrode 57 contacts the solder 52. Next, as shown in FIG.
The solder 52 is thermocompression bonded to the terminal electrode 57 of the semiconductor device 56 without supplying a flux. Thus, an intermetallic compound 58 is formed at the interface between the solder 52 and the terminal electrode 57.
【００３８】このような方法で製造することで、熱圧着
時にまず半田５２が回路基板５４の入出力端子電極５３
に到達し、拡散により金属間化合物５８を生成して接続
を得ることができる。その後溶けた樹脂膜５１が接続部
を補強する。これにより、より安定な接続を得ることが
できる。しかも、実装後はフラックスの洗浄が不要であ
る。また、従来の異方性導電膜（ＡＣＦ）などに比べて
低荷重実装が可能になり、セラミック基板でも安定な接
続が得られる。By manufacturing in this manner, the solder 52 is first connected to the input / output terminal electrodes 53 of the circuit board 54 during thermocompression bonding.
And an intermetallic compound 58 is generated by diffusion to obtain a connection. Thereafter, the melted resin film 51 reinforces the connection portion. Thereby, a more stable connection can be obtained. Moreover, after mounting, cleaning of the flux is unnecessary. Further, mounting with a lower load is possible as compared with a conventional anisotropic conductive film (ACF) or the like, and a stable connection can be obtained even with a ceramic substrate.
【００３９】なお、図では樹脂膜５１中に気泡は存在し
ていないが、気泡を含んでいても問題ない。これにより
むしろ高周波特性に有利な構造とすることができる。さ
らに、気泡の量は、樹脂膜５１が反応して硬化するとき
に気泡を発生させるような成分、例えば反応性希釈剤な
どの量を制御することにより変えることができる。Although no air bubbles are present in the resin film 51 in the drawing, there is no problem even if air bubbles are included. Thereby, a structure more advantageous for high frequency characteristics can be obtained. Furthermore, the amount of bubbles can be changed by controlling the amount of a component that generates bubbles when the resin film 51 reacts and cures, for example, a reactive diluent.
【００４０】半田５２の材料としては、例えばＡｕ、Ａ
ｌ、Ｐｄ、Ｐｂ、Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔｉ、Ｎ
ｉ、Ｃｒ、Ａｇ、Ｐｔ、Ｓｂの少なくとも１種を用いる
ことができる。また、樹脂膜５１としては、エポキシ系
樹脂を主成分として含み、ＳｉＯ2やＡｌ2Ｏ3、ＳｉＮ
などの無機物の粒子だけを含んだ絶縁膜を用いることが
できる。含まれる粒子は無機物であれば何でもよい。As a material of the solder 52, for example, Au, A
1, Pd, Pb, Sn, Cu, In, Bi, Ti, N
At least one of i, Cr, Ag, Pt, and Sb can be used. The resin film 51 includes an epoxy-based resin as a main component, and includes SiO 2 , Al 2 O 3 , SiN
For example, an insulating film containing only inorganic particles can be used. The contained particles may be any inorganic materials.
【００４１】（実施の形態６）図６は、本発明の実施の
形態６にかかる実装構造の製造方法を示す概略断面図で
ある。図６（ａ）に示すように、半導体装置６６の端子
電極６７上に半田６２を設け、その周囲を取り囲む樹脂
膜６１（フィルム）を設ける。樹脂膜６１の厚みは、半
田６２の高さと等しいかそれより低くする。また、入出
力端子電極６３が設けられた回路基板６４を準備し、半
田６２が入出力端子電極６３に当接するように、半導体
装置６６を回路基板６４上に載置する。次に、図６
（ｂ）に示すように、フラックスを供給することなく、
半田６２を入出力端子電極６３と熱圧着させる。それに
より、半田６２と入出力端子電極６３の界面に金属間化
合物６８を形成して、所望の実装構造を得る。しかも、
実装後はフラックスの洗浄がいらない。また、従来の異
方性導電膜（ＡＣＦ）などに比べて低荷重実装が可能に
なり、セラミック基板でも安定な接続が得られる。(Embodiment 6) FIG. 6 is a schematic sectional view showing a method for manufacturing a mounting structure according to Embodiment 6 of the present invention. As shown in FIG. 6A, a solder 62 is provided on a terminal electrode 67 of a semiconductor device 66, and a resin film 61 (film) surrounding the solder is provided. The thickness of the resin film 61 is equal to or lower than the height of the solder 62. Further, a circuit board 64 provided with the input / output terminal electrodes 63 is prepared, and the semiconductor device 66 is mounted on the circuit board 64 such that the solder 62 contacts the input / output terminal electrodes 63. Next, FIG.
As shown in (b), without supplying flux,
The solder 62 is thermocompression-bonded to the input / output terminal electrode 63. Thus, an intermetallic compound 68 is formed at the interface between the solder 62 and the input / output terminal electrode 63, and a desired mounting structure is obtained. Moreover,
No flux cleaning is required after mounting. Further, mounting with a lower load is possible as compared with a conventional anisotropic conductive film (ACF) or the like, and a stable connection can be obtained even with a ceramic substrate.
【００４２】なお、図では樹脂中に気泡は存在していな
いが、気泡を含んでいても問題ない。これによりむしろ
高周波特性に有利な構造とすることができる。さらに、
気泡の量は、樹脂膜６１が反応して硬化するときに気泡
を発生させるような成分、例えば反応性希釈剤などの量
を制御することにより変えることができる。Although no bubbles are present in the resin in the figure, there is no problem even if bubbles are contained. Thereby, a structure more advantageous for high frequency characteristics can be obtained. further,
The amount of bubbles can be changed by controlling the amount of a component that generates bubbles when the resin film 61 reacts and cures, for example, a reactive diluent.
【００４３】半田の材料としては、例えばＡｕ、Ａｌ、
Ｐｄ、Ｐｂ、Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔｉ、Ｎｉ、Ｃ
ｒ、Ａｇ、Ｐｔ、Ｓｂの少なくとも１種を用いることが
できる。また、樹脂膜６１としては、エポキシ系樹脂を
主成分として含み、ＳｉＯ2やＡｌ2Ｏ3、ＳｉＮなどの
無機物の粒子だけを含んだ絶縁膜を用いることができ
る。含まれる粒子は無機物であれば何でもよい。As the material of the solder, for example, Au, Al,
Pd, Pb, Sn, Cu, In, Bi, Ti, Ni, C
At least one of r, Ag, Pt, and Sb can be used. In addition, as the resin film 61, an insulating film containing an epoxy resin as a main component and containing only inorganic particles such as SiO 2 , Al 2 O 3 , and SiN can be used. The contained particles may be any inorganic materials.
【００４４】（実施の形態７）図７は、本発明の実施の
形態７にかかる実装構造の製造方法を示す概略断面図で
ある。図７（ａ）に示すように、回路基板７４の入出力
端子電極７３上に半田７２を設け、さらに封止樹脂７１
（液状または樹脂膜）を供給する。封止樹脂７１は半田
７２を覆っていてもいなくてもよい。ただし、半導体装
置７６が実装される領域の少なくとも一部に供給され
る。そして、半導体装置７６に設けられた端子電極７７
が、半田７２に当接するように、半導体装置７６を回路
基板７４上に載置する。次に、図７（ｂ）に示すよう
に、フラックスを供給することなく、半田７２を端子電
極７７と熱圧着させ、それにより、界面に金属化合物７
８を形成して所望の実装構造を得る。(Embodiment 7) FIG. 7 is a schematic sectional view showing a method of manufacturing a mounting structure according to Embodiment 7 of the present invention. As shown in FIG. 7A, a solder 72 is provided on an input / output terminal electrode 73 of a circuit board 74, and a sealing resin 71 is further provided.
(Liquid or resin film). The sealing resin 71 may or may not cover the solder 72. However, it is supplied to at least a part of a region where the semiconductor device 76 is mounted. Then, the terminal electrode 77 provided on the semiconductor device 76 is provided.
However, the semiconductor device 76 is placed on the circuit board 74 so as to be in contact with the solder 72. Next, as shown in FIG. 7B, the solder 72 is thermocompression-bonded to the terminal electrode 77 without supplying a flux.
8 to obtain a desired mounting structure.
【００４５】ここで、図８に示すように、熱圧着実装時
には先に実装荷重（図８（ａ））が作用し、後から熱
（図８（ｂ））が作用することが望ましい。なぜなら、
先に実装荷重が作用することにより、半田７２と半導体
装置７６の端子電極７７の距離がより縮まるので、後か
ら作用する熱で封止樹脂７１が硬化するときに、同時に
短時間で半田７２と端子電極７７の界面で拡散が進み、
金属間化合物７８が生成され、より安定な接続が得られ
るからである。しかも実装後はフラックスの洗浄がいら
ない。また、従来の異方性導電膜（ＡＣＦ）などに比べ
て低荷重実装が可能になり、セラミック基板でも安定な
接続が得られる。Here, as shown in FIG. 8, it is desirable that a mounting load (FIG. 8A) acts first during thermocompression bonding, and that heat (FIG. 8B) acts later. Because
When the mounting load is applied first, the distance between the solder 72 and the terminal electrode 77 of the semiconductor device 76 is further reduced. Therefore, when the sealing resin 71 is hardened by the heat applied later, the solder 72 and the solder 72 are simultaneously set in a short time. Diffusion proceeds at the interface of the terminal electrode 77,
This is because the intermetallic compound 78 is generated, and a more stable connection can be obtained. Moreover, no flux cleaning is required after mounting. Further, mounting with a lower load is possible as compared with a conventional anisotropic conductive film (ACF) or the like, and a stable connection can be obtained even with a ceramic substrate.
【００４６】なお、図では封止樹脂７１中に気泡は存在
していないが、気泡を含んでいても問題ない。これによ
りむしろ高周波特性に有利な構造とすることができる。
さらに、気泡の量は、封止樹脂７１が反応して硬化する
ときに気泡を発生させるような成分、例えば反応性希釈
剤などの量を制御することにより変えることができる。Although no air bubbles are present in the sealing resin 71 in the drawing, there is no problem if air bubbles are included. Thereby, a structure more advantageous for high frequency characteristics can be obtained.
Furthermore, the amount of bubbles can be changed by controlling the amount of a component that generates bubbles when the sealing resin 71 reacts and cures, for example, a reactive diluent.
【００４７】半田の材料としては、例えばＡｕ、Ａｌ、
Ｐｄ、Ｐｂ、Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔｉ、Ｎｉ、Ｃ
ｒ、Ａｇ、Ｐｔ、Ｓｂの少なくとも１種を用いることが
できる。また、封止樹脂７１としては、エポキシ系樹脂
を主成分として含み、ＳｉＯ 2やＡｌ2Ｏ3、ＳｉＮなど
の無機物の粒子だけを含んだ絶縁樹脂を用いることがで
きる。含まれる粒子は無機物であれば何でもよい。As the material of the solder, for example, Au, Al,
Pd, Pb, Sn, Cu, In, Bi, Ti, Ni, C
It is possible to use at least one of r, Ag, Pt, and Sb.
it can. Also, as the sealing resin 71, an epoxy resin
Containing as a main component SiO 2 TwoAnd AlTwoOThree, SiN, etc.
Insulation resin containing only inorganic particles can be used
Wear. The contained particles may be any inorganic particles.
【００４８】（実施の形態８）図９は、本発明の実施の
形態８にかかる実装構造の製造方法を示す概略断面図で
ある。図９（ａ）に示すように、半導体装置８６の端子
電極８７上に半田８２を設ける。回路基板８４上には、
封止樹脂８１（液状または樹脂膜）を供給する。ここで
封止樹脂８１は、回路基板８４の入出力端子電極８３を
覆っていても、覆っていなくてもよい。ただし、半導体
装置８６が実装される領域の少なくとも一部に供給され
ている。そして、半田８２が入出力端子電極８３に当接
するように、半導体装置８６を回路基板８４上に載置す
る。次に、図９（ｂ）に示すように、フラックスを供給
することなく、半田８２を入出力端子電極８３と熱圧着
させ、それにより、界面に金属化合物８８を形成して所
望の実装構造を得る。(Eighth Embodiment) FIG. 9 is a schematic sectional view showing a method of manufacturing a mounting structure according to an eighth embodiment of the present invention. As shown in FIG. 9A, a solder 82 is provided on a terminal electrode 87 of a semiconductor device 86. On the circuit board 84,
The sealing resin 81 (liquid or resin film) is supplied. Here, the sealing resin 81 may or may not cover the input / output terminal electrodes 83 of the circuit board 84. However, it is supplied to at least a part of a region where the semiconductor device 86 is mounted. Then, the semiconductor device 86 is mounted on the circuit board 84 so that the solder 82 contacts the input / output terminal electrode 83. Next, as shown in FIG. 9B, the solder 82 is thermocompression-bonded to the input / output terminal electrode 83 without supplying a flux, whereby a metal compound 88 is formed at the interface to form a desired mounting structure. obtain.
【００４９】ここで、熱圧着実装時には、図１０に示す
ように、先に実装荷重（図１０（ａ））が作用し、後か
ら熱（図１０（ｂ））が作用することが望ましい。なぜ
なら先に実装荷重が作用することにより、半田８２と回
路基板８４の入出力端子電極８３の距離がより縮まるの
で、後から作用する熱で封止樹脂８１が硬化するとき
に、同時に短時間で半田８２と入出力端子電極８３の界
面で拡散が進み、金属間化合物８８が生成され、より安
定な接続が得られるからである。しかも実装後はフラッ
クスの洗浄がいらない。また、従来の異方性導電膜（Ａ
ＣＦ）などに比べて低荷重実装が可能になり、セラミッ
ク基板でも安定な接続が得られる。Here, at the time of thermocompression bonding, as shown in FIG. 10, it is desirable that a mounting load (FIG. 10A) acts first and heat (FIG. 10B) acts later. Because the mounting load acts first, the distance between the solder 82 and the input / output terminal electrodes 83 of the circuit board 84 is further reduced. This is because diffusion proceeds at the interface between the solder 82 and the input / output terminal electrode 83, and the intermetallic compound 88 is generated, so that a more stable connection can be obtained. Moreover, no flux cleaning is required after mounting. In addition, a conventional anisotropic conductive film (A
CF) and the like can be mounted with a lower load, and a stable connection can be obtained even with a ceramic substrate.
【００５０】なお、図では封止樹脂８１中に気泡は存在
していないが、気泡を含んでいても問題ない。これによ
りむしろ高周波特性に有利な構造とすることができる。
さらに、気泡の量は、封止樹脂が反応して硬化するとき
に気泡を発生させるような成分、例えば反応性希釈剤な
どの量を制御することにより変えることができる。半田
８２の材料そしては、例えばＡｕ、Ａｌ、Ｐｄ、Ｐｂ、
Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔｉ、Ｎｉ、Ｃｒ、Ａｇ、Ｐ
ｔ、Ｓｂの少なくとも１種を用いることができる。ま
た、封止樹脂８１としては、エポキシ系樹脂を主成分と
して含み、ＳｉＯ 2やＡｌ2Ｏ3、ＳｉＮなどの無機物の
粒子だけを含んだ絶縁樹脂を用いることができる。含ま
れる粒子は無機物であれば何でもよい。In the figure, bubbles are present in the sealing resin 81.
No, but it does not matter if it contains air bubbles. This
Rather, a structure advantageous for high frequency characteristics can be obtained.
In addition, the amount of air bubbles is determined when the sealing resin reacts and cures.
Components that generate air bubbles, such as reactive diluents
It can be varied by controlling which amount. solder
82, and for example, Au, Al, Pd, Pb,
Sn, Cu, In, Bi, Ti, Ni, Cr, Ag, P
At least one of t and Sb can be used. Ma
The sealing resin 81 is mainly composed of an epoxy resin.
As SiO TwoAnd AlTwoOThreeOf inorganic substances such as SiN
An insulating resin containing only particles can be used. Included
The particles to be formed may be any inorganic materials.
【００５１】（実施の形態９）図１１〜１３は、本発明
の実施の形態９にかかる回路基板の製造方法を示す概略
断面図である。まず図１１（ａ）に示すように樹脂膜９
１（フィルム）上に剥離シート９５が接着された部材を
用意する。次に剥離シート９５のついた樹脂膜９１を、
回路基板９４上に載置し、熱を作用させることにより少
なくとも回路基板９４の入出力端子電極９３上の接続さ
れる部分を覆うように接着させる（図１１（ｂ））。Ninth Embodiment FIGS. 11 to 13 are schematic sectional views showing a method for manufacturing a circuit board according to a ninth embodiment of the present invention. First, as shown in FIG.
A member having a release sheet 95 bonded to 1 (film) is prepared. Next, the resin film 91 with the release sheet 95 is
It is mounted on the circuit board 94 and is bonded by heat so as to cover at least a portion of the circuit board 94 to be connected to the input / output terminal electrodes 93 (FIG. 11B).
【００５２】次に図１２（ｃ）に示すように、樹脂膜９
１及び剥離シート９５の入出力端子電極９３上にある必
要部位に穴９６をあける。穴９６をあけるには、レーザ
ーを用いてもよいし、紫外線を用いてもよい。レーザー
を用いる場合は、樹脂膜９１及び剥離シート９５として
は、一般的などのような樹脂でも用いることができる。
剥離シート９５の場合は、剥離性を有する材料であるこ
とを要するが、テフロン（登録商標）、セロハン、ＰＥ
Ｔ（ポリエチレンテレフタレート）などを用いることが
できる。紫外線を用いる場合は、樹脂膜９１及び剥離シ
ート９５としては、感光性のある樹脂を用いる。紫外線
に感光性のある樹脂であれば特に限定されないが、主
に、紫外線硬化型のエポキシ樹脂、アクリル樹脂などを
用いることができる。Next, as shown in FIG.
A hole 96 is made in a required portion of the release sheet 95 on the input / output terminal electrode 93. To make the holes 96, a laser or ultraviolet light may be used. When a laser is used, any common resin can be used as the resin film 91 and the release sheet 95.
In the case of the release sheet 95, it is necessary that the release sheet 95 be a material having releasability, but Teflon (registered trademark), cellophane, PE
T (polyethylene terephthalate) or the like can be used. When ultraviolet rays are used, a photosensitive resin is used for the resin film 91 and the release sheet 95. The resin is not particularly limited as long as it is a resin that is sensitive to ultraviolet light, but mainly an ultraviolet-curable epoxy resin, an acrylic resin, or the like can be used.
【００５３】次に図１２（ｄ）に示すように、スキージ
９９で半田９２を穴９６に埋め込む。図１３（ｅ）に示
すように半田９２を穴９６に充填した後、剥離シート９
５をはがす（図１３（ｆ））。その後、半田をリフロー
溶融させる（図１３（ｇ））。Next, as shown in FIG. 12D, the solder 92 is embedded in the hole 96 with a squeegee 99. After the solder 92 is filled in the holes 96 as shown in FIG.
5 is removed (FIG. 13 (f)). Thereafter, the solder is reflow-melted (FIG. 13 (g)).
【００５４】以上のようにして、半田９２とそれをとり
かこむ樹脂膜９１を有する回路基板９４が得られる。As described above, a circuit board 94 having the solder 92 and the resin film 91 surrounding the solder 92 is obtained.
【００５５】半田９２としては、例えばＡｕ、Ａｌ、Ｐ
ｄ、Ｐｂ、Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔｉ、Ｎｉ、Ｃ
ｒ、Ａｇ、Ｐｔ、Ｓｂの少なくとも１種を用いることが
できる。また、樹脂膜９１としては、エポキシ系樹脂を
主成分として含み、ＳｉＯ2やＡｌ2Ｏ3、ＳｉＮなどの
無機物の粒子だけを含んだ絶縁膜を用いることができ
る。含まれる粒子は無機物であれば何でもよい。As the solder 92, for example, Au, Al, P
d, Pb, Sn, Cu, In, Bi, Ti, Ni, C
At least one of r, Ag, Pt, and Sb can be used. Further, as the resin film 91, an insulating film containing an epoxy resin as a main component and containing only inorganic particles such as SiO 2 , Al 2 O 3 , and SiN can be used. The contained particles may be any inorganic materials.
【００５６】（実施の形態１０）図１４〜１６は、本発
明の実施の形態１０にかかる回路基板の製造方法を示す
の概略断面図である。まず図１４（ａ）に示すように、
樹脂膜１０１（フィルム）上に剥離シート１０５が接着
された部材を用意する。次に剥離シート１０５のついた
樹脂膜１０１を回路基板１０４上に載置し、熱を作用さ
せることにより少なくとも回路基板１０４の入出力端子
電極１０３上の接続される部分を覆うように接着させる
（図１４（ｂ））。(Embodiment 10) FIGS. 14 to 16 are schematic sectional views showing a method of manufacturing a circuit board according to Embodiment 10 of the present invention. First, as shown in FIG.
A member in which a release sheet 105 is adhered to a resin film 101 (film) is prepared. Next, the resin film 101 with the release sheet 105 is placed on the circuit board 104, and is heated so as to adhere so as to cover at least a portion of the circuit board 104 connected to the input / output terminal electrodes 103 ( FIG. 14 (b)).
【００５７】次に図１５（ｃ）に示すように、樹脂膜１
０１及び剥離シート１０５の入出力端子電極１０３上に
ある必要部位に穴１０６をあける。穴１０６をあけるに
は、レーザーを用いてもよいし、紫外線を用いてもよ
い。レーザーを用いる場合には、樹脂膜１０１及び剥離
シート１０５は一般的などのような樹脂でも用いること
ができる。剥離シート１０５の場合は、剥離性を有する
ことを要するが、テフロン、セロハン、ＰＥＴ（ポリエ
チレンテレフタレート）などを用いることができる。紫
外線を用いる場合は、樹脂膜１０１及び剥離シート１０
５には感光性のある樹脂を用いる。紫外線に感光性のあ
る樹脂であれば特に限定されないが、主に、紫外線硬化
型のエポキシ樹脂、アクリル樹脂などを用いることがで
きる。Next, as shown in FIG.
A hole 106 is formed in a necessary portion of the release sheet 01 and the input / output terminal electrode 103 of the release sheet 105. A laser may be used to form the hole 106, or ultraviolet light may be used. When a laser is used, the resin film 101 and the release sheet 105 can be made of any general resin. In the case of the release sheet 105, it is necessary to have releasability, but Teflon, cellophane, PET (polyethylene terephthalate), or the like can be used. When ultraviolet rays are used, the resin film 101 and the release sheet 10
For 5, a photosensitive resin is used. The resin is not particularly limited as long as it is a resin that is sensitive to ultraviolet light, but mainly an ultraviolet-curable epoxy resin, an acrylic resin, or the like can be used.
【００５８】次に図１５（ｄ）に示すように、板１０７
上に形成した半田ボール１０２を穴１０６に載置する。
板１０７の表面は、半田ボール１０２が球状になるよう
にＣｒ（クロム）などで被覆しており、フラックスの粘
着性を利用して半田ボール１０２をつけておく。図１６
（ｅ）に示すように半田ボール１０２が載置された後、
半田をリフロー溶融する（図１６（ｆ））。その後、剥
離シート１０５をはがす（図１６（ｇ））。Next, as shown in FIG.
The solder ball 102 formed above is placed in the hole 106.
The surface of the plate 107 is coated with Cr (chromium) or the like so that the solder ball 102 becomes spherical, and the solder ball 102 is attached using the adhesiveness of the flux. FIG.
After the solder ball 102 is placed as shown in FIG.
The solder is reflow-melted (FIG. 16 (f)). Thereafter, the release sheet 105 is peeled off (FIG. 16 (g)).
【００５９】以上の様にして、半田１０２とそれを取り
囲む樹脂膜１０１を有する回路基板１０４が得られる。As described above, a circuit board 104 having the solder 102 and the resin film 101 surrounding the solder 102 is obtained.
【００６０】半田１０２としては、例えばＡｕ、Ａｌ、
Ｐｄ、Ｐｂ、Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔｉ、Ｎｉ、Ｃ
ｒ、Ａｇ、Ｐｔ、Ｓｂの少なくとも１種を用いることが
できる。また、樹脂膜１０１としては、エポキシ系樹脂
を主成分として含み、ＳｉＯ 2やＡｌ2Ｏ3、ＳｉＮなど
の無機物の粒子だけを含んだ絶縁膜を用いることができ
る。含まれる粒子は無機物であれば何でもよい。As the solder 102, for example, Au, Al,
Pd, Pb, Sn, Cu, In, Bi, Ti, Ni, C
It is possible to use at least one of r, Ag, Pt, and Sb.
it can. Further, as the resin film 101, an epoxy resin
Containing as a main component SiO 2 TwoAnd AlTwoOThree, SiN, etc.
Insulation film containing only inorganic particles can be used
You. The contained particles may be any inorganic particles.
【００６１】[0061]
【実施例】図９、１０に示した実施の形態８の方法によ
り実装を行った結果を図１７に示す。基板にはセラミッ
ク基板を用いた。端子電極にはＰｂ−Ｓｎの半田を用い
た。セラミック基板上の入出力端子電極は、ＡｇＰｔペ
ーストを印刷・焼成して作製した。EXAMPLE FIG. 17 shows the result of mounting according to the method of the eighth embodiment shown in FIGS. A ceramic substrate was used as the substrate. Pb-Sn solder was used for the terminal electrodes. The input / output terminal electrodes on the ceramic substrate were produced by printing and baking AgPt paste.
【００６２】図１７（ａ）には各実装荷重に対する初期
接続の結果を示す（樹脂膜使用）。実装後は、リフロー
（２３０〜２４０℃を１０ｓｅｃ以上キープ）を通して
いる。実装荷重５０／ｂｕｍｐ以上でリフロー後でも抵
抗値が安定であることが判明した。（ｂ）には５０ｇ／
ｂｕｍｐの実装荷重で、それぞれ樹脂膜と封止樹脂（液
状）を用いて実装した場合の初期特性の結果を示す。い
ずれの場合もリフロー後でも初期接続は安定している。
このことから、フラックスを使用せず、熱圧着実装する
ことで十分安定な接続が得られることがわかる。FIG. 17A shows the results of initial connection for each mounting load (using a resin film). After mounting, reflow (keep 230-240 ° C. for 10 seconds or more) is performed. It was found that the resistance value was stable even after reflow at a mounting load of 50 / bump or more. (B) has 50g /
The results of initial characteristics when mounting is performed using a resin film and a sealing resin (liquid) with a mounting load of bump, respectively. In any case, the initial connection is stable even after reflow.
From this, it can be seen that a sufficiently stable connection can be obtained by performing thermocompression mounting without using a flux.
【００６３】また、それらの作製したサンプルについ
て、半田耐熱試験（２７０〜２８０℃で１０ｓｅｃ以上
キープを５サイクル）を行った結果を（ｃ）に、温度特
性（室温〜１５０℃まで）を行った結果を（ｄ）に、熱
衝撃試験（−４０〜１２５℃）に投入した結果を（ｅ）
に示す。これらの結果から、実装荷重５０ｇ／ｂｕｍｐ
で十分な信頼性が確保されていることもわかった。これ
は従来の異方性導電膜（ＡＣＦ）を用いた実装結果と比
べても、より小さい実装荷重で安定な接続が得られるこ
とを示している。また、（ｆ）には実装荷重３０ｇ／ｂ
ｕｍｐの場合の接続部の断面を示す（フィルム使用）。The temperature characteristics (from room temperature to 150 ° C.) were obtained by performing the soldering heat test (5 cycles of keeping at 270 to 280 ° C. for 10 seconds or more) on the prepared samples. (D) shows the results and (e) shows the results of the thermal shock test (-40 to 125 ° C.).
Shown in From these results, the mounting load was 50 g / bump.
It was also found that sufficient reliability was secured. This indicates that a stable connection can be obtained with a smaller mounting load as compared with a mounting result using a conventional anisotropic conductive film (ACF). (F) shows a mounting load of 30 g / b.
The cross section of the connection part in the case of Ump is shown (using a film).
【００６４】[0064]
【発明の効果】本発明によれば、実装時にフラックスを
供給することなく、半田を熱と荷重を併用して実装する
ことで、界面に金属化合物を形成することにより、接触
によるよりもより低抵抗で信頼性の高い接続が可能であ
る。また実装荷重も小さくてすみ、高生産に適した熱圧
着実装が可能になる。さらに接続部を補強する樹脂に空
気を発生する成分を含ませることにより、実装構造に気
泡を含み高周波特性にも優れた構造を実現できる。According to the present invention, the solder is mounted by using both heat and load without supplying a flux at the time of mounting, thereby forming a metal compound at the interface, thereby lowering the soldering temperature than by contact. A highly reliable connection is possible with a resistor. In addition, the mounting load can be reduced, and thermocompression bonding suitable for high production can be performed. Furthermore, by including a component that generates air in the resin that reinforces the connection portion, a structure that includes bubbles in the mounting structure and has excellent high-frequency characteristics can be realized.
【図１】 本発明の実施の形態１にかかる実装構造の概
略断面図FIG. 1 is a schematic cross-sectional view of a mounting structure according to a first embodiment of the present invention.
【図２】 本発明の実施の形態２にかかる実装構造の概
略断面図FIG. 2 is a schematic sectional view of a mounting structure according to a second embodiment of the present invention;
【図３】 本発明の実施の形態３にかかる回路基板の概
略断面図FIG. 3 is a schematic sectional view of a circuit board according to a third embodiment of the present invention;
【図４】 本発明の実施の形態４にかかる半導体装置の
概略断面図FIG. 4 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the present invention;
【図５】 本発明の実施の形態５にかかる実装構造の製
造方法を示す概略断面図FIG. 5 is a schematic cross-sectional view illustrating a method of manufacturing a mounting structure according to a fifth embodiment of the present invention.
【図６】 本発明の実施の形態６にかかる実装構造の製
造方法を示す概略断面図FIG. 6 is a schematic cross-sectional view illustrating a method of manufacturing a mounting structure according to a sixth embodiment of the present invention.
【図７】 本発明の実施の形態７にかかる実装構造の製
造方法を示す概略断面図FIG. 7 is a schematic cross-sectional view illustrating a method of manufacturing a mounting structure according to a seventh embodiment of the present invention.
【図８】 本発明の実施の形態７にかかる実装構造の製
造方法を示すグラフFIG. 8 is a graph showing a method for manufacturing a mounting structure according to a seventh embodiment of the present invention;
【図９】 本発明の実施の形態８にかかる実装構造の製
造方法を示す概略断面図FIG. 9 is a schematic cross-sectional view showing a method of manufacturing a mounting structure according to an eighth embodiment of the present invention.
【図１０】 本発明の実施の形態８にかかる実装構造の
製造方法を示すグラフFIG. 10 is a graph showing a method for manufacturing a mounting structure according to an eighth embodiment of the present invention;
【図１１】 本発明の実施の形態９にかかる回路基板の
製造方法を示す概略断面図FIG. 11 is a schematic sectional view illustrating a method for manufacturing a circuit board according to a ninth embodiment of the present invention.
【図１２】 図１１に続く工程を示す概略断面図FIG. 12 is a schematic sectional view showing a step following FIG. 11;
【図１３】 図１２に続く工程を示す概略断面図FIG. 13 is a schematic sectional view showing a step following FIG. 12;
【図１４】 本発明の実施の形態１０にかかる回路基板
の製造方法の概略断面図FIG. 14 is a schematic sectional view of a method for manufacturing a circuit board according to a tenth embodiment of the present invention;
【図１５】 図１４に続く工程を示す概略断面図FIG. 15 is a schematic sectional view showing a step following FIG. 14;
【図１６】 図１５に続く工程を示す概略断面図FIG. 16 is a schematic sectional view showing a step following FIG. 15;
【図１７】 本発明の実施例における熱圧着実装の結果
による各特性を示すグラフ（ａ〜ｅ）と接続部断面写真
を示す図（ｆ）FIG. 17 is a graph (a) showing each characteristic according to the result of thermocompression bonding in the embodiment of the present invention and a diagram (f) showing a photograph of a cross section of a connection portion;
【図１８】 従来の半田バンプを示す概略断面図FIG. 18 is a schematic sectional view showing a conventional solder bump.
【図１９】 従来の異方性導電膜（ＡＣＦ）を用いた実
装方法を示す概略断面図FIG. 19 is a schematic cross-sectional view showing a mounting method using a conventional anisotropic conductive film (ACF).
【図２０】 従来の異方性導電膜（ＡＣＦ）を用いて実
装した場合の結果による各特性を示すグラフFIG. 20 is a graph showing each characteristic based on a result of mounting using a conventional anisotropic conductive film (ACF).
【図２１】 従来の異方性導電膜（ＡＣＦ）を用いて実
装した場合の接続部断面写真を示す図FIG. 21 is a view showing a photograph of a cross section of a connection portion when mounting is performed using a conventional anisotropic conductive film (ACF).
１０、２０ 気泡 １１、２１、７１、８１ 封止樹脂 １２、２２、３２、４２、５２、６２、７２、８２、９
２、１０２ 半田 １３、２３、３３、５３、６３、７３、８３、９３、１
０３ 入出力端子電極 １４、２４、３４、５４、６４、７４、８４、９４、１
０４ 回路基板 １６、２６、４６、５６、６６、７６、８６ 半導体装
置 １７、２７、４７、５７、６７、７７、８７ 端子電極 １８、２８、５８、６８、７８、８８ 金属間化合物 ３１、４１、５１、６１、９１、１０１ 樹脂膜 ９５、１０５ 剥離シート ９９ スキージ １０９ 板（表面Ｃｒ処理） １１１ Ｐｂ−Ｓｎ半田 １１２ Ｃｕ−Ｓｎ金属間化合物 １１３ Ｃｒ−Ｃｕ １１４ Ｃｒ １１５ Ａｌ １１６ ガラス保護膜 １１７ ＳｉＯ2膜 １１８ ＩＣ基板 １２１ 基板１ １２２ 電極１ １２３ 導電粒子 １２４ 接着剤 １２５ 電極２ １２６ 基板２10, 20 Bubbles 11, 21, 71, 81 Sealing resin 12, 22, 32, 42, 52, 62, 72, 82, 9
2,102 Solder 13,23,33,53,63,73,83,93,1,1
03 input / output terminal electrodes 14, 24, 34, 54, 64, 74, 84, 94, 1
04 circuit board 16, 26, 46, 56, 66, 76, 86 semiconductor device 17, 27, 47, 57, 67, 77, 87 terminal electrode 18, 28, 58, 68, 78, 88 intermetallic compound 31, 41 , 51, 61, 91, 101 Resin film 95, 105 Release sheet 99 Squeegee 109 Board (Surface Cr treatment) 111 Pb-Sn solder 112 Cu-Sn intermetallic compound 113 Cr-Cu 114 Cr 115 Al 116 Glass protective film 117 SiO 2 film 118 IC substrate 121 substrate 1 122 electrode 1 123 conductive particles 124 adhesive 125 electrode 2 126 substrate 2
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小島 俊之 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5F044 KK01 KK18 KK19 LL04 QQ03 QQ04 QQ06 RR19 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Toshiyuki Kojima 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5F044 KK01 KK18 KK19 LL04 QQ03 QQ04 QQ06 RR19
Claims (21)
子電極を有する回路基板上に実装した実装構造であっ
て、 前記端子電極と前記入出力端子電極の間が、前記入出力
端子電極上に設けられた半田、および前記半田と前記端
子電極の界面に形成された金属間化合物により接続さ
れ、少なくとも前記半田と前記金属間化合物の周囲が封
止樹脂に囲まれて前記接続が補強され、前記金属間化合
物は、前記半田と前記端子電極が熱圧着されたときに形
成されたものであることを特徴とする実装構造。1. A mounting structure in which a semiconductor device having a terminal electrode is mounted on a circuit board having an input / output terminal electrode, wherein a space between the terminal electrode and the input / output terminal electrode is provided on the input / output terminal electrode. The provided solder, and connected by an intermetallic compound formed at the interface between the solder and the terminal electrode, at least the periphery of the solder and the intermetallic compound is surrounded by a sealing resin to reinforce the connection, The mounting structure, wherein the intermetallic compound is formed when the solder and the terminal electrode are thermocompression-bonded.
子電極を有する回路基板上に実装した実装構造であっ
て、 前記端子電極と前記入出力端子電極の間が、前記端子電
極上に設けられた半田、および前記半田と前記入出力端
子電極の界面に形成された金属間化合物により接続さ
れ、少なくとも前記半田と前記金属間化合物の周囲が封
止樹脂に囲まれて前記接続が補強され、前記金属間化合
物は、前記半田と前記入出力端子電極が熱圧着されたと
きに形成されたものであることを特徴とする実装構造。2. A mounting structure in which a semiconductor device having a terminal electrode is mounted on a circuit board having an input / output terminal electrode, wherein a space between the terminal electrode and the input / output terminal electrode is provided on the terminal electrode. Solder, and connected by an intermetallic compound formed at the interface between the solder and the input / output terminal electrode, at least the periphery of the solder and the intermetallic compound is surrounded by a sealing resin to reinforce the connection, The mounting structure, wherein the intermetallic compound is formed when the solder and the input / output terminal electrode are thermocompression-bonded.
入出力端子電極上に半田が形成され、少なくとも前記半
田を取り囲むように前記基板表面に樹脂膜が設けられ、
前記樹脂膜の厚さが前記半田の高さ以下であることを特
徴とする回路基板。3. An input / output terminal electrode is provided on a substrate surface, solder is formed on the input / output terminal electrode, and a resin film is provided on at least the substrate surface so as to surround the solder.
A circuit board, wherein the thickness of the resin film is equal to or less than the height of the solder.
に半田が形成され、少なくとも前記半田を取り囲むよう
に前記表面に樹脂膜が設けられ、前記樹脂膜の厚さが前
記半田の高さ以下であることを特徴とする半導体装置。4. A terminal having a terminal electrode on a surface thereof, a solder formed on the terminal electrode, a resin film provided on the surface so as to surround at least the solder, and a thickness of the resin film being higher than that of the solder. A semiconductor device, characterized by:
子電極を有する回路基板に実装するための製造方法であ
って、 前記入出力端子電極上に半田が形成され、少なくとも前
記半田の周囲の表面部に樹脂膜が設けられて、前記樹脂
膜の厚さが前記半田の高さ以下である回路基板を用い、 前記半導体装置を、前記端子電極が前記半田に対向する
ように前記回路基板上に載置して熱圧着を施すことによ
り、まず前記半田が前記端子電極に接触して界面に金属
間化合物を形成し、その後溶けた前記樹脂膜が少なくと
も前記半田及び前記金属間化合物の周囲を取り囲むこと
を特徴とする実装構造の製造方法。5. A manufacturing method for mounting a semiconductor device having a terminal electrode on a circuit board having an input / output terminal electrode, wherein solder is formed on the input / output terminal electrode, and at least a surface around the solder. A resin film is provided on the portion, and a circuit board having a thickness of the resin film equal to or less than the height of the solder is used. The semiconductor device is placed on the circuit board such that the terminal electrodes face the solder. By placing and performing thermocompression bonding, first, the solder contacts the terminal electrode to form an intermetallic compound at the interface, and then the melted resin film surrounds at least the periphery of the solder and the intermetallic compound. A method for manufacturing a mounting structure, comprising:
子電極を有する回路基板に実装するための製造方法であ
って、 前記端子電極上に半田が形成され、少なくとも前記半田
の周囲の表面部に樹脂膜が設けられて、前記樹脂膜の厚
さが前記半田の高さ以下である半導体装置を用い、 前記半導体装置を、前記半田が前記入出力端子電極に対
向するように前記回路基板上に載置して熱圧着を施すこ
とにより、まず前記半田が前記入出力端子電極に接触し
て界面に前記金属間化合物を形成し、その後溶けた前記
樹脂膜が少なくとも前記半田及び前記金属間化合物の周
囲を取り囲むことを特徴とする実装構造の製造方法。6. A manufacturing method for mounting a semiconductor device having a terminal electrode on a circuit board having an input / output terminal electrode, wherein solder is formed on the terminal electrode and at least a surface portion around the solder is provided. A resin film is provided, and a semiconductor device having a thickness of the resin film equal to or less than the height of the solder is used. The semiconductor device is placed on the circuit board such that the solder faces the input / output terminal electrode. By placing and performing thermocompression bonding, first, the solder contacts the input / output terminal electrode to form the intermetallic compound at the interface, and then the melted resin film has at least the solder and the intermetallic compound. A method for manufacturing a mounting structure, which surrounds the periphery.
子電極を有する回路基板に実装するための製造方法であ
って、 前記入出力端子電極上に半田が形成され、前記半導体装
置が実装される領域の少なくとも一部に封止樹脂が供給
された回路基板を用い、 前記半導体装置を、前記端子電極が前記半田に対向する
ように前記回路基板上に載置して熱圧着を施すことによ
り、前記半田が前記端子電極に到達して界面に金属間化
合物を形成し、前記封止樹脂が少なくとも前記半田及び
前記金属間化合物を取り囲んで補強することを特徴とす
る実装構造の製造方法。7. A manufacturing method for mounting a semiconductor device having terminal electrodes on a circuit board having input / output terminal electrodes, wherein solder is formed on the input / output terminal electrodes, and the semiconductor device is mounted. By using a circuit board in which a sealing resin is supplied to at least a part of the region, the semiconductor device is placed on the circuit board so that the terminal electrodes face the solder and subjected to thermocompression bonding. The method of manufacturing a mounting structure, wherein the solder reaches the terminal electrode to form an intermetallic compound at an interface, and the sealing resin surrounds and reinforces at least the solder and the intermetallic compound.
子電極を有する回路基板に実装するための製造方法であ
って、 前記入出力端子電極上に半田が形成された半導体装置
と、前記半導体装置が実装される領域の少なくとも一部
に封止樹脂が供給された回路基板とを用い、 前記半導体装置を、前記半田が前記入出力端子電極に対
向するように前記回路基板上に載置して熱圧着を施すこ
とにより、前記半田が前記入出力端子電極に到達して界
面に金属間化合物を形成し、前記封止樹脂が少なくとも
前記半田及び前記金属間化合物を取り囲んで補強するこ
とを特徴とする実装構造の製造方法。8. A manufacturing method for mounting a semiconductor device having a terminal electrode on a circuit board having an input / output terminal electrode, the semiconductor device having solder formed on the input / output terminal electrode; And a circuit board in which a sealing resin is supplied to at least a part of a region where the semiconductor device is mounted, and the semiconductor device is placed on the circuit board so that the solder faces the input / output terminal electrodes. By performing thermocompression bonding, the solder reaches the input / output terminal electrode to form an intermetallic compound at the interface, and the sealing resin surrounds at least the solder and the intermetallic compound and reinforces it. Method of manufacturing the mounting structure.
を少なくとも設定された大きさに到達させて保持した状
態で、次に設定された温度まで熱を作用させることを特
徴とする請求項７または８記載の実装構造の製造方法。9. The method according to claim 1, wherein when the thermocompression bonding is performed, heat is applied to a next set temperature in a state where the mounting load reaches at least a set size and is held. 9. The method for manufacturing the mounting structure according to 7 or 8.
の入出力端子電極上の少なくとも実装領域を含む部分に
前記剥離シートを表面にして接着する工程と、前記剥離
シートと前記樹脂膜に穴をあける工程と、前記穴に半田
を埋め込む工程と、前記剥離シートを除去する工程と、
前記半田を溶融する工程とを有することを特徴とする回
路基板の製造方法。10. A step of bonding a resin film having a release sheet to a portion including at least a mounting area on an input / output terminal electrode of a circuit board with the release sheet as a surface, and forming a hole in the release sheet and the resin film. Drilling step, a step of embedding solder in the hole, a step of removing the release sheet,
Melting the solder.
の入出力端子電極上の少なくとも実装領域を含む部分に
前記剥離シートを表面にして接着する工程と、前記剥離
シートと前記樹脂膜に穴をあける工程と、前記穴に転写
により半田を搭載する工程と、前記半田を溶融する工程
と、前記剥離シートを除去する工程とを有することを特
徴とする回路基板の製造方法。11. A step of bonding a resin film having a release sheet to a portion including at least a mounting region on an input / output terminal electrode of a circuit board with the release sheet as a surface, and forming a hole in the release sheet and the resin film. A method for manufacturing a circuit board, comprising: a step of punching; a step of mounting solder in the hole by transfer; a step of melting the solder; and a step of removing the release sheet.
とを特徴とする請求項１または２記載の実装構造。12. The mounting structure according to claim 1, wherein bubbles are present in the sealing resin.
泡を発生させる成分を含むことを特徴とする請求項７ま
たは８記載の実装構造の製造方法。13. The method according to claim 7, wherein the material of the sealing resin includes a component that generates bubbles during thermocompression bonding.
ｂ、Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔｉ、Ｎｉ、Ｃｒ、Ａ
ｇ、Ｐｔ、及びＳｂから選ばれた少なくとも１種を含む
ことを特徴とする請求項１または２記載の実装構造、も
しくは請求項５〜９のいずれか１項記載の実装構造の製
造方法。14. The solder is made of Au, Al, Pd, P
b, Sn, Cu, In, Bi, Ti, Ni, Cr, A
The method for manufacturing a mounting structure according to claim 1, wherein the mounting structure includes at least one selected from g, Pt, and Sb.
ｂ、Ｓｎ、Ｃｕ、Ｉｎ、Ｂｉ、Ｔｉ、Ｎｉ、Ｃｒ、Ａ
ｇ、Ｐｔ、及びＳｂから選ばれた少なくとも１種を含む
ことを特徴とする請求項３記載の回路基板、請求項４記
載の半導体装置、もしくは請求項１０または１１記載の
回路基板の製造方法。15. The solder may be made of Au, Al, Pd, P
b, Sn, Cu, In, Bi, Ti, Ni, Cr, A
The method for manufacturing a circuit board according to claim 3, wherein the circuit board includes at least one selected from the group consisting of g, Pt, and Sb.
成分として含み、無機物の粒子としてＳｉＯ2、Ａｌ2Ｏ
2、ＴｉＯ2、ＢｅＯ、ＭｇＯ、ＣａＯ、ＳｒＯ、Ｂａ
Ｏ、ＮｉＯ、ＣｏＯ、ＺｎＯ、Ｂ2Ｏ3、Ｂｉ2Ｏ3、Ｚｒ
Ｏ2、及びＴｈＯ2から選ばれた少なくとも１種を含んで
いることを特徴とする請求項１または２記載の実装構
造、もしくは請求項７または８記載の実装構造の製造方
法。16. The sealing resin contains an epoxy-based resin as a main component, and contains SiO 2 , Al 2 O as inorganic particles.
2, TiO 2, BeO, MgO , CaO, SrO, Ba
O, NiO, CoO, ZnO, B 2 O 3, Bi 2 O 3, Zr
The mounting structure according to claim 1, wherein the method comprises at least one selected from the group consisting of O 2 and ThO 2 .
分として含み、無機物の粒子としてＳｉＯ2、Ａｌ
2Ｏ2、ＴｉＯ2、ＢｅＯ、ＭｇＯ、ＣａＯ、ＳｒＯ、Ｂ
ａＯ、ＮｉＯ、ＣｏＯ、ＺｎＯ、Ｂ2Ｏ3、Ｂｉ2Ｏ3、Ｚ
ｒＯ2、及びＴｈＯ2から選ばれた少なくとも１種を含ん
でいることを特徴とする請求項５または６記載の実装構
造の製造方法。17. The resin film contains an epoxy resin as a main component, and includes SiO 2 , Al as inorganic particles.
2 O 2 , TiO 2 , BeO, MgO, CaO, SrO, B
aO, NiO, CoO, ZnO, B 2 O 3 , Bi 2 O 3 , Z
7. The method according to claim 5, further comprising at least one selected from the group consisting of rO 2 and ThO 2 .
分として含み、無機物の粒子としてＳｉＯ2、Ａｌ
2Ｏ2、ＴｉＯ2、ＢｅＯ、ＭｇＯ、ＣａＯ、ＳｒＯ、Ｂ
ａＯ、ＮｉＯ、ＣｏＯ、ＺｎＯ、Ｂ2Ｏ3、Ｂｉ2Ｏ3、Ｚ
ｒＯ2、及びＴｈＯ2から選ばれた少なくとも１種を含ん
でいることを特徴とする請求項３記載の回路基板、請求
項４記載の半導体装置、もしくは請求項１０または１１
記載の回路基板の製造方法。18. The resin film contains an epoxy resin as a main component, and contains SiO 2 , Al
2 O 2 , TiO 2 , BeO, MgO, CaO, SrO, B
aO, NiO, CoO, ZnO, B 2 O 3 , Bi 2 O 3 , Z
The circuit board according to claim 3, wherein the circuit board comprises at least one selected from the group consisting of rO 2 and ThO 2.
The method for manufacturing the circuit board according to the above.
工程において、レーザーを用いて穴をあけることを特徴
とする請求項１０または１１記載の回路基板の製造方
法。19. The method for manufacturing a circuit board according to claim 10, wherein in the step of forming holes in the resin film and the release sheet, holes are formed using a laser.
工程において、紫外線で露光することにより穴をあける
ことを特徴とする請求項１０または１１記載の回路基板
の製造方法。20. The method for manufacturing a circuit board according to claim 10, wherein in the step of forming a hole in the resin film and the release sheet, the hole is formed by exposing to ultraviolet light.
んでいることを特徴とする請求項１０または１１記載の
回路基板の製造方法。21. The method according to claim 10, wherein the release sheet contains an epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000272188A JP2002083841A (en) | 2000-09-07 | 2000-09-07 | Mounting structure and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000272188A JP2002083841A (en) | 2000-09-07 | 2000-09-07 | Mounting structure and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002083841A true JP2002083841A (en) | 2002-03-22 |
Family
ID=18758348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000272188A Pending JP2002083841A (en) | 2000-09-07 | 2000-09-07 | Mounting structure and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002083841A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007500455A (en) * | 2003-05-23 | 2007-01-11 | ナショナル スターチ アンド ケミカル インベストメント ホールディング コーポレーション | How to use pre-applied underfill encapsulant |
| JPWO2008050635A1 (en) * | 2006-10-19 | 2010-02-25 | パナソニック株式会社 | Semiconductor element mounting structure and semiconductor element mounting method |
| JP2014082359A (en) * | 2012-10-17 | 2014-05-08 | Olympus Corp | Semiconductor substrate, semiconductor device, solid state image pickup device and semiconductor substrate manufacturing method |
| WO2020159158A1 (en) * | 2019-01-29 | 2020-08-06 | 주식회사 엘지화학 | Method for manufacturing semiconductor package |
| US11527503B2 (en) | 2019-01-29 | 2022-12-13 | Lg Chem, Ltd. | Method for manufacturing semiconductor package |
-
2000
- 2000-09-07 JP JP2000272188A patent/JP2002083841A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007500455A (en) * | 2003-05-23 | 2007-01-11 | ナショナル スターチ アンド ケミカル インベストメント ホールディング コーポレーション | How to use pre-applied underfill encapsulant |
| JPWO2008050635A1 (en) * | 2006-10-19 | 2010-02-25 | パナソニック株式会社 | Semiconductor element mounting structure and semiconductor element mounting method |
| JP5066529B2 (en) * | 2006-10-19 | 2012-11-07 | パナソニック株式会社 | Semiconductor element mounting structure and semiconductor element mounting method |
| JP2014082359A (en) * | 2012-10-17 | 2014-05-08 | Olympus Corp | Semiconductor substrate, semiconductor device, solid state image pickup device and semiconductor substrate manufacturing method |
| WO2020159158A1 (en) * | 2019-01-29 | 2020-08-06 | 주식회사 엘지화학 | Method for manufacturing semiconductor package |
| US11527503B2 (en) | 2019-01-29 | 2022-12-13 | Lg Chem, Ltd. | Method for manufacturing semiconductor package |
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