JPH0766208A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0766208A JPH0766208A JP5212696A JP21269693A JPH0766208A JP H0766208 A JPH0766208 A JP H0766208A JP 5212696 A JP5212696 A JP 5212696A JP 21269693 A JP21269693 A JP 21269693A JP H0766208 A JPH0766208 A JP H0766208A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- semiconductor device
- bump
- melting point
- magnetic material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置およびそ
の製造方法に係わり、特にデバイスの信頼性を向上させ
た半導体装置およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device having improved device reliability and its manufacturing method.
【０００２】[0002]
【従来の技術】図７は、従来の半導体装置を示す断面図
である。実装基板１の表面上には第１のパッド２が設け
られる。半導体チップ３の表面上には第２のパッド４が
設けられ、このパッド４の上にはＰｂ／Ｓｎ等の低融点
金属からなるバンプ５が形成される。2. Description of the Related Art FIG. 7 is a sectional view showing a conventional semiconductor device. The first pad 2 is provided on the surface of the mounting substrate 1. A second pad 4 is provided on the surface of the semiconductor chip 3, and a bump 5 made of a low melting point metal such as Pb / Sn is formed on the pad 4.
【０００３】この後、前記バンプ５が第１のパッド２の
上に位置するように、実装基板１の上には半導体チップ
３が配置される。次に、前記実装基板１及び半導体チッ
プ３の全体を加熱することにより前記低融点金属からな
るバンプ５を溶融させる。これにより、第２のパッド４
は第１のパッド２と接続される。Thereafter, the semiconductor chip 3 is arranged on the mounting substrate 1 so that the bumps 5 are located on the first pads 2. Next, the entire mounting substrate 1 and the semiconductor chip 3 are heated to melt the bumps 5 made of the low melting point metal. As a result, the second pad 4
Is connected to the first pad 2.
【０００４】[0004]
【発明が解決しようとする課題】ところで、上記従来の
バンプによる接続方法では、バンプ５を溶融させる際、
バンプ５のみが加熱されるのではなく、実装基板１及び
半導体チップ３の全体が加熱される。このため、バンプ
５による接続部分以外の箇所における加熱可能な温度の
上限がバンプ３の融点より低い温度である場合は、上記
従来の接続方法を使用することができない。By the way, in the conventional connection method using bumps, when the bumps 5 are melted,
Not only the bump 5 is heated, but the entire mounting substrate 1 and the semiconductor chip 3 are heated. For this reason, when the upper limit of the temperature that can be heated in a portion other than the connection portion by the bump 5 is lower than the melting point of the bump 3, the conventional connection method cannot be used.
【０００５】また、実装基板１及び半導体チップ３の全
体を加熱することによって、バンプ５による接続部分以
外の箇所に熱的な損傷を与えることがある。これによ
り、デバイスの信頼性が低下することがある。Further, heating the entire mounting substrate 1 and the semiconductor chip 3 may cause thermal damage to a portion other than the connecting portion by the bump 5. This may reduce the reliability of the device.
【０００６】また、実装基板１および半導体チップ３の
全体を加熱した後、常温に戻された際、前記実装基板１
と半導体チップ３の熱膨脹係数の差により接続部に大き
な応力や歪みが発生し、この接続部が破壊されることが
ある。したがって、半導体装置の信頼性が低下すること
がある。Further, after the mounting substrate 1 and the semiconductor chip 3 are entirely heated and then returned to room temperature, the mounting substrate 1 is heated.
Due to the difference in the coefficient of thermal expansion between the semiconductor chip 3 and the semiconductor chip 3, a large stress or strain may be generated in the connection portion and the connection portion may be destroyed. Therefore, the reliability of the semiconductor device may decrease.
【０００７】この発明は上記のような事情を考慮してな
されたものであり、その目的は、バンプを集中的に加熱
して溶融させることにより、デバイスの信頼性を向上さ
せた半導体装置およびその製造方法を提供することにあ
る。The present invention has been made in consideration of the above circumstances, and an object thereof is a semiconductor device in which the reliability of the device is improved by intensively heating and melting the bumps and the semiconductor device. It is to provide a manufacturing method.
【０００８】[0008]
【課題を解決するための手段】この発明は、上記課題を
解決するため、実装基板の表面上に形成された第１のパ
ッドと、半導体チップの表面上に形成された第２のパッ
ドと、前記第１のパッドと前記第２のパッドとが接続さ
れた磁性材料と低融点金属とからなるバンプとを具備す
ることを特徴としている。In order to solve the above-mentioned problems, the present invention provides a first pad formed on the surface of a mounting substrate and a second pad formed on the surface of a semiconductor chip. It is characterized in that the first pad and the second pad are connected to each other, and a bump made of a low melting point metal and a magnetic material is provided.
【０００９】また、第１のパッドの上に、第２のパッド
上に設けられた磁性材料と低融点金属とからなるバンプ
を配置する工程と、前記バンプに高周波磁場を与えるこ
とにより、前記第１のパッドと前記第２のパッドとを前
記バンプにより接続する工程とを具備することを特徴と
している。Further, a step of disposing a bump made of a magnetic material and a low melting point metal provided on the second pad on the first pad, and applying a high frequency magnetic field to the bump, And a step of connecting the first pad and the second pad with the bump.
【００１０】また、第１のパッド上に設けられた磁性材
料の上に、第２のパッド上に設けられた低融点金属から
なるバンプを配置する工程と、前記磁性材料に高周波磁
場を与えることにより、前記第１のパッドと前記第２の
パッドとを前記バンプにより接続する工程とを具備する
ことを特徴としている。また、前記磁性材料のキュリ−
温度は、前記低融点金属の融点より２０℃〜５０℃高い
温度であることを特徴としている。Further, a step of disposing a bump made of a low melting point metal provided on the second pad on the magnetic material provided on the first pad, and applying a high frequency magnetic field to the magnetic material. Then, the step of connecting the first pad and the second pad by the bump is provided. In addition, the curry of the magnetic material
The temperature is characterized by being 20 ° C. to 50 ° C. higher than the melting point of the low melting point metal.
【００１１】[0011]
【作用】この発明は、実装基板の表面上に第１のパッド
を形成し、半導体チップの表面上に第２のパッドを形成
し、この第２のパッドの上に磁性材料と低融点金属とか
らなるバンプを設ける。前記第１のパッドの上に前記バ
ンプを配置し、このバンプに高周波磁場を与えることに
より、前記磁性材料を発熱させ、この熱により前記低融
点金属を溶融している。したがって、バンプを集中的に
加熱することができ、このバンプによる接続部以外の箇
所が加熱されることがない。このため、前記接続部以外
の箇所に熱的な損傷を与えることがないから、前記接続
部以外の箇所において熱による劣化を防止することがで
きる。また、前記接続部を加熱した後、常温に戻した
際、前記実装基板と前記半導体チップの温度は変化する
ことがない。このため、前記実装基板と前記半導体チッ
プの熱膨脹係数の差により前記接続部に発生する応力や
歪みを低減させることができる。これにより、前記接続
部の破壊を防止することができる。この結果、半導体装
置の信頼性の低下を防止させることができる。According to the present invention, the first pad is formed on the surface of the mounting substrate, the second pad is formed on the surface of the semiconductor chip, and the magnetic material and the low melting point metal are formed on the second pad. A bump consisting of. By disposing the bump on the first pad and applying a high frequency magnetic field to the bump, the magnetic material is caused to generate heat, and the heat melts the low melting point metal. Therefore, the bumps can be intensively heated, and the portions other than the connection portion by the bumps are not heated. For this reason, thermal damage is not given to a portion other than the connection portion, so that deterioration due to heat can be prevented in the portion other than the connection portion. Moreover, when the connection portion is heated and then returned to room temperature, the temperatures of the mounting substrate and the semiconductor chip do not change. Therefore, it is possible to reduce the stress or strain generated in the connection portion due to the difference in thermal expansion coefficient between the mounting substrate and the semiconductor chip. As a result, it is possible to prevent the connection portion from being broken. As a result, it is possible to prevent the reliability of the semiconductor device from decreasing.
【００１２】[0012]
【実施例】以下、図面を参照してこの発明を実施例によ
り説明する。図１乃至図３は、この発明の第１の実施例
による半導体装置の製造方法を示す断面図である。図４
は、図１に示す半導体装置におけるバンプによる接続部
分を示す拡大断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. 1 to 3 are sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. Figure 4
FIG. 3 is an enlarged cross-sectional view showing a connection portion by bumps in the semiconductor device shown in FIG.
【００１３】先ず、図２に示すように、実装基板１１の
表面上には第１の電極パッド１２が設けられる。半導体
チップ１３の表面上には第２の電極パッド１４が設けら
れ、この第２の電極パッド１４の上には蒸着法及びメッ
キ法等により磁性材料１５ａとＰｂ／Ｓｎ等の低融点金
属１５ｂとからなるバンプ１５が形成される。First, as shown in FIG. 2, a first electrode pad 12 is provided on the surface of the mounting substrate 11. A second electrode pad 14 is provided on the surface of the semiconductor chip 13, and a magnetic material 15a and a low melting point metal 15b such as Pb / Sn are formed on the second electrode pad 14 by a vapor deposition method, a plating method or the like. The bumps 15 are formed.
【００１４】この後、図３に示すように、前記バンプ１
５が第１の電極パッド１２の上に位置するように、実装
基板１１の上には半導体チップ１３が配置される。次
に、図１及び図４に示すように、前記実装基板１１及び
半導体チップ１３の全体に高周波磁場が与えられる。こ
れにより、前記磁性材料１５ａは発熱され、この熱によ
り低融点金属１５ｂは溶融される。この結果、前記第２
の電極パッド１４はバンプ１５を介して第１の電極パッ
ド１２と接続される。After this, as shown in FIG.
The semiconductor chip 13 is arranged on the mounting substrate 11 so that the wiring 5 is located on the first electrode pad 12. Next, as shown in FIGS. 1 and 4, a high-frequency magnetic field is applied to the entire mounting substrate 11 and semiconductor chip 13. As a result, the magnetic material 15a is heated, and the low melting point metal 15b is melted by this heat. As a result, the second
The electrode pad 14 is connected to the first electrode pad 12 via the bump 15.
【００１５】尚、前記磁性材料１５ａは、磁気ヒステリ
シスが大きいものが好ましく、キュリ−温度が低融点金
属１５ｂの融点より２０℃〜５０℃程度高いものが好ま
しい。The magnetic material 15a preferably has a large magnetic hysteresis, and the Curie temperature is preferably higher than the melting point of the low melting point metal 15b by about 20 to 50.degree.
【００１６】上記第１の実施例によれば、第２の電極パ
ッド１４の上に磁性材料１５ａと低融点金属１５ｂとか
らなるバンプ１５を形成し、このバンプ１５が第１の電
極パッド１２の上に位置するように半導体チップ１３を
配置し、この半導体チップ１３及び実装基板１１の全体
に高周波磁場を与える。これにより、前記磁性材料１５
ａを発熱させ、この熱により低融点金属１５ｂを溶融し
ている。したがって、バンプ１５を集中的に加熱するこ
とができ、このバンプ１５による接続部以外の箇所が加
熱されることがない。このため、前記接続部以外の箇所
における加熱可能な温度の上限が低融点金属１５ｂの融
点より低い場合でも、上記バンプによる接続方法を使用
することができる。また、前記接続部以外の箇所に熱的
な損傷を与えることがないから、前記接続部以外の箇所
において、熱による劣化を防止することができる。ま
た、前記接続部を加熱した後、常温に戻した際、前記実
装基板１１と前記半導体チップ１３の温度は変化するこ
とがないため、前記実装基板１１と前記半導体チップ１
３の熱膨脹係数の差により前記接続部に発生する応力や
歪みを低減させることができる。これにより、前記接続
部の破壊を防止することができる。この結果、半導体装
置の信頼性の低下を防止することができる。According to the first embodiment described above, the bump 15 made of the magnetic material 15a and the low melting point metal 15b is formed on the second electrode pad 14, and the bump 15 serves as the first electrode pad 12. The semiconductor chip 13 is arranged so as to be located above, and a high-frequency magnetic field is applied to the entire semiconductor chip 13 and the mounting substrate 11. Thereby, the magnetic material 15
A heat is generated, and the low melting point metal 15b is melted by this heat. Therefore, the bumps 15 can be intensively heated, and the portions other than the connecting portions by the bumps 15 are not heated. Therefore, even when the upper limit of the temperature that can be heated in a portion other than the connection portion is lower than the melting point of the low melting point metal 15b, the connection method using the bump can be used. Further, since no thermal damage is given to a portion other than the connecting portion, deterioration due to heat can be prevented in a portion other than the connecting portion. Further, since the temperature of the mounting substrate 11 and the semiconductor chip 13 does not change when the connection portion is heated and then returned to room temperature, the mounting substrate 11 and the semiconductor chip 1 are not changed.
Due to the difference in the coefficient of thermal expansion of No. 3, the stress and strain generated in the connecting portion can be reduced. As a result, it is possible to prevent the connection portion from being broken. As a result, it is possible to prevent the reliability of the semiconductor device from decreasing.
【００１７】また、バンプ１５における磁性材料１５ａ
には、そのキュリ−温度が低融点金属の融点より２０℃
〜５０℃程度高い範囲にあるものを用いることにより、
バンプ１５の加熱温度を容易に制御することができる。The magnetic material 15a on the bump 15 is also used.
The Curie temperature is 20 ° C higher than the melting point of the low melting point metal.
By using a material in the high range of about -50 ° C,
The heating temperature of the bump 15 can be easily controlled.
【００１８】尚、上記第１の実施例では、第２の電極パ
ッド１４の上にバンプ１５を形成しているが、第１の電
極パッド１２の上にバンプ１５を形成することも可能で
ある。Although the bumps 15 are formed on the second electrode pads 14 in the first embodiment, the bumps 15 can be formed on the first electrode pads 12. .
【００１９】図５は、この発明の第２の実施例による半
導体装置におけるバンプによる接続部分を示す拡大断面
図であり、図４と同一部分には同一符号を付し、異なる
部分についてのみ説明する。FIG. 5 is an enlarged cross-sectional view showing a connecting portion by bumps in a semiconductor device according to a second embodiment of the present invention. The same portions as those in FIG. 4 are designated by the same reference numerals and only different portions will be described. .
【００２０】実装基板１１の表面上には第１の電極パッ
ド１２が設けられ、この第１の電極パッド１２の上には
磁性材料１５ａが設けられる。第２の電極パッド１４の
上には低融点金属からなるバンプ１５が形成される。A first electrode pad 12 is provided on the surface of the mounting substrate 11, and a magnetic material 15a is provided on the first electrode pad 12. Bumps 15 made of a low melting point metal are formed on the second electrode pads 14.
【００２１】上記第２の実施例においても第１の実施例
と同様の効果を得ることができる。図６は、この発明の
第３の実施例による半導体装置におけるバンプによる接
続部分を示す拡大断面図であり、図４と同一部分には同
一符号を付し、異なる部分についてのみ説明する。Also in the second embodiment, the same effect as that of the first embodiment can be obtained. FIG. 6 is an enlarged cross-sectional view showing a connection portion by a bump in a semiconductor device according to a third embodiment of the present invention. The same portions as those in FIG. 4 are designated by the same reference numerals and only different portions will be described.
【００２２】第２の電極パッド１４の上には粉末状の磁
性材料１５ａを含む低融点金属１５ｂからなるバンプ１
５が形成される。上記第３の実施例においても第１の実
施例と同様の効果を得ることができる。A bump 1 made of a low melting point metal 15b containing a powdery magnetic material 15a is formed on the second electrode pad 14.
5 is formed. Also in the third embodiment, the same effect as that of the first embodiment can be obtained.
【００２３】[0023]
【発明の効果】以上説明したようにこの発明によれば、
第１のパッドと第２のパッドとを磁性材料と低融点金属
とからなるバンプにより接続している。したがって、バ
ンプを集中的に加熱して溶融させることにより、半導体
装置の信頼性を向上させることができる。As described above, according to the present invention,
The first pad and the second pad are connected by a bump made of a magnetic material and a low melting point metal. Therefore, the reliability of the semiconductor device can be improved by intensively heating and melting the bumps.
【図１】この発明の第１の実施例による半導体装置の製
造方法を示すものであり、図３の次の工程を示す断面
図。FIG. 1 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention, showing the next step of FIG. 3;
【図２】この発明の第１の実施例による半導体装置の製
造方法を示す断面図。FIG. 2 is a sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図３】この発明の第１の実施例による半導体装置の製
造方法を示すものであり、図２の次の工程を示す断面
図。FIG. 3 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention, showing the next step of FIG. 2;
【図４】この発明の図１に示す半導体装置におけるバン
プによる接続部分を示す拡大断面図。FIG. 4 is an enlarged cross-sectional view showing a connection portion by bumps in the semiconductor device shown in FIG. 1 of the present invention.
【図５】この発明の第２の実施例による半導体装置にお
けるバンプによる接続部分を示す拡大断面図。FIG. 5 is an enlarged cross-sectional view showing a connection portion by bumps in a semiconductor device according to a second embodiment of the present invention.
【図６】この発明の第３の実施例による半導体装置にお
けるバンプによる接続部分を示す拡大断面図。FIG. 6 is an enlarged cross-sectional view showing a connection portion by bumps in a semiconductor device according to a third embodiment of the present invention.
【図７】従来の半導体装置を示す断面図。FIG. 7 is a sectional view showing a conventional semiconductor device.
【符号の説明】 11…実装基板、12…第１の電極パッド、13…半導体チッ
プ、14…第２の電極パッド、15…バンプ、15a …磁性材
料、15b …低融点金属[Explanation of reference numerals] 11 ... Mounting substrate, 12 ... First electrode pad, 13 ... Semiconductor chip, 14 ... Second electrode pad, 15 ... Bump, 15a ... Magnetic material, 15b ... Low melting point metal
Claims (5)
ッドと、 半導体チップの表面上に形成された第２のパッドと、 前記第１のパッドと前記第２のパッドとが接続された磁
性材料と低融点金属とからなるバンプと、 を具備することを特徴とする半導体装置。1. A first pad formed on a surface of a mounting substrate, a second pad formed on a surface of a semiconductor chip, the first pad and the second pad are connected to each other. A semiconductor device comprising: a bump made of a magnetic material and a low melting point metal.
設けられた磁性材料と低融点金属とからなるバンプを配
置する工程と、 前記バンプに高周波磁場を与えることにより、前記第１
のパッドと前記第２のパッドとを前記バンプにより接続
する工程と、 を具備することを特徴とする半導体装置の製造方法。2. A step of disposing a bump made of a magnetic material and a low melting point metal provided on a second pad on the first pad, and applying a high frequency magnetic field to the bump 1
And a step of connecting the second pad and the second pad by the bump, the method of manufacturing a semiconductor device.
徴とする請求項１又は２記載の半導体装置およびその製
造方法。3. The semiconductor device and its manufacturing method according to claim 1, wherein the magnetic material is in the form of powder.
上に、第２のパッド上に設けられた低融点金属からなる
バンプを配置する工程と、 前記磁性材料に高周波磁場を与えることにより、前記第
１のパッドと前記第２のパッドとを前記バンプにより接
続する工程と、 を具備することを特徴とする半導体装置の製造方法。4. A step of disposing a bump made of a low melting point metal provided on a second pad on a magnetic material provided on the first pad, and applying a high frequency magnetic field to the magnetic material. And a step of connecting the first pad and the second pad by the bump.
融点金属の融点より２０℃〜５０℃高い温度であること
を特徴とする請求項１、２又は４記載の半導体装置およ
びその製造方法。5. The semiconductor device according to claim 1, 2 or 4, wherein the Curie temperature of the magnetic material is 20 ° C. to 50 ° C. higher than the melting point of the low melting point metal. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5212696A JPH0766208A (en) | 1993-08-27 | 1993-08-27 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5212696A JPH0766208A (en) | 1993-08-27 | 1993-08-27 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0766208A true JPH0766208A (en) | 1995-03-10 |
Family
ID=16626919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5212696A Pending JPH0766208A (en) | 1993-08-27 | 1993-08-27 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0766208A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09199506A (en) * | 1995-11-15 | 1997-07-31 | Citizen Watch Co Ltd | Method for forming bump on semiconductor chip |
| KR100699805B1 (en) * | 2001-02-02 | 2007-03-27 | 삼성전자주식회사 | Ball Grid Array package using conductive balls comprising magnetic core |
| US9373609B2 (en) | 2012-10-18 | 2016-06-21 | Infineon Technologies Ag | Bump package and methods of formation thereof |
| CN110012614A (en) * | 2019-04-19 | 2019-07-12 | 维沃移动通信有限公司 | A kind of circuit board, circuit board assemblies, electronic equipment and welding method |
-
1993
- 1993-08-27 JP JP5212696A patent/JPH0766208A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09199506A (en) * | 1995-11-15 | 1997-07-31 | Citizen Watch Co Ltd | Method for forming bump on semiconductor chip |
| KR100699805B1 (en) * | 2001-02-02 | 2007-03-27 | 삼성전자주식회사 | Ball Grid Array package using conductive balls comprising magnetic core |
| US9373609B2 (en) | 2012-10-18 | 2016-06-21 | Infineon Technologies Ag | Bump package and methods of formation thereof |
| DE102013111540B4 (en) | 2012-10-18 | 2020-01-16 | Infineon Technologies Ag | Hump housing and method for its manufacture |
| CN110012614A (en) * | 2019-04-19 | 2019-07-12 | 维沃移动通信有限公司 | A kind of circuit board, circuit board assemblies, electronic equipment and welding method |
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