JPH0669052B2 - High-density mounting method for semiconductor devices - Google Patents
High-density mounting method for semiconductor devicesInfo
- Publication number
- JPH0669052B2 JPH0669052B2 JP60203068A JP20306885A JPH0669052B2 JP H0669052 B2 JPH0669052 B2 JP H0669052B2 JP 60203068 A JP60203068 A JP 60203068A JP 20306885 A JP20306885 A JP 20306885A JP H0669052 B2 JPH0669052 B2 JP H0669052B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- element package
- circuit board
- printed circuit
- mounting method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Description
【発明の詳細な説明】 〔概要〕 本発明の半導体素子の高密度実装方法は、プリント基板
に半導体素子パッケージが実装される際、両者間に所望
の間隔が形成される構造になっている。DETAILED DESCRIPTION OF THE INVENTION [Outline] The method for high-density mounting of semiconductor devices according to the present invention has a structure in which a desired space is formed between two semiconductor device packages when they are mounted on a printed circuit board.
このため該間隔を利用して、例えば改造ワイヤによる追
加配線等を行うことができるので、プリント板の高密度
実装化が実現できる。For this reason, it is possible to perform additional wiring using, for example, a modified wire, etc. by utilizing this interval, so that high-density mounting of the printed board can be realized.
本発明は半導体素子パッケージの実装方法の改良に係
り、特にプリント板の高密度実装化を目的として開発さ
れた半導体素子の高密度実装方法に関する。The present invention relates to an improvement in a mounting method of a semiconductor device package, and more particularly to a high density mounting method of a semiconductor device developed for high density mounting of a printed board.
第３図の構造図に示すように従来型の半導体素子パッケ
ージ２は、プリント基板１のボンディングパッド11と対
向して配設されたバンプ群３が、例えば電気炉等で加熱
されることによって溶融し、半導体素子パッケージ２と
プリント基板１間の電気回路を構成すると同時に機械的
にも両者が結合されるようになっている。As shown in the structural diagram of FIG. 3, in the conventional semiconductor element package 2, the bump group 3 arranged so as to face the bonding pad 11 of the printed circuit board 1 is melted by being heated by, for example, an electric furnace. However, an electric circuit between the semiconductor element package 2 and the printed circuit board 1 is formed, and at the same time, both are mechanically coupled.
一般にプリント基板１とバンプ接合によりボンディング
されるフリップチップタイプの半導体素子パッケージ２
は、他のボンディング方式よりも高密度の実装が可能で
ある。Generally, a flip-chip type semiconductor device package 2 is bonded to the printed board 1 by bump bonding.
Can be mounted at a higher density than other bonding methods.
しかしながら上記従来の半導体素子パッケージ２のバン
プ接合方式には下記の問題点がある。However, the bump bonding method of the conventional semiconductor device package 2 has the following problems.
以下それらの問題点を第３図の構成図および第４図の実
装方法図によって説明する。These problems will be described below with reference to the configuration diagram of FIG. 3 and the mounting method diagram of FIG.
半導体素子パッケージ２のサイズが大きくなるにつれ
てバンプ群３のピッチｐの累積誤差も大きくなり、基板
１側のボンディングパッド11との間に位置ズレが生じて
相互間の接合頼言度が低下する。As the size of the semiconductor element package 2 increases, the cumulative error of the pitch p of the bump group 3 also increases, causing a positional deviation between the bump pad 3 and the bonding pad 11 on the side of the substrate 1 and reducing the degree of mutual reliance on bonding.
バンプ群３とボンディングパッド11をダイレクトに接
合する実装方法を適用すると半導体素子パッケージ２と
プリント基板１との熱膨張率差によって接合部に歪を生
じ、接続部に大きな応力が加わるため接続信頼度に問題
がある。If the mounting method in which the bump group 3 and the bonding pad 11 are directly bonded is applied, the bonding portion is distorted due to the difference in coefficient of thermal expansion between the semiconductor element package 2 and the printed circuit board 1, and a large stress is applied to the connecting portion, so that the connection reliability is high. I have a problem.
半導体素子パッケージ２とプリント基板１間に形成さ
れるギャップΔが微小であるため（Δは通常0.5mm程
度）、該ギャップΔ内に、例えば改造用ワイヤ等を挿入
することができない。Since the gap Δ formed between the semiconductor element package 2 and the printed board 1 is very small (Δ is usually about 0.5 mm), for example, a modification wire or the like cannot be inserted into the gap Δ.
このため、改造パッド1aを半導体素子パッケージ２の外
周部に配置する必要が生じ、該改造パッド1aのエリアが
大きくなって実装密度が低下する。Therefore, it is necessary to dispose the modified pad 1a on the outer peripheral portion of the semiconductor element package 2, and the area of the modified pad 1a becomes large and the mounting density is reduced.
半導体素子パッケージ２のバンプ群３がARRAY構造配
置（例えば基盤目のような配置）になると、半導体素子
パッケージ２の外周部に配置された改造パッド1aとボン
ディングパッド11とを接続するための再配線層1bが必要
となり、基板１の層数が増加する。When the bump group 3 of the semiconductor device package 2 has an ARRAY structure arrangement (for example, a substrate-like arrangement), rewiring for connecting the modified pad 1a and the bonding pad 11 arranged on the outer peripheral portion of the semiconductor device package 2 The layer 1b is required and the number of layers of the substrate 1 is increased.
浸漬沸騰冷却方式で半導体素子パッケージ２を冷却す
る場合、プリント基板１と半導体素子パッケージ２のギ
ャップΔが狭いので沸騰時に発生する泡が該ギャップΔ
内に閉じ込められ、冷却効率を著しく悪化させる。When the semiconductor element package 2 is cooled by the immersion boiling cooling method, since the gap Δ between the printed circuit board 1 and the semiconductor element package 2 is narrow, bubbles generated during boiling are the gap Δ.
It is trapped inside and significantly deteriorates the cooling efficiency.
本発明は従来の半導体素子実装方法の改良を目的とする
もので、特にバンプ群３とボンディングパッド11の接続
に接続用コンタクト５を用いることで前記との問題
点を解決し、接続用コンタクト５の長さを調節すること
で前記ととの問題点を解決するようにしている。The present invention is intended to improve a conventional semiconductor element mounting method. In particular, by using the connecting contact 5 for connecting the bump group 3 and the bonding pad 11, the above-mentioned problems are solved, and the connecting contact 5 The problem with the above is solved by adjusting the length of.
本発明は、その実施例図面第１図に示すように、プリン
ト基板１のボンディングパッド11と半導体素子パッケー
ジ２のバンプ群３を接続用コンタクト５を介して接続す
ることによってこれらプリント基板１と半導体素子パッ
ケージ２間に所望間隔Ｌを形成し、且つ前記本接続用コ
ンタクト５の長さを変化させることによって前記半導体
素子パッケージ２と前記プリント基板１間に形成される
所望間隔Ｌを制御するようにしたことを特徴とする。As shown in FIG. 1 of the embodiment, the present invention connects a bonding pad 11 of a printed circuit board 1 and a bump group 3 of a semiconductor element package 2 via a contact 5 for connection between the printed circuit board 1 and the semiconductor. A desired space L is formed between the device packages 2 and the desired space L formed between the semiconductor device package 2 and the printed circuit board 1 is controlled by changing the length of the main connection contact 5. It is characterized by having done.
このように構成されたものにおいては、プリント基板１
のボンディングパッド11上に直立する形で配置された接
続用コンタクト５の開放側の端部と半導体素子パッケー
ジ２のバンプ群３を接合すればプリント基板１上に半導
体素子パッケージ２が所望の間隔Ｌを保持した状態で実
装される。In the case of such a configuration, the printed circuit board 1
If the open end of the connection contact 5 arranged upright on the bonding pad 11 is bonded to the bump group 3 of the semiconductor element package 2, the semiconductor element package 2 is placed on the printed circuit board 1 at a desired distance L. It is implemented while holding.
従って本発明によれば半導体素子パッケージ２と、プリ
ンタ基板１との間隔Ｌが接続用コンタクト５の長さを調
節することにより自在に変えられるため、例えば改造用
の回路部品（図示せず）等を実装するための基板内接続
用パターン12を半導体素子パッケージ２とプリント基板
１間に設けることができる。Therefore, according to the present invention, the distance L between the semiconductor element package 2 and the printer substrate 1 can be freely changed by adjusting the length of the connecting contact 5, so that, for example, a circuit component for remodeling (not shown) or the like. An in-board connecting pattern 12 for mounting the can be provided between the semiconductor element package 2 and the printed board 1.
以下図面に示した実施例に基づいて本発明を詳細に説明
する。The present invention will be described in detail below based on the embodiments shown in the drawings.
第１図は本発明の一実施例を示す高密度実装方法の構成
図である。FIG. 1 is a block diagram of a high-density mounting method showing an embodiment of the present invention.
なお全図を通じて同一符号は同一物を示す。Note that the same reference numerals denote the same parts throughout the drawings.
この図に示すように本発明の高密度実装方法は、先ずプ
リント基板１のボンディングパッド11上に先端を偏平型
に形成された接続用コンタクト５がボンディングされ
る。As shown in this figure, in the high-density mounting method of the present invention, first, the connecting contact 5 having a flat tip is bonded onto the bonding pad 11 of the printed board 1.
そしてボンディングされた接続用コンタクト５の他端側
に半導体素子パッケージ２のバンプ群３が位置決めさ
れ、これらを加熱してバンプ群３を接続用コンタクト５
に融着させる。なお、バンプ群３を接続用コンタクト５
に融着させる手段として本実施例ではリフロー半田付け
法を用いた。Then, the bump group 3 of the semiconductor element package 2 is positioned on the other end side of the bonded connection contact 5, and these are heated to connect the bump group 3 to the connection contact 5.
Fuse to. The bump group 3 is connected to the contact 5
In this embodiment, the reflow soldering method is used as a means for fusing.
以上の説明から明らかなように、本発明を適用すること
により、半導体素子パッケージ２とプリント基板１間に
所望間隔Ｌを自在に形成できることから、この所望間隔
Ｌを利用してそこに改造用の回路部品（図示せず）等を
実装するための基板内接続用パターン12を付設したり、
第２図に示す改造ワイヤ13を付設する等が可能となる。
また、本発明を適用することで半導体素子パッケージ２
とプリント基板１間のギャップΔが拡大されることか
ら、浸漬沸騰冷却法式で半導体素子パッケージ２を冷却
する時に泡がこのギャップΔ内に閉じ込めらるようなこ
とがないので冷却効率が著しく向上する。As is apparent from the above description, by applying the present invention, the desired distance L can be freely formed between the semiconductor element package 2 and the printed circuit board 1. Therefore, the desired distance L can be used to modify the desired distance L. Attaching an in-board connection pattern 12 for mounting circuit parts (not shown),
It is possible to attach the modified wire 13 shown in FIG.
Further, by applying the present invention, the semiconductor device package 2
Since the gap Δ between the printed circuit board 1 and the printed circuit board 1 is enlarged, bubbles are not trapped in the gap Δ when the semiconductor element package 2 is cooled by the immersion boiling cooling method, so that the cooling efficiency is significantly improved. .
第２図は本発明の細部構造の一例を示す図であって、
（ａ）は要部平面図、（ｂ）は要部側断面図である。FIG. 2 is a diagram showing an example of a detailed structure of the present invention,
(A) is a plan view of a main part, and (b) is a side sectional view of the main part.
同図は第１図に示した所望間隔Ｌのスペースを利用して
改造ワイヤ13の配線を行った例である。This figure is an example in which the modified wire 13 is laid using the space of the desired spacing L shown in FIG.
改造がある場合は、同図に示すように基板内層接続パッ
ド16を改造時のパターンカット部17でカットし、基板内
層接続パッド16と並列的に設けられている改造ワイヤボ
ンディング用パッド14に改造ワイヤ13を接続する。If there is modification, cut the board inner layer connection pad 16 with the pattern cutting part 17 at the time of modification as shown in the figure, and modify it to the modified wire bonding pad 14 provided in parallel with the board inner layer connection pad 16. Connect the wire 13.
以上述べた本発明による実装方法は、単にフリップチッ
プタイプの半導体素子パッケージに限らず、端子が表面
に突出している型式の所謂SMT型の半導体素子パッケー
ジにも適用できる。The mounting method according to the present invention described above is applicable not only to a flip-chip type semiconductor element package but also to a so-called SMT type semiconductor element package of a type in which terminals are projected on the surface.
本発明は以上説明したように、半導体素子パッケージと
プリント基板間に所望のギャップが確保されるため、半
導体素子パッケージとプリント基板間に改造ワイヤ13等
を増設することが可能となり、このため、改造パッド1b
を半導体素子パッケージ２の領域外に設ける、或いは再
配線層1bをプリント基板１の内層部分に設ける（第４図
参照）等の必要性が無くなるので、半導体素子パッケー
ジ２の高密度実装が可能となる。As described above, the present invention secures a desired gap between the semiconductor element package and the printed circuit board, so that it is possible to add a modified wire 13 or the like between the semiconductor element package and the printed circuit board. Pad 1b
Need not be provided outside the region of the semiconductor element package 2 or the rewiring layer 1b is provided in the inner layer portion of the printed circuit board 1 (see FIG. 4), so that high density mounting of the semiconductor element package 2 is possible. Become.
また浸漬沸騰冷却時における泡の付着問題も発生せず、
素子の冷却効率が著しく向上する。In addition, there is no problem of foam adhesion during immersion boiling cooling,
The cooling efficiency of the element is significantly improved.
第１図は本発明の一実施例を示す高密度実装方法の構成
図、 第２図は本発明の細部構造の一例を示す図であって、
（ａ）は要部平面図、（ｂ）は要部側断面図、 第３図は従来の半導体素子パッケージの構造図、 第４図は従来の半導体素子パッケージの実装方法図であ
る。 図中、１はプリント基板、1aは改造パッド、1bは再配線
層、２は半導体素子パッケージ、３はバンプ群、５は接
続用コンタクト、11はボンディングパッド、12は基板内
接続用パターン、13は改造ワイヤ、14は改造ワイヤボン
ディング用パッド、16は基板内層接続パッド、17は改造
時のパターンカット部、ｐはバンプ間のピッチ、Δは半
導体素子パッケージとプリント基板間に形成された微小
間隔、Ｌは半導体素子パッケージとプリント基板間に形
成される所望間隔をそれぞれ示す。FIG. 1 is a configuration diagram of a high-density mounting method showing an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a detailed structure of the present invention.
(A) is a plan view of a main part, (b) is a side sectional view of the main part, FIG. 3 is a structural diagram of a conventional semiconductor device package, and FIG. 4 is a mounting method diagram of the conventional semiconductor device package. In the figure, 1 is a printed circuit board, 1a is a modified pad, 1b is a rewiring layer, 2 is a semiconductor element package, 3 is a bump group, 5 is a contact for connection, 11 is a bonding pad, 12 is a pattern for connection within the board, 13 Is a modified wire, 14 is a modified wire bonding pad, 16 is a board inner layer connection pad, 17 is a pattern cut portion at the time of modification, p is a pitch between bumps, and Δ is a minute gap formed between the semiconductor element package and the printed board. , L denote desired intervals formed between the semiconductor device package and the printed circuit board.
Claims (1)
（１）に実装される半導体素子パッケージ（２）の実装
方法であって、 プリント基板（１）のボンディングパッド（11）と半導
体素子パッケージ（２）のバンプ群（３）を接続用コン
タクト（５）を介して接続することによってこれらプリ
ント基板（１）と半導体素子パッケージ（２）間に回路
変更等を行うための所望間隔（Ｌ）を形成し、且つ前記
接続用コンタクト（５）の長さを変化させることによっ
て前記半導体素子パッケージ（２）と前記プリント基板
（１）間に形成される所望間隔（Ｌ）を制御するように
したことを特徴とする半導体素子の高密度実装方法。1. A method of mounting a semiconductor element package (2) mounted on a printed board (1) via a bump group (3), comprising: a bonding pad (11) of the printed board (1) and a semiconductor element package. By connecting the bump group (3) of (2) via the connecting contact (5), a desired distance (L) for making a circuit change or the like between the printed board (1) and the semiconductor element package (2). And the desired distance (L) formed between the semiconductor device package (2) and the printed circuit board (1) is controlled by changing the length of the connection contact (5). A high-density mounting method for semiconductor devices, which is characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60203068A JPH0669052B2 (en) | 1985-09-12 | 1985-09-12 | High-density mounting method for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60203068A JPH0669052B2 (en) | 1985-09-12 | 1985-09-12 | High-density mounting method for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6262533A JPS6262533A (en) | 1987-03-19 |
| JPH0669052B2 true JPH0669052B2 (en) | 1994-08-31 |
Family
ID=16467811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60203068A Expired - Fee Related JPH0669052B2 (en) | 1985-09-12 | 1985-09-12 | High-density mounting method for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669052B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2622741A1 (en) * | 1987-11-04 | 1989-05-05 | Nec Corp | Structure for connecting substrates with different thermal expansion coefficients |
| JPH01170035A (en) * | 1987-12-02 | 1989-07-05 | Amp Inc | Micro-i/o pins and its manufacture |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5728337A (en) * | 1980-07-28 | 1982-02-16 | Hitachi Ltd | Connecting constructin of semiconductor element |
| JPS6151838A (en) * | 1984-08-22 | 1986-03-14 | Hitachi Ltd | Semiconductor device |
-
1985
- 1985-09-12 JP JP60203068A patent/JPH0669052B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6262533A (en) | 1987-03-19 |
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| LAPS | Cancellation because of no payment of annual fees |