JPH06151437A - Electrode structure of semiconductor device, its formation, and packaging body - Google Patents

Electrode structure of semiconductor device, its formation, and packaging body

Info

Publication number
JPH06151437A
JPH06151437A JP4296247A JP29624792A JPH06151437A JP H06151437 A JPH06151437 A JP H06151437A JP 4296247 A JP4296247 A JP 4296247A JP 29624792 A JP29624792 A JP 29624792A JP H06151437 A JPH06151437 A JP H06151437A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode
circuit board
forming
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4296247A
Other languages
Japanese (ja)
Other versions
JP3119739B2 (en
Inventor
Yoshihiro Bessho
芳宏 別所
Yoshihiro Tomura
善広 戸村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP04296247A priority Critical patent/JP3119739B2/en
Publication of JPH06151437A publication Critical patent/JPH06151437A/en
Application granted granted Critical
Publication of JP3119739B2 publication Critical patent/JP3119739B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent

Abstract

PURPOSE:To provide the electrode structure of a semiconductor device which can easily and highly reliably connect the semiconductor device to a circuit board, its manufacturing method, and a mounting body. CONSTITUTION:Bump electrodes 6 with rugged surfaces at their front end sections are provided on the electrode pads 2 of the IC board of a semiconductor device. Joining surfaces 7 are formed on the rugged surfaces of the electrodes 6 and the electrodes 6 for semiconductors are respectively joined to terminal electrodes 9 on a circuit board 8 through the layers 7. Therefore, the joining strengths of the electrodes 6 can be increased by the rugged surfaces at the front end sections of the electrodes and highly reliable junctions can be realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置を回路基板
に実装する際の半導体装置の電極構造とその形成方法な
らびに実装体に関するものであり、特にフェースダウン
で実装される半導体装置の電極構造とその形成方法なら
びに実装体に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure of a semiconductor device when mounting the semiconductor device on a circuit board, a method of forming the same, and a mounting body, and more particularly to an electrode structure of a semiconductor device mounted face down. And a method of forming the same and a mounting body.

【0002】[0002]

【従来の技術】従来、半導体装置を回路基板上へ実装す
るには半田付けが利用されることが多かったが、近年、
半導体装置のパッケージが小型化し、かつ接続端子数が
増加したことにより、接続端子間隔が狭くなり、従来の
半田付け技術で対処することは次第に困難になってき
た。
2. Description of the Related Art Conventionally, soldering was often used to mount a semiconductor device on a circuit board.
As the package of the semiconductor device has become smaller and the number of connection terminals has increased, the connection terminal interval has become narrower, and it has become increasingly difficult to cope with this with conventional soldering techniques.

【0003】そこで最近では、半導体装置を回路基板上
に直付けして実装面積を小型化し、回路基板の効率的使
用を図ろうとする方法が考案されている。なかでも、半
導体装置を回路基板に接続するに際し、アルミ電極パッ
ド上にあらかじめ密着金属や拡散防止金属の蒸着膜を形
成し、さらにこの上にメッキにより半田層を形成してな
る電極構造を有する半導体装置を製造し、この半導体装
置を回路基板にフェースダウンに積載して高温に加熱す
ることにより半田と回路基板の端子電極とを融着した実
装構造が、接続後の機械的強度が強く、一括して接続で
きることなどから有効な方法であるとされている(たと
えば、工業調査会、1980年1月15日発行、日本マ
イクロエレクトロニクス協会編、『IC化実装技
術』)。
Therefore, recently, a method has been devised in which a semiconductor device is directly mounted on a circuit board to reduce the mounting area and to efficiently use the circuit board. In particular, when connecting a semiconductor device to a circuit board, a semiconductor having an electrode structure in which a vapor deposition film of an adhesion metal or a diffusion prevention metal is formed in advance on an aluminum electrode pad, and a solder layer is formed on the vapor deposition film by plating. A mounting structure in which a device is manufactured and the semiconductor device is stacked face down on a circuit board and heated to a high temperature so that the solder and the terminal electrodes of the circuit board are fused together has high mechanical strength after connection and It is said that this is an effective method because it can be connected afterwards (for example, Industrial Research Society, published on January 15, 1980, edited by Japan Microelectronics Association, "IC implementation technology").

【0004】以下に図面を参照しながら、従来の半導体
装置の電極構造とその形成方法ならびに実装体の一例に
ついて説明する。図4は従来の半田バンプ電極を有する
半導体装置用電極の形成方法を示す概略説明図、図5は
電極構造を示す概略説明図、図6は実装体を示す概略説
明図である。
An example of a conventional electrode structure of a semiconductor device, a method for forming the same, and a mounting body will be described below with reference to the drawings. FIG. 4 is a schematic explanatory diagram showing a conventional method for forming an electrode for a semiconductor device having a solder bump electrode, FIG. 5 is a schematic explanatory diagram showing an electrode structure, and FIG. 6 is a schematic explanatory diagram showing a mounted body.

【0005】図4および図5において、10は半導体装
置のIC基板、11は電極パッド、12はパッシベーシ
ョン膜、13は密着金属膜、14は拡散防止金属膜、1
5はフォトレジスト膜である。16はメッキ後の半田バ
ンプであり、17はリフロー後の半田バンプである。図
6において、18は回路基板であり、19は端子電極で
ある。
4 and 5, 10 is an IC substrate of a semiconductor device, 11 is an electrode pad, 12 is a passivation film, 13 is an adhesion metal film, 14 is a diffusion prevention metal film, 1
5 is a photoresist film. Reference numeral 16 is a solder bump after plating, and 17 is a solder bump after reflow. In FIG. 6, 18 is a circuit board and 19 is a terminal electrode.

【0006】このような構成要素からなる従来の半田バ
ンプ電極を有する半導体装置の電極構造とその形成方法
ならびに実装体について、以下にその概略を説明する。
まず、図4(a)に示すように半導体装置のIC基板1
0の電極パッド11上にCuなどの密着金属膜13およ
びCrなどの拡散防止金属膜14を蒸着により形成す
る。その後、図4(b)に示すように電極部以外をフォ
トレジスト15で覆い、メッキ法により半田を拡散防止
金属膜14上に析出させ、図4(c)に示すマッシュル
ーム状の半田バンプ16を得る。最後に、半田リフロー
を行うことにより、図4(d)に示すように半田バンプ
17を形成して図5の電極構造の半田バンプ電極を得
る。
An electrode structure of a semiconductor device having a conventional solder bump electrode composed of such components, a method of forming the same, and a mounting body will be outlined below.
First, as shown in FIG. 4A, the IC substrate 1 of the semiconductor device
An adhesion metal film 13 such as Cu and a diffusion preventing metal film 14 such as Cr are formed on the electrode pad 11 of 0 by vapor deposition. After that, as shown in FIG. 4B, the portions other than the electrode portions are covered with the photoresist 15, and the solder is deposited on the diffusion preventing metal film 14 by the plating method to form the mushroom-shaped solder bumps 16 shown in FIG. 4C. obtain. Finally, by performing solder reflow, solder bumps 17 are formed as shown in FIG. 4D to obtain solder bump electrodes having the electrode structure of FIG.

【0007】さらに、このようにして得た半田バンプ電
極を有する半導体装置を、回路基板18の所定の位置に
位置合わせを行ってフェースダウンで積載した後、20
0〜300℃の高温に加熱して半田バンプ17を溶融
し、端子電極19に融着することで図6のような半導体
装置の実装体を得ることができる。
Further, the semiconductor device having the solder bump electrodes thus obtained is aligned at a predetermined position on the circuit board 18 and face-down loaded, and then 20
By heating to a high temperature of 0 to 300 ° C. to melt the solder bumps 17 and fuse the solder bumps 17 to the terminal electrodes 19, a semiconductor device package as shown in FIG. 6 can be obtained.

【0008】[0008]

【発明が解決しようとする課題】しかしながら上記のよ
うな半田バンプ電極を有する半導体装置の電極構造とそ
の形成方法ならびに実装体は、 1.高温に加熱し半田を溶融して端子電極と接続する際
に、IC基板と回路基板とのギャップを維持することが
できず、そのため半田が広がって隣接部とショートする
危険性がある、 2.熱膨張の異なるIC基板と回路基板とを半田で接続
しているため、熱応力に対して脆い、などといった問題
点を有していた。
However, the electrode structure of the semiconductor device having the solder bump electrodes as described above, the method for forming the same, and the mounting body are as follows. When the solder is melted by heating it to a high temperature and connecting it to the terminal electrode, the gap between the IC substrate and the circuit substrate cannot be maintained, so that there is a risk that the solder spreads and short-circuits with an adjacent portion. Since the IC substrate and the circuit substrate, which have different thermal expansions, are connected to each other by solder, there is a problem that they are brittle against thermal stress.

【0009】本発明は上記の問題に鑑みてなされたもの
であり、半導体装置と回路基板とを容易に信頼性高く接
続することのできる半導体装置の電極構造とその形成方
法ならびに実装体を提供することを目的とするものであ
る。
The present invention has been made in view of the above problems, and provides an electrode structure of a semiconductor device, a method of forming the same, and a mounting body that can easily and reliably connect the semiconductor device and a circuit board. That is the purpose.

【0010】[0010]

【課題を解決するための手段】上記課題を解決するため
に、本発明のフェースダウンで回路基板に実装される半
導体装置の電極構造は、半導体装置の電極パッド部上に
形成された突起電極を、先端部に凹凸面を有する構造に
したものである。
In order to solve the above-mentioned problems, an electrode structure of a semiconductor device mounted on a circuit board face down according to the present invention has a protruding electrode formed on an electrode pad portion of the semiconductor device. The structure has an uneven surface at the tip.

【0011】さらに、本発明のフェースダウンで回路基
板に実装される半導体装置用電極の形成方法は、半導体
装置の電極パッド部上に凸状の突起電極を形成する工程
と、前記突起電極を表面に凹凸を形成した平面土台に押
圧する工程と、前記平面土台を超音波振動させることに
よって、前記突起電極先端部に凹凸面を形成する工程と
を備えたものである。
Further, the method of forming a semiconductor device electrode mounted on a circuit board face down according to the present invention comprises a step of forming a convex protruding electrode on an electrode pad portion of the semiconductor device, and a step of forming the protruding electrode on the surface. And a step of forming an uneven surface on the tip end portion of the bump electrode by ultrasonically vibrating the flat base.

【0012】さらに本発明のフェースダウンで回路基板
に実装された半導体装置の実装体は、半導体装置の電極
パッド部上に形成された先端部に凹凸面を有する突起電
極を接合層を介して回路基板上の端子電極に電気的に接
続して構成したものである。
Further, according to the mounting body of a semiconductor device mounted on a circuit board face down according to the present invention, a protruding electrode having an uneven surface at a tip portion formed on an electrode pad portion of the semiconductor device is connected to a circuit via a bonding layer. It is configured by being electrically connected to the terminal electrodes on the substrate.

【0013】また、突起電極は、Auなどの金属を使
い、ワイヤボンディングやメッキなどの方法により形成
することができる。また、接合層は導電性接着剤や半田
などからなるものを用いればよい。
The bump electrodes can be formed by a method such as wire bonding or plating using metal such as Au. The bonding layer may be made of a conductive adhesive or solder.

【0014】[0014]

【作用】上記構成のように、半導体装置の電極パッド部
上に先端部に凹凸面を有した突起電極を設けたことによ
り、半導体装置を回路基板の端子電極に接合した際に、
突起電極の先端面と回路基板の端子電極との接着面積を
大きくすることができ、電気的、機械的に良好な接合が
可能となり、信頼性の高い半導体装置の実装体を得るこ
とができる。
As described above, by providing the protruding electrode having the uneven surface at the tip on the electrode pad portion of the semiconductor device, when the semiconductor device is bonded to the terminal electrode of the circuit board,
The bonding area between the tip surface of the protruding electrode and the terminal electrode of the circuit board can be increased, and good electrical and mechanical bonding can be achieved, and a highly reliable semiconductor device package can be obtained.

【0015】[0015]

【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。図1は本発明の一実施例における
半導体装置用電極の形成方法を示す概略説明図、図2は
上記実施例の電極形成方法による半導体装置の電極構造
を示す概略説明図、図3は上記実施例の電極を有する半
導体装置の実装体を示す概略説明図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic explanatory view showing a method of forming an electrode for a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic explanatory view showing an electrode structure of a semiconductor device by the electrode forming method of the above embodiment, and FIG. It is a schematic explanatory drawing which shows the mounted body of the semiconductor device which has an example electrode.

【0016】図1および図2において、1は半導体装置
のIC基板、2は電極パッド、3は突起電極である。4
は超音波発信器内蔵の平面土台、5は平面土台4の表面
に形成された凹凸面であり、6は先端部に凹凸面が形成
された突起電極である。図3において、7は導電性接着
剤からなる接合層であり、8は回路基板、9は端子電極
である。
1 and 2, 1 is an IC substrate of a semiconductor device, 2 is an electrode pad, and 3 is a protruding electrode. Four
Is a flat base with a built-in ultrasonic transmitter, 5 is an uneven surface formed on the surface of the flat base 4, and 6 is a protruding electrode having an uneven surface at the tip. In FIG. 3, 7 is a bonding layer made of a conductive adhesive, 8 is a circuit board, and 9 is a terminal electrode.

【0017】このような構成要素からなる半導体装置の
電極構造とその形成方法ならびに実装体について、以下
にその概略を説明する。まず、公知のAuによるメッキ
法により図1(a)に示す半導体装置のIC基板1の電
極パッド2上に突起電極3を形成する。次に図1(b)
に示すように、突起電極3を形成したIC基板1をフェ
ースダウンで表面に凹凸面5を形成した平面土台4上に
載置する。さらに図1(c)に示すように、平面土台4
に内蔵した超音波発振器を作動させ、平面土台4を振動
させることによって、突起電極3の先端部に凹凸面を形
成する。上記により、図2に示す先端部に凹凸面が形成
された突起電極6が容易に得られる。
The outline of the electrode structure of the semiconductor device including such components, the forming method thereof, and the mounting body will be described below. First, the bump electrode 3 is formed on the electrode pad 2 of the IC substrate 1 of the semiconductor device shown in FIG. 1A by a known Au plating method. Next, FIG. 1 (b)
As shown in, the IC substrate 1 having the protruding electrodes 3 formed thereon is placed face down on a flat base 4 having an uneven surface 5 formed on its surface. Further, as shown in FIG. 1C, the flat base 4
By operating the ultrasonic oscillator built into the substrate, the flat base 4 is vibrated to form an uneven surface at the tip of the protruding electrode 3. As described above, the protruding electrode 6 having the uneven surface formed at the tip portion shown in FIG. 2 can be easily obtained.

【0018】さらに、このようにして得た半導体装置の
突起電極6の先端部の凹凸面に導電性接着剤からなる接
合層7を転写法や印刷法により形成したのち、前記半導
体装置を回路基板8の所定の位置に位置合わせを行って
フェースダウンで積載した後、接合層7を硬化させて突
起電極6を端子電極9に接着させる。上記により、図3
に示すフェースダウンで回路基板に実装した半導体装置
の実装体を得る。
Further, after the bonding layer 7 made of a conductive adhesive is formed on the uneven surface of the tip portion of the bump electrode 6 of the semiconductor device thus obtained by the transfer method or the printing method, the semiconductor device is mounted on the circuit board. After aligning at a predetermined position of 8 and stacking face down, the bonding layer 7 is cured to bond the protruding electrode 6 to the terminal electrode 9. From the above, FIG.
A semiconductor device package mounted on a circuit board is obtained face down as shown in FIG.

【0019】半導体装置用電極を回路基板8の端子電極
9と接続する際に、突起電極6によりIC基板1と回路
基板8とのギャップを維持することができる。このた
め、接合層7の広がりを規制することが可能となり、隣
接部とショートする危険のない、微細ピッチで接続可能
な半導体装置の実装体が得られる。
When connecting the semiconductor device electrode to the terminal electrode 9 of the circuit board 8, the gap between the IC board 1 and the circuit board 8 can be maintained by the protruding electrode 6. For this reason, it is possible to regulate the spread of the bonding layer 7, and it is possible to obtain a semiconductor device package that can be connected at a fine pitch without the risk of short-circuiting with an adjacent portion.

【0020】また、先端部に凹凸面が形成された突起電
極を用いることにより、突起電極の凹凸部に接合層が入
り込むことで回路基板の端子電極との接着力が大きくな
り、極めて安定で信頼性が高く、かつ高密度に半導体装
置を実装することができる。
Further, by using the protruding electrode having the uneven surface at the tip, the bonding layer enters into the uneven portion of the protruding electrode to increase the adhesive force with the terminal electrode of the circuit board, which is extremely stable and reliable. The semiconductor device can be mounted with high density and high density.

【0021】なお、本実施例では突起電極をAuによる
メッキ法を用いて形成するとしたが、その形状が突起状
であればAuワイヤによるワイヤボンディングなどの方
法で形成しても良い。また、本実施例では導電性接着剤
からなる接合層を突起電極に転写法や印刷法により形成
するとしたが、回路基板の端子電極上にあらかじめ接合
層を形成しても良い。また、合層は導電性接着剤に限ら
れるものでなく、半田など他の接合材料でもよい。
In this embodiment, the bump electrode is formed by using the plating method using Au, but if the shape is a projection, it may be formed by a wire bonding method using Au wire. Further, in this embodiment, the bonding layer made of a conductive adhesive is formed on the protruding electrodes by the transfer method or the printing method, but the bonding layer may be formed in advance on the terminal electrodes of the circuit board. Further, the composite layer is not limited to the conductive adhesive, but may be another bonding material such as solder.

【0022】[0022]

【発明の効果】以上のように、本発明によれば、半導体
装置の突起電極の先端部に容易に凹凸面を形成すること
ができるため、極めて汎用性が高い。さらに、半導体装
置の突起電極の先端部に凹凸面を設けることにより、半
導体装置を回路基板の端子電極に接合する際に、突起電
極の凹凸面と回路基板の端子電極面との接合面積を大き
くできるため、極めて安定で信頼性の高い半導体装置の
実装体を得ることができる。
As described above, according to the present invention, since the uneven surface can be easily formed at the tip of the protruding electrode of the semiconductor device, the versatility is extremely high. Furthermore, by providing an uneven surface at the tip of the protruding electrode of the semiconductor device, when the semiconductor device is bonded to the terminal electrode of the circuit board, the bonding area between the uneven surface of the protruding electrode and the terminal electrode surface of the circuit board is increased. Therefore, an extremely stable and highly reliable semiconductor device package can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における半導体装置用電極の
形成方法を示す概略説明図
FIG. 1 is a schematic explanatory view showing a method for forming an electrode for a semiconductor device according to an embodiment of the present invention.

【図2】本発明の一実施例における半導体装置の電極構
造を示す概略説明図
FIG. 2 is a schematic explanatory diagram showing an electrode structure of a semiconductor device according to an embodiment of the present invention.

【図3】本発明の一実施例における半導体装置の実装体
を示す概略説明図
FIG. 3 is a schematic explanatory view showing a semiconductor device mounting body according to an embodiment of the present invention.

【図4】従来の半田バンプ電極を有する半導体装置用電
極の形成方法を示す概略説明図
FIG. 4 is a schematic explanatory view showing a method for forming an electrode for a semiconductor device having a conventional solder bump electrode.

【図5】従来の半田バンプ電極の電極構造を示す概略説
明図
FIG. 5 is a schematic explanatory view showing an electrode structure of a conventional solder bump electrode.

【図6】従来の半田バンプ電極を有する半導体装置の実
装体を示す概略説明図
FIG. 6 is a schematic explanatory view showing a mounting body of a semiconductor device having a conventional solder bump electrode.

【符号の説明】[Explanation of symbols]

1 半導体装置のIC基板 2 電極パッド 3 突起電極 4 超音波発振器内蔵の平面土台 5 凹凸面 6 先端部に凹凸面が形成された突起電極 7 接合層 8 回路基板 9 端子電極 1 IC substrate of semiconductor device 2 Electrode pad 3 Projection electrode 4 Planar base with built-in ultrasonic oscillator 5 Concavo-convex surface 6 Projection electrode with concavo-convex surface formed at the tip 7 Bonding layer 8 Circuit board 9 Terminal electrode

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 フェースダウンで回路基板に実装される
半導体装置の電極構造であって、半導体装置の電極パッ
ド部上に形成された突起電極は先端部に凹凸面を有する
ことを特徴とする半導体装置の電極構造。
1. An electrode structure of a semiconductor device mounted face down on a circuit board, wherein a protruding electrode formed on an electrode pad portion of the semiconductor device has an uneven surface at its tip. Device electrode structure.
【請求項2】 突起電極がAuからなることを特徴とす
る請求項1記載の半導体装置の電極構造。
2. The electrode structure of a semiconductor device according to claim 1, wherein the protruding electrode is made of Au.
【請求項3】 フェースダウンで回路基板に実装される
半導体装置用電極の形成方法であって、半導体装置の電
極パッド部上に凸状の突起電極を形成する工程と、前記
突起電極を表面に凹凸を形成した平面土台に押圧する工
程と、前記平面土台を超音波振動させることによって、
前記突起電極先端部に凹凸面を形成する工程とを備えた
ことを特徴とする半導体装置用電極の形成方法。
3. A method of forming electrodes for a semiconductor device to be mounted face down on a circuit board, comprising the steps of forming a convex protruding electrode on an electrode pad portion of the semiconductor device, and forming the protruding electrode on the surface. By pressing the flat base having irregularities and ultrasonically vibrating the flat base,
And a step of forming an uneven surface on the tip of the bump electrode.
【請求項4】 突起電極がAuによるメッキ法により形
成されることを特徴とする請求項3記載の半導体装置用
電極の形成方法。
4. The method for forming an electrode for a semiconductor device according to claim 3, wherein the protruding electrode is formed by a plating method using Au.
【請求項5】 突起電極がワイヤボンディング装置によ
りAuワイヤから形成されることを特徴とする請求項3
記載の半導体装置用電極の形成方法。
5. The protruding electrode is formed of Au wire by a wire bonding apparatus.
A method for forming an electrode for a semiconductor device as described above.
【請求項6】 フェースダウンで回路基板に実装される
半導体装置の実装体であって、半導体装置の電極パッド
部上に形成された先端部に凹凸面を有する突起電極が接
合層を介して回路基板上の端子電極に電気的に接続され
ていることを特徴とする半導体装置の実装体。
6. A semiconductor device mounting body mounted face down on a circuit board, wherein a protruding electrode having an uneven surface at a tip end portion formed on an electrode pad portion of the semiconductor device is a circuit via a bonding layer. A semiconductor device mounting body, which is electrically connected to a terminal electrode on a substrate.
【請求項7】 接合層が導電性接着剤からなることを特
徴とする請求項6記載の半導体装置の実装体。
7. The semiconductor device package according to claim 6, wherein the bonding layer is made of a conductive adhesive.
【請求項8】 接合層が半田からなることを特徴とする
請求項6記載の半導体装置の実装体。
8. The semiconductor device package according to claim 6, wherein the bonding layer is made of solder.
JP04296247A 1992-11-06 1992-11-06 Method for forming electrode for semiconductor device and package Expired - Fee Related JP3119739B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04296247A JP3119739B2 (en) 1992-11-06 1992-11-06 Method for forming electrode for semiconductor device and package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04296247A JP3119739B2 (en) 1992-11-06 1992-11-06 Method for forming electrode for semiconductor device and package

Publications (2)

Publication Number Publication Date
JPH06151437A true JPH06151437A (en) 1994-05-31
JP3119739B2 JP3119739B2 (en) 2000-12-25

Family

ID=17831100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04296247A Expired - Fee Related JP3119739B2 (en) 1992-11-06 1992-11-06 Method for forming electrode for semiconductor device and package

Country Status (1)

Country Link
JP (1) JP3119739B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002093852A (en) * 2000-09-18 2002-03-29 Matsushita Electric Ind Co Ltd Manufacturing method of semiconductor device, and the semiconductor device
JP2007109998A (en) * 2005-10-17 2007-04-26 Omron Corp Sensor device
DE19743767B4 (en) * 1996-12-27 2009-06-18 LG Semicon Co., Ltd., Cheongju A method of manufacturing a semiconductor die package having a surface mount semiconductor die and a semiconductor die package having a semiconductor die fabricated therefrom
JP2011124426A (en) * 2009-12-11 2011-06-23 Panasonic Corp Solder flip-chip mounting method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19743767B4 (en) * 1996-12-27 2009-06-18 LG Semicon Co., Ltd., Cheongju A method of manufacturing a semiconductor die package having a surface mount semiconductor die and a semiconductor die package having a semiconductor die fabricated therefrom
JP2002093852A (en) * 2000-09-18 2002-03-29 Matsushita Electric Ind Co Ltd Manufacturing method of semiconductor device, and the semiconductor device
JP4601141B2 (en) * 2000-09-18 2010-12-22 パナソニック株式会社 Semiconductor device manufacturing method and semiconductor device
JP2007109998A (en) * 2005-10-17 2007-04-26 Omron Corp Sensor device
JP2011124426A (en) * 2009-12-11 2011-06-23 Panasonic Corp Solder flip-chip mounting method

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