JP3119739B2 - Method for forming electrode for semiconductor device and package - Google Patents

Method for forming electrode for semiconductor device and package

Info

Publication number
JP3119739B2
JP3119739B2 JP04296247A JP29624792A JP3119739B2 JP 3119739 B2 JP3119739 B2 JP 3119739B2 JP 04296247 A JP04296247 A JP 04296247A JP 29624792 A JP29624792 A JP 29624792A JP 3119739 B2 JP3119739 B2 JP 3119739B2
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
forming
circuit board
protruding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04296247A
Other languages
Japanese (ja)
Other versions
JPH06151437A (en
Inventor
芳宏 別所
善広 戸村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP04296247A priority Critical patent/JP3119739B2/en
Publication of JPH06151437A publication Critical patent/JPH06151437A/en
Application granted granted Critical
Publication of JP3119739B2 publication Critical patent/JP3119739B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置を回路基板
に実装する際の半導体装置の電極構造とその形成方法な
らびに実装体に関するものであり、特にフェースダウン
で実装される半導体装置の電極構造とその形成方法なら
びに実装体に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure of a semiconductor device when the semiconductor device is mounted on a circuit board, a method of forming the same, and a mounting body, and more particularly to an electrode structure of a semiconductor device mounted face-down. And a method for forming the same and a package.

【0002】[0002]

【従来の技術】従来、半導体装置を回路基板上へ実装す
るには半田付けが利用されることが多かったが、近年、
半導体装置のパッケージが小型化し、かつ接続端子数が
増加したことにより、接続端子間隔が狭くなり、従来の
半田付け技術で対処することは次第に困難になってき
た。
2. Description of the Related Art Conventionally, soldering has often been used to mount a semiconductor device on a circuit board.
As the package of the semiconductor device has become smaller and the number of connection terminals has increased, the interval between the connection terminals has become narrower, and it has become increasingly difficult to deal with the conventional soldering technology.

【0003】そこで最近では、半導体装置を回路基板上
に直付けして実装面積を小型化し、回路基板の効率的使
用を図ろうとする方法が考案されている。なかでも、半
導体装置を回路基板に接続するに際し、アルミ電極パッ
ド上にあらかじめ密着金属や拡散防止金属の蒸着膜を形
成し、さらにこの上にメッキにより半田層を形成してな
る電極構造を有する半導体装置を製造し、この半導体装
置を回路基板にフェースダウンに積載して高温に加熱す
ることにより半田と回路基板の端子電極とを融着した実
装構造が、接続後の機械的強度が強く、一括して接続で
きることなどから有効な方法であるとされている(たと
えば、工業調査会、1980年1月15日発行、日本マ
イクロエレクトロニクス協会編、『IC化実装技
術』)。
Therefore, recently, a method has been devised in which a semiconductor device is directly mounted on a circuit board to reduce the mounting area, and the circuit board is used efficiently. Above all, when connecting a semiconductor device to a circuit board, a semiconductor having an electrode structure in which a vapor deposition film of an adhesion metal or a diffusion preventing metal is formed in advance on an aluminum electrode pad, and a solder layer is formed thereon by plating. The device is manufactured, this semiconductor device is mounted face down on a circuit board and heated to a high temperature to fuse the solder and the terminal electrodes of the circuit board. This method is considered to be an effective method because it can be connected to the Internet (for example, the Industrial Research Council, published on January 15, 1980, edited by the Japan Microelectronics Association, "IC mounting technology").

【0004】以下に図面を参照しながら、従来の半導体
装置の電極構造とその形成方法ならびに実装体の一例に
ついて説明する。図4は従来の半田バンプ電極を有する
半導体装置用電極の形成方法を示す概略説明図、図5は
電極構造を示す概略説明図、図6は実装体を示す概略説
明図である。
An example of a conventional electrode structure of a semiconductor device, a method of forming the same, and an example of a package will be described below with reference to the drawings. FIG. 4 is a schematic explanatory view showing a conventional method for forming an electrode for a semiconductor device having solder bump electrodes, FIG. 5 is a schematic explanatory view showing an electrode structure, and FIG. 6 is a schematic explanatory view showing a mounted body.

【0005】図4および図5において、10は半導体装
置のIC基板、11は電極パッド、12はパッシベーシ
ョン膜、13は密着金属膜、14は拡散防止金属膜、1
5はフォトレジスト膜である。16はメッキ後の半田バ
ンプであり、17はリフロー後の半田バンプである。図
6において、18は回路基板であり、19は端子電極で
ある。
In FIGS. 4 and 5, reference numeral 10 denotes an IC substrate of a semiconductor device, 11 denotes an electrode pad, 12 denotes a passivation film, 13 denotes an adhesion metal film, 14 denotes a diffusion preventing metal film, 1
Reference numeral 5 denotes a photoresist film. Reference numeral 16 denotes a solder bump after plating, and reference numeral 17 denotes a solder bump after reflow. In FIG. 6, reference numeral 18 denotes a circuit board, and 19 denotes a terminal electrode.

【0006】このような構成要素からなる従来の半田バ
ンプ電極を有する半導体装置の電極構造とその形成方法
ならびに実装体について、以下にその概略を説明する。
まず、図4(a)に示すように半導体装置のIC基板1
0の電極パッド11上にCuなどの密着金属膜13およ
びCrなどの拡散防止金属膜14を蒸着により形成す
る。その後、図4(b)に示すように電極部以外をフォ
トレジスト15で覆い、メッキ法により半田を拡散防止
金属膜14上に析出させ、図4(c)に示すマッシュル
ーム状の半田バンプ16を得る。最後に、半田リフロー
を行うことにより、図4(d)に示すように半田バンプ
17を形成して図5の電極構造の半田バンプ電極を得
る。
An outline of an electrode structure of a conventional semiconductor device having such a component and having a solder bump electrode, a method of forming the same, and a package will be described below.
First, as shown in FIG.
An adhesion metal film 13 such as Cu and a diffusion prevention metal film 14 such as Cr are formed on the 0 electrode pad 11 by vapor deposition. Thereafter, as shown in FIG. 4B, the portions other than the electrode portions are covered with a photoresist 15, and the solder is deposited on the diffusion preventing metal film 14 by a plating method, and the mushroom-shaped solder bumps 16 shown in FIG. obtain. Finally, by performing solder reflow, solder bumps 17 are formed as shown in FIG. 4D to obtain solder bump electrodes having the electrode structure of FIG.

【0007】さらに、このようにして得た半田バンプ電
極を有する半導体装置を、回路基板18の所定の位置に
位置合わせを行ってフェースダウンで積載した後、20
0〜300℃の高温に加熱して半田バンプ17を溶融
し、端子電極19に融着することで図6のような半導体
装置の実装体を得ることができる。
Further, the semiconductor device having the solder bump electrodes obtained in this manner is positioned face to face at a predetermined position on the circuit board 18, and then mounted on the circuit board 18.
By heating to a high temperature of 0 to 300 ° C. to melt the solder bumps 17 and fuse them to the terminal electrodes 19, a semiconductor device package as shown in FIG. 6 can be obtained.

【0008】[0008]

【発明が解決しようとする課題】しかしながら上記のよ
うな半田バンプ電極を有する半導体装置の電極構造とそ
の形成方法ならびに実装体は、 1.高温に加熱し半田を溶融して端子電極と接続する際
に、IC基板と回路基板とのギャップを維持することが
できず、そのため半田が広がって隣接部とショートする
危険性がある、 2.熱膨張の異なるIC基板と回路基板とを半田で接続
しているため、熱応力に対して脆い、などといった問題
点を有していた。
However, an electrode structure of a semiconductor device having the above-mentioned solder bump electrode, a method of forming the same, and a package are as follows. When heating to a high temperature to melt the solder and connect it to the terminal electrodes, the gap between the IC board and the circuit board cannot be maintained, and therefore, there is a risk that the solder spreads and short-circuits with an adjacent part. Since the IC board and the circuit board having different thermal expansions are connected by solder, they have a problem that they are brittle against thermal stress.

【0009】本発明は上記の問題に鑑みてなされたもの
であり、半導体装置と回路基板とを容易に信頼性高く接
続することのできる半導体装置の電極構造とその形成方
法ならびに実装体を提供することを目的とするものであ
る。
The present invention has been made in view of the above problems, and provides an electrode structure of a semiconductor device, a method of forming the electrode structure, and a mounting body that can easily and highly reliably connect the semiconductor device and a circuit board. The purpose is to do so.

【0010】[0010]

【課題を解決するための手段】本発明の請求項1記載の
半導体装置の実装体は、フェースダウンで回路基板に実
装される半導体装置の実装体であって、半導体装置の電
極パッド部上に形成された先端部に凹凸面を有する突起
電極が、導電性接着剤を介して回路基板上の端子電極に
電気的に接続されていることを特徴とする。 本発明の請
求項2記載の半導体装置の実装体は、請求項1において
突起電極がAuからなることを特徴とする。 本発明の請
求項3記載の半導体装置用電極の形成方法は、フェース
ダウンで回路基板に実装される半導体装置用電極の形成
方法であって、半導体装置の電極パッド部上に凸状の突
起電極を形成する工程と、前記突起電極を表面に凹凸を
形成した平面土台に押圧する工程と、前記平面土台を超
音波振動させることによって、前記突起電極先端部に凹
凸面を形成する工程とを備えたことを特徴とする本発
明の請求項4記載の半導体装置用電極の形成方法は、請
求項3において、突起電極がAuによるメッキ法により
形成されることを特徴とする本発明の請求項5記載の
半導体装置用電極の形成方法は、請求項3において、突
起電極がワイヤボンディング装置によりAuワイヤから
形成されることを特徴とする。
According to a first aspect of the present invention, there is provided:
The semiconductor device package is mounted face down on the circuit board.
A package of a semiconductor device to be mounted.
A projection with an uneven surface at the tip formed on the pole pad
The electrodes are connected to the terminal electrodes on the circuit board via conductive adhesive.
It is characterized by being electrically connected. The present invention
The package of the semiconductor device according to claim 2 is the package according to claim 1.
The projection electrode is made of Au. The present invention
4. The method for forming an electrode for a semiconductor device according to claim 3, wherein
Forming electrodes for semiconductor devices mounted on circuit boards by down
The method comprises the steps of: forming a projection on an electrode pad portion of a semiconductor device;
Forming an electromotive electrode, and forming the bump electrodes on the surface with irregularities.
Pressing the formed flat base; and
By vibrating with sound waves, a concave
Forming a convex surface . Departure
The method for forming an electrode for a semiconductor device according to claim 4 is
In claim 3, the protruding electrode is plated by Au.
It is characterized by being formed . Claim 5 of the present invention
The method for forming an electrode for a semiconductor device according to claim 3, wherein
Electrode from Au wire by wire bonding equipment
It is characterized by being formed.

【0011】[0011]

【0012】[0012]

【0013】[0013]

【0014】[0014]

【作用】上記構成のように、半導体装置の電極パッド部
上に先端部に凹凸面を有した突起電極を設けたことによ
り、半導体装置を回路基板の端子電極に接合した際に、
突起電極の先端面と回路基板の端子電極との接着面積を
大きくすることができ、電気的、機械的に良好な接合が
可能となり、信頼性の高い半導体装置の実装体を得るこ
とができる。
As described above, by providing a protruding electrode having an uneven surface at the tip on the electrode pad portion of the semiconductor device as described above, when the semiconductor device is joined to the terminal electrode of the circuit board,
The bonding area between the tip surface of the protruding electrode and the terminal electrode of the circuit board can be increased, good electrical and mechanical bonding can be achieved, and a highly reliable semiconductor device package can be obtained.

【0015】[0015]

【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。図1は本発明の一実施例における
半導体装置用電極の形成方法を示す概略説明図、図2は
上記実施例の電極形成方法による半導体装置の電極構造
を示す概略説明図、図3は上記実施例の電極を有する半
導体装置の実装体を示す概略説明図である。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic explanatory view showing a method of forming an electrode for a semiconductor device according to one embodiment of the present invention, FIG. 2 is a schematic explanatory view showing an electrode structure of a semiconductor device according to the electrode forming method of the above embodiment, and FIG. FIG. 2 is a schematic explanatory view showing a mounted body of a semiconductor device having an example electrode.

【0016】図1および図2において、1は半導体装置
のIC基板、2は電極パッド、3は突起電極である。4
は超音波発信器内蔵の平面土台、5は平面土台4の表面
に形成された凹凸面であり、6は先端部に凹凸面が形成
された突起電極である。図3において、7は導電性接着
剤からなる接合層であり、8は回路基板、9は端子電極
である。
1 and 2, reference numeral 1 denotes an IC substrate of a semiconductor device, 2 denotes an electrode pad, and 3 denotes a protruding electrode. 4
Denotes a flat base built in the ultrasonic transmitter, 5 denotes an uneven surface formed on the surface of the flat base 4, and 6 denotes a projecting electrode having an uneven surface formed at the tip. In FIG. 3, reference numeral 7 denotes a bonding layer made of a conductive adhesive, 8 denotes a circuit board, and 9 denotes a terminal electrode.

【0017】このような構成要素からなる半導体装置の
電極構造とその形成方法ならびに実装体について、以下
にその概略を説明する。まず、公知のAuによるメッキ
法により図1(a)に示す半導体装置のIC基板1の電
極パッド2上に突起電極3を形成する。次に図1(b)
に示すように、突起電極3を形成したIC基板1をフェ
ースダウンで表面に凹凸面5を形成した平面土台4上に
載置する。さらに図1(c)に示すように、平面土台4
に内蔵した超音波発振器を作動させ、平面土台4を振動
させることによって、突起電極3の先端部に凹凸面を形
成する。上記により、図2に示す先端部に凹凸面が形成
された突起電極6が容易に得られる。
An outline of an electrode structure of a semiconductor device having such components, a method of forming the same, and a mounting body will be described below. First, the projection electrode 3 is formed on the electrode pad 2 of the IC substrate 1 of the semiconductor device shown in FIG. 1A by a known Au plating method. Next, FIG.
As shown in (1), the IC substrate 1 on which the protruding electrodes 3 are formed is placed face down on a flat base 4 having an uneven surface 5 formed on the surface. Further, as shown in FIG.
By operating the ultrasonic oscillator built in the device and vibrating the flat base 4, an uneven surface is formed at the tip of the protruding electrode 3. As described above, the protruding electrode 6 shown in FIG.

【0018】さらに、このようにして得た半導体装置の
突起電極6の先端部の凹凸面に導電性接着剤からなる接
合層7を転写法や印刷法により形成したのち、前記半導
体装置を回路基板8の所定の位置に位置合わせを行って
フェースダウンで積載した後、接合層7を硬化させて突
起電極6を端子電極9に接着させる。上記により、図3
に示すフェースダウンで回路基板に実装した半導体装置
の実装体を得る。
Further, a bonding layer 7 made of a conductive adhesive is formed on the uneven surface at the tip of the protruding electrode 6 of the semiconductor device thus obtained by a transfer method or a printing method. After positioning at a predetermined position 8 and stacking face-down, the bonding layer 7 is cured and the protruding electrode 6 is bonded to the terminal electrode 9. From the above, FIG.
A semiconductor device mounted body mounted on a circuit board face-down is obtained as shown in FIG.

【0019】半導体装置用電極を回路基板8の端子電極
9と接続する際に、突起電極6によりIC基板1と回路
基板8とのギャップを維持することができる。このた
め、接合層7の広がりを規制することが可能となり、隣
接部とショートする危険のない、微細ピッチで接続可能
な半導体装置の実装体が得られる。
When the semiconductor device electrode is connected to the terminal electrode 9 of the circuit board 8, the gap between the IC substrate 1 and the circuit board 8 can be maintained by the protruding electrode 6. For this reason, it is possible to regulate the spread of the bonding layer 7, and it is possible to obtain a semiconductor device package that can be connected at a fine pitch without risk of short-circuiting with an adjacent portion.

【0020】また、先端部に凹凸面が形成された突起電
極を用いることにより、突起電極の凹凸部に接合層が入
り込むことで回路基板の端子電極との接着力が大きくな
り、極めて安定で信頼性が高く、かつ高密度に半導体装
置を実装することができる。
In addition, by using a projection electrode having an uneven surface at the tip, the bonding layer enters into the uneven portion of the projection electrode, thereby increasing the adhesive force with the terminal electrode of the circuit board. A semiconductor device can be mounted with high performance and high density.

【0021】なお、本実施例では突起電極をAuによる
メッキ法を用いて形成するとしたが、その形状が突起状
であればAuワイヤによるワイヤボンディングなどの方
法で形成しても良い。また、本実施例では導電性接着剤
からなる接合層を突起電極に転写法や印刷法により形成
するとしたが、回路基板の端子電極上にあらかじめ接合
層を形成しても良い
In this embodiment, the protruding electrodes are formed by using a plating method using Au. However, if the protruding electrodes have a protruding shape, they may be formed by a method such as wire bonding using an Au wire. In this embodiment, the bonding layer made of the conductive adhesive is formed on the protruding electrode by the transfer method or the printing method. However, the bonding layer may be formed in advance on the terminal electrode of the circuit board .

【0022】[0022]

【発明の効果】以上のように、本発明によれば、半導体
装置の突起電極の先端部に容易に凹凸面を形成すること
ができるため、極めて汎用性が高い。さらに、半導体装
置の突起電極の先端部に凹凸面を設けることにより、半
導体装置を回路基板の端子電極に接合する際に、突起電
極の凹凸面と回路基板の端子電極面との接合面積を大き
くできるため、極めて安定で信頼性の高い半導体装置の
実装体を得ることができる。
As described above, according to the present invention, an uneven surface can be easily formed at the tip of the protruding electrode of the semiconductor device, so that the versatility is extremely high. Furthermore, by providing an uneven surface at the tip of the protruding electrode of the semiconductor device, when joining the semiconductor device to the terminal electrode of the circuit board, the bonding area between the uneven surface of the protruding electrode and the terminal electrode surface of the circuit board is increased. Therefore, an extremely stable and highly reliable semiconductor device package can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例における半導体装置用電極の
形成方法を示す概略説明図
FIG. 1 is a schematic explanatory view showing a method for forming an electrode for a semiconductor device according to an embodiment of the present invention.

【図2】本発明の一実施例における半導体装置の電極構
造を示す概略説明図
FIG. 2 is a schematic explanatory view showing an electrode structure of a semiconductor device according to one embodiment of the present invention.

【図3】本発明の一実施例における半導体装置の実装体
を示す概略説明図
FIG. 3 is a schematic explanatory view showing a package of a semiconductor device according to an embodiment of the present invention;

【図4】従来の半田バンプ電極を有する半導体装置用電
極の形成方法を示す概略説明図
FIG. 4 is a schematic explanatory view showing a conventional method for forming an electrode for a semiconductor device having a solder bump electrode.

【図5】従来の半田バンプ電極の電極構造を示す概略説
明図
FIG. 5 is a schematic explanatory view showing an electrode structure of a conventional solder bump electrode.

【図6】従来の半田バンプ電極を有する半導体装置の実
装体を示す概略説明図
FIG. 6 is a schematic explanatory view showing a packaged semiconductor device having a conventional solder bump electrode.

【符号の説明】[Explanation of symbols]

1 半導体装置のIC基板 2 電極パッド 3 突起電極 4 超音波発振器内蔵の平面土台 5 凹凸面 6 先端部に凹凸面が形成された突起電極 7 接合層 8 回路基板 9 端子電極 DESCRIPTION OF SYMBOLS 1 IC board of semiconductor device 2 Electrode pad 3 Protruding electrode 4 Flat base with built-in ultrasonic oscillator 5 Uneven surface 6 Protruding electrode with uneven surface formed at the tip 7 Bonding layer 8 Circuit board 9 Terminal electrode

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/60

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】フェースダウンで回路基板に実装される半
導体装置の実装体であって、半導体装置の電極パッド部
上に形成された先端部に凹凸面を有する突起電極が、導
電性接着剤を介して回路基板上の端子電極に電気的に接
続されていることを特徴とする半導体装置の実装体。
1. A semiconductor device mounted face-down on a circuit board, comprising: an electrode pad portion of the semiconductor device.
A protruding electrode with an uneven surface at the tip formed on top
Electrically connected to the terminal electrodes on the circuit board via the conductive adhesive
A package of a semiconductor device characterized by being connected.
【請求項2】突起電極がAuからなることを特徴とする
請求項1記載の半導体装置の実装体
2. A mounting member as claimed in claim 1, wherein the projecting electrode is characterized in that it consists of Au.
【請求項3】フェースダウンで回路基板に実装される半
導体装置用電極の形成方法であって、半導体装置の電極
パッド部上に凸状の突起電極を形成する工程と、前記突
起電極を表面に凹凸を形成した平面土台に押圧する工程
と、前記平面土台を超音波振動させることによって、前
記突起電極先端部に凹凸面を形成する工程とを備えたこ
とを特徴とする半導体装置用電極の形成方法。
3. A method for forming an electrode for a semiconductor device mounted on a circuit board face down, comprising: forming a protruding projection electrode on an electrode pad portion of the semiconductor device; Forming an electrode for a semiconductor device, comprising: a step of pressing against a flat base having projections and depressions; and a step of forming a projection and depression surface at the tip of the protruding electrode by ultrasonically vibrating the flat base. Method.
【請求項4】突起電極がAuによるメッキ法により形成
されることを特徴とする請求項3記載の半導体装置用電
極の形成方法。
4. The method for forming an electrode for a semiconductor device according to claim 3, wherein the protruding electrode is formed by a plating method using Au.
【請求項5】突起電極がワイヤボンディング装置により
Auワイヤから形成されることを特徴とする請求項3記
載の半導体装置用電極の形成方法。
5. The method for forming an electrode for a semiconductor device according to claim 3, wherein the protruding electrode is formed from an Au wire by a wire bonding apparatus.
JP04296247A 1992-11-06 1992-11-06 Method for forming electrode for semiconductor device and package Expired - Fee Related JP3119739B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04296247A JP3119739B2 (en) 1992-11-06 1992-11-06 Method for forming electrode for semiconductor device and package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04296247A JP3119739B2 (en) 1992-11-06 1992-11-06 Method for forming electrode for semiconductor device and package

Publications (2)

Publication Number Publication Date
JPH06151437A JPH06151437A (en) 1994-05-31
JP3119739B2 true JP3119739B2 (en) 2000-12-25

Family

ID=17831100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04296247A Expired - Fee Related JP3119739B2 (en) 1992-11-06 1992-11-06 Method for forming electrode for semiconductor device and package

Country Status (1)

Country Link
JP (1) JP3119739B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100239406B1 (en) * 1996-12-27 2000-01-15 김영환 Surface mounted semiconductor package and method of manufacturing the same
JP4601141B2 (en) * 2000-09-18 2010-12-22 パナソニック株式会社 Semiconductor device manufacturing method and semiconductor device
JP4380616B2 (en) * 2005-10-17 2009-12-09 オムロン株式会社 Electronic component mounting substrate and manufacturing method thereof, sensor device and manufacturing method thereof
JP5457157B2 (en) * 2009-12-11 2014-04-02 パナソニック株式会社 Solder flip chip mounting method

Also Published As

Publication number Publication date
JPH06151437A (en) 1994-05-31

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