JP2001326236A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JP2001326236A
JP2001326236A JP2000140714A JP2000140714A JP2001326236A JP 2001326236 A JP2001326236 A JP 2001326236A JP 2000140714 A JP2000140714 A JP 2000140714A JP 2000140714 A JP2000140714 A JP 2000140714A JP 2001326236 A JP2001326236 A JP 2001326236A
Authority
JP
Japan
Prior art keywords
chip substrate
synthetic resin
chip
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000140714A
Other languages
Japanese (ja)
Inventor
Naoto Kimura
直人 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2000140714A priority Critical patent/JP2001326236A/en
Publication of JP2001326236A publication Critical patent/JP2001326236A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the warpage of a semiconductor device caused by synthetic resin sealing. SOLUTION: On a chip substrate 2 made of a synthetic resin, a plurality of semiconductor chips 4 are mutually bonded and fixed at intervals. On the chip substrate 2 around at least each semiconductor chip 4, a synthetic resin 18 that is heated for fluidizing is filled. After the filled synthetic resin 18 is cooled for curing, the synthetic resin 18 and the chip substrate 2 are cut between adjacent semiconductor chips 4 for obtaining each semiconductor device 20. At that time, on a region on the chip substrate 2 other than a place where the semiconductor chip 4 is fixed, an invar plate 12 where a coefficient of thermal expansion is small or negative is extended for bonding and fixing to the chip substrate 2 in advance. The synthetic resin 18 after the curing and chip substrate 2 is cut so that the plate 12 is not included in each semiconductor device 20.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特にチップ基板上に配置した半導体チップを
合成樹脂により封止する工程を含む半導体装置の製造方
法に関するものである。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of sealing a semiconductor chip disposed on a chip substrate with a synthetic resin.

【０００２】[0002]

【従来の技術】半導体チップの１つの実装形態として、
合成樹脂から成るチップ基板上に半導体チップを接着固
定し、半導体チップの周辺あるいは全体を合成樹脂によ
り封止する方式が用いられる。半導体チップを封止する
ための合成樹脂は、加熱して溶融させ、流動状態にして
半導体チップ周辺などに供給される。そして、合成樹脂
の温度が低下し、硬化した段階で各半導体チップごとに
個々の半導体装置とすべく合成樹脂およびチップ基板が
切断される。2. Description of the Related Art As one mounting form of a semiconductor chip,
A method is used in which a semiconductor chip is bonded and fixed on a chip substrate made of a synthetic resin, and the periphery or the whole of the semiconductor chip is sealed with the synthetic resin. A synthetic resin for sealing a semiconductor chip is heated and melted, and is supplied in a fluidized state around the semiconductor chip. Then, at a stage where the temperature of the synthetic resin is lowered and cured, the synthetic resin and the chip substrate are cut into individual semiconductor devices for each semiconductor chip.

【０００３】[0003]

【発明が解決しようとする課題】ところで、チップ基
板、チップ、ならびに封止用の合成樹脂はそれぞれ熱膨
張率が異なり、特に封止用の合成樹脂は冷却時の収縮率
が大きいため、バイメタルの変形と同じ原理で、チップ
基板全体は、チップ基板側に凸の状態で反ったものとな
ってしまう。このような反りは切断前のみならず、切断
により個々の半導体装置とした状態でも生じており、そ
の結果、半導体装置をプリント基板に搭載して半田ボー
ルにより接合する場合に、半田ボールとの間に隙間が生
じるなどして接合不良を引き起こすことがある。Incidentally, the chip substrate, the chip, and the synthetic resin for sealing have different thermal expansion coefficients. Particularly, the synthetic resin for sealing has a large shrinkage rate upon cooling. On the same principle as the deformation, the entire chip substrate is warped in a state of being convex toward the chip substrate. Such warpage occurs not only before cutting but also in a state where individual semiconductor devices are cut by cutting. As a result, when the semiconductor device is mounted on a printed circuit board and joined by solder balls, the warpage between the semiconductor devices and the solder balls occurs. In some cases, a gap may be formed in the wire, resulting in poor bonding.

【０００４】本発明はこのような問題を解決するために
なされたもので、その目的は、合成樹脂封止に伴う半導
体装置の反りを防止できる半導体装置の製造方法を提供
することにある。The present invention has been made to solve such a problem, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a semiconductor device from being warped due to sealing with a synthetic resin.

【０００５】[0005]

【課題を解決するための手段】本発明は、上記目的を達
成するため、合成樹脂から成るチップ基板上に、相互に
間隔をおいて複数の半導体チップを接着固定し、少なく
とも前記半導体チップの周辺の前記チップ基板上に、加
熱して流動状態の前記合成樹脂を充填し、充填した前記
合成樹脂が冷却により硬化した後、隣接する前記半導体
チップの間で前記合成樹脂および前記チップ基板を切断
して、それぞれが少なくとも１つの前記半導体チップを
含む個々の半導体装置を得る半導体装置の製造方法であ
って、あらかじめ前記半導体チップの固定箇所を除く前
記チップ基板上に、熱膨張率が小さいか、または負値で
ある金属材料の板体を延在させて前記チップ基板に接着
固定した上で、前記合成樹脂を充填し、硬化した前記合
成樹脂および前記チップ基板を切断する際は、個々の前
記半導体装置に前記板体が含まれないように切断するこ
とを特徴とする。According to the present invention, in order to achieve the above object, a plurality of semiconductor chips are bonded and fixed at intervals to each other on a chip substrate made of synthetic resin, and at least a periphery of the semiconductor chip is provided. The above-mentioned chip substrate is filled with the synthetic resin in a heated and fluidized state, and after the filled synthetic resin is cured by cooling, the synthetic resin and the chip substrate are cut between adjacent semiconductor chips. A method of manufacturing a semiconductor device, each of which obtains an individual semiconductor device including at least one of the semiconductor chips, wherein the coefficient of thermal expansion is small on the chip substrate excluding a portion where the semiconductor chip is fixed, or After extending a plate of a metal material having a negative value and adhering and fixing the chip to the chip substrate, filling the synthetic resin, and curing the synthetic resin and the When cutting the-up substrate, wherein the cutting so that it does not contain the plate member to each of said semiconductor device.

【０００６】このように、本発明の半導体装置の製造方
法では、半導体チップが固定されている箇所を除くチッ
プ基板上の領域に、熱膨張率が小さいか、または負値で
ある金属材料の板体をあらかじめ延在させてチップ基板
に接着固定しておくので、チップ基板が金属材料の板体
により補強され、充填する合成樹脂の熱膨張率が大きい
場合でも、合成樹脂が硬化した際のチップ基板の反りは
大幅に緩和される。そのため、半田ボールによりプリン
ト基板と接合する場合の接合不良発生の問題を解決する
ことができる。また、合成樹脂およびチップ基板を切断
する際は、個々の半導体装置に板体が含まれないように
切断するので、半導体装置が大型化したり、重量が増す
ことはなく、本半導体装置を使用する装置の小型・軽量
化に有利である。As described above, according to the method of manufacturing a semiconductor device of the present invention, a metal material plate having a small coefficient of thermal expansion or a negative value is provided in a region on a chip substrate except for a portion where a semiconductor chip is fixed. Since the body is extended and fixed to the chip substrate by bonding, the chip substrate is reinforced by a metal plate, and even when the synthetic resin to be filled has a large coefficient of thermal expansion, the chip when the synthetic resin is cured Substrate warpage is greatly reduced. Therefore, it is possible to solve the problem of the occurrence of defective bonding when bonding to a printed circuit board with solder balls. Further, when cutting the synthetic resin and the chip substrate, each semiconductor device is cut so as not to include a plate, so that the semiconductor device is used without increasing the size or increasing the weight. This is advantageous for reducing the size and weight of the device.

【０００７】[0007]

【発明の実施の形態】次に本発明の実施の形態例につい
て図面を参照して説明する。図１は本発明の製造方法に
より製造したチップ基板切断前の半導体装置の一例を示
す断面側面図、図２は本発明の製造方法により製造した
チップ基板切断後の半導体装置の一例を示す断面側面図
である。本実施の形態例では、まず、一例としてガラス
エポキシ樹脂から成るチップ基板２上に、相互に間隔を
おいて複数の半導体チップ４を接着剤６により接着固定
する。より具体的には、半導体チップ４は平面視略矩形
であり、このような半導体チップ４をチップ基板２上に
マトリクス状に配置して固定する。また、チップ基板２
には半導体チップ４の配置個所近傍に開口８が形成され
るとともに、半導体チップ４と反対側の面、すなわち下
面には導電性材料から成るパターン１０が被着されてい
る。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional side view showing an example of a semiconductor device before cutting a chip substrate manufactured by the manufacturing method of the present invention. FIG. 2 is a cross-sectional side view showing one example of a semiconductor device after cutting the chip substrate manufactured by the manufacturing method of the present invention. FIG. In the present embodiment, first, a plurality of semiconductor chips 4 are bonded and fixed with an adhesive 6 at an interval to each other on a chip substrate 2 made of, for example, a glass epoxy resin. More specifically, the semiconductor chip 4 is substantially rectangular in plan view, and such semiconductor chips 4 are arranged and fixed on the chip substrate 2 in a matrix. In addition, chip substrate 2
An opening 8 is formed in the vicinity of the place where the semiconductor chip 4 is arranged, and a pattern 10 made of a conductive material is applied to a surface opposite to the semiconductor chip 4, that is, a lower surface.

【０００８】その後、半導体チップ４が固定されている
箇所を除くチップ基板２上の領域に、熱膨張率が小さい
か、または負値である金属材料としてアンバ（または超
アンバ）の板体１２を延在させてチップ基板２に接着固
定する。この板体１２は本実施の形態例では、各半導体
チップ４を囲み、縦横の格子状に延在させる。ここで、
板体１２の寸法としては、幅はたとえば２ｍｍ程度、厚
みはたとえば５０μｍ〜１００μｍ程度とすることで良
好な結果を得ることができる。After that, an amber (or super-invar) plate 12 as a metal material having a small coefficient of thermal expansion or a negative value is placed in a region on the chip substrate 2 excluding a portion where the semiconductor chip 4 is fixed. It is extended and adhesively fixed to the chip substrate 2. In the present embodiment, the plate body 12 surrounds each semiconductor chip 4 and extends in a vertical and horizontal lattice. here,
Good results can be obtained by setting the width of the plate body 12 to about 2 mm and the thickness to about 50 μm to 100 μm, for example.

【０００９】つづいて、半導体チップ４の端子１４とパ
ターン１０とを、開口８を通じて敷設した導電性材料か
ら成るワイヤ１６により接続する。その後、本実施の形
態例では一例として半導体チップ４の周辺のチップ基板
２上に、加熱して流動状態の合成樹脂１８を充填する。
ここで、合成樹脂１８は、図１に示したように、チップ
基板２の下面側も含め、チップ基板２の開口８およびワ
イヤ１６の周辺箇所にも充填する。ただし、チップ基板
２の下面に形成されたパターン１０の箇所は少なくとも
一部を露出させておく。Subsequently, the terminals 14 of the semiconductor chip 4 and the pattern 10 are connected by wires 16 made of a conductive material laid through the openings 8. Thereafter, in the present embodiment, as an example, the chip substrate 2 around the semiconductor chip 4 is filled with the synthetic resin 18 in a heated and flowing state.
Here, as shown in FIG. 1, the synthetic resin 18 also fills the openings 8 of the chip substrate 2 and the peripheral portions of the wires 16, including the lower surface side of the chip substrate 2. However, at least a part of the pattern 10 formed on the lower surface of the chip substrate 2 is exposed.

【００１０】そして、充填した合成樹脂１８が冷却によ
り硬化した後、隣接する半導体チップ４の間で合成樹脂
１８およびチップ基板２を切断して、それぞれが１つの
半導体チップ４を含む個々の半導体装置２０を得る。こ
こで、合成樹脂１８およびチップ基板２を切断する際に
は、個々の半導体装置２０に板体１２が含まれないよう
に切断し、したがって切断後の半導体装置２０は図２に
示したようなものとなる。作製した半導体装置２０は、
図２に示したように、プリント基板２２上のパターン２
４とチップ基板２下面のパターン１０との間に半田ボー
ル２６を介在させた状態で、加熱により半田ボール２６
を溶融させ、パターン１０とパターン２４とを接合す
る。Then, after the filled synthetic resin 18 is cured by cooling, the synthetic resin 18 and the chip substrate 2 are cut between the adjacent semiconductor chips 4, and individual semiconductor devices each including one semiconductor chip 4 are cut. Get 20. Here, when cutting the synthetic resin 18 and the chip substrate 2, the individual semiconductor devices 20 are cut so as not to include the plate body 12. Therefore, the cut semiconductor device 20 is as shown in FIG. It will be. The manufactured semiconductor device 20
As shown in FIG.
In a state where the solder ball 26 is interposed between the solder ball 26 and the pattern 10 on the lower surface of the chip substrate 2, the solder ball 26 is heated.
And the pattern 10 and the pattern 24 are joined.

【００１１】そして、本実施の形態例では、上述のよう
に、半導体チップ４が固定されている箇所を除くチップ
基板２上の領域にアンバの板体１２を、あらかじめ延在
させてチップ基板２に接着固定しておくので、チップ基
板２が金属材料の板体１２により補強され、充填する合
成樹脂１８の熱膨張率が大きい場合でも、合成樹脂１８
が硬化した際のチップ基板２の反りは大幅に緩和され
る。そのため、半田ボール２６によりプリント基板２２
と接合する場合の接合不良発生の問題を解決することが
できる。また、合成樹脂１８およびチップ基板２を切断
する際は、個々の半導体装置２０に板体１２が含まれな
いように切断するので、半導体装置２０が大型化した
り、重量が増すことはなく、本半導体装置を使用する装
置の小型・軽量化に有利である。In this embodiment, as described above, the invar plate 12 is previously extended in a region on the chip substrate 2 excluding the portion where the semiconductor chip 4 is fixed, and Therefore, even if the chip substrate 2 is reinforced by the metal material plate 12 and the coefficient of thermal expansion of the synthetic resin 18 to be filled is large,
The warpage of the chip substrate 2 when is cured is greatly reduced. Therefore, the printed circuit board 22 is
It is possible to solve the problem of the occurrence of poor joining when joining. Further, when cutting the synthetic resin 18 and the chip substrate 2, the individual semiconductor devices 20 are cut so as not to include the plate body 12, so that the semiconductor device 20 does not increase in size or increase in weight. This is advantageous in reducing the size and weight of a device using a semiconductor device.

【００１２】なお、本実施の形態例では、チップ基板２
はガラスエポキシ樹脂により形成されているとしたが、
チップ基板２が合成樹脂によりフィルム状に形成されて
いる場合にも本発明は無論有効である。また、合成樹脂
１８は半導体チップ４の周辺に限らず、半導体チップ４
の上部にも充填してよく、その場合にも同様に板体１２
の作用によりチップ基板２の反りを防止できる。In this embodiment, the chip substrate 2
Is made of glass epoxy resin,
The present invention is of course also effective when the chip substrate 2 is formed in a film shape from a synthetic resin. Further, the synthetic resin 18 is not limited to the periphery of the semiconductor chip 4,
May be filled also in the upper part of the plate body.
Can prevent the chip substrate 2 from warping.

【００１３】[0013]

【発明の効果】以上説明したように本発明は、合成樹脂
から成るチップ基板上に、相互に間隔をおいて複数の半
導体チップを接着固定し、少なくとも前記半導体チップ
の周辺の前記チップ基板上に、加熱して流動状態の前記
合成樹脂を充填し、充填した前記合成樹脂が冷却により
硬化した後、隣接する前記半導体チップの間で前記合成
樹脂および前記チップ基板を切断して、それぞれが少な
くとも１つの前記半導体チップを含む個々の半導体装置
を得る半導体装置の製造方法であって、あらかじめ前記
半導体チップの固定箇所を除く前記チップ基板上に、熱
膨張率が小さいか、または負値である金属材料の板体を
延在させて前記チップ基板に接着固定した上で、前記合
成樹脂を充填し、硬化した前記合成樹脂および前記チッ
プ基板を切断する際は、個々の前記半導体装置に前記板
体が含まれないように切断することを特徴とする。As described above, according to the present invention, a plurality of semiconductor chips are bonded and fixed at intervals to each other on a chip substrate made of a synthetic resin, and at least on the chip substrate around the semiconductor chip. Heating, filling the synthetic resin in a fluidized state, after the filled synthetic resin is cured by cooling, cutting the synthetic resin and the chip substrate between the adjacent semiconductor chips, each having at least 1 A method of manufacturing a semiconductor device for obtaining individual semiconductor devices including two semiconductor chips, wherein a metal material having a small coefficient of thermal expansion or a negative value is previously formed on the chip substrate except for a fixing portion of the semiconductor chip. After the plate body is extended and adhered and fixed to the chip substrate, the synthetic resin is filled, and the cured synthetic resin and the chip substrate are cut. It is characterized by cutting so that it does not contain the plate member to each of said semiconductor device.

【００１４】このように、本発明の半導体装置の製造方
法では、半導体チップが固定されている箇所を除くチッ
プ基板上の領域に、熱膨張率が小さいか、または負値で
ある金属材料の板体をあらかじめ延在させてチップ基板
に接着固定しておくので、チップ基板が金属材料の板体
により補強され、充填する合成樹脂の熱膨張率が大きい
場合でも、合成樹脂が硬化した際のチップ基板の反りは
大幅に緩和される。そのため、半田ボールによりプリン
ト基板と接合する場合の接合不良発生の問題を解決する
ことができる。また、合成樹脂およびチップ基板を切断
する際は、個々の半導体装置に板体が含まれないように
切断するので、半導体装置が大型化したり、重量が増す
ことはなく、本半導体装置を使用する装置の小型・軽量
化に有利である。As described above, according to the method of manufacturing a semiconductor device of the present invention, a metal material plate having a small coefficient of thermal expansion or a negative value is provided in a region on a chip substrate except for a portion where a semiconductor chip is fixed. Since the body is extended and fixed to the chip substrate by bonding, the chip substrate is reinforced by a metal plate, and even when the synthetic resin to be filled has a large coefficient of thermal expansion, the chip when the synthetic resin is cured Substrate warpage is greatly reduced. Therefore, it is possible to solve the problem of the occurrence of defective bonding when bonding to a printed circuit board with solder balls. Further, when cutting the synthetic resin and the chip substrate, each semiconductor device is cut so as not to include a plate, so that the semiconductor device is used without increasing the size or increasing the weight. This is advantageous for reducing the size and weight of the device.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の製造方法により製造したチップ基板切
断前の半導体装置の一例を示す断面側面図である。FIG. 1 is a sectional side view showing an example of a semiconductor device before cutting a chip substrate manufactured by a manufacturing method of the present invention.

【図２】本発明の製造方法により製造したチップ基板切
断後の半導体装置の一例を示す断面側面図である。FIG. 2 is a sectional side view showing an example of a semiconductor device after cutting a chip substrate manufactured by the manufacturing method of the present invention.

【符号の説明】 ２……チップ基板、４……半導体チップ、６……接着
剤、８……開口、１０……パターン、１２……板体、１
４……端子、１６……ワイヤ、１８……合成樹脂、２０
……半導体装置、２２……プリント基板、２４……パタ
ーン、２６……半田ボール。[Description of Signs] 2 ... Chip substrate, 4 ... Semiconductor chip, 6 ... Adhesive, 8 ... Opening, 10 ... Pattern, 12 ... Plate body, 1
4 ... terminal, 16 ... wire, 18 ... synthetic resin, 20
... Semiconductor device, 22... Printed board, 24... Pattern, 26... Solder ball.

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】 合成樹脂から成るチップ基板上に、相互
に間隔をおいて複数の半導体チップを接着固定し、少な
くとも前記半導体チップの周辺の前記チップ基板上に、
加熱して流動状態の前記合成樹脂を充填し、充填した前
記合成樹脂が冷却により硬化した後、隣接する前記半導
体チップの間で前記合成樹脂および前記チップ基板を切
断して、それぞれが少なくとも１つの前記半導体チップ
を含む個々の半導体装置を得る半導体装置の製造方法で
あって、 あらかじめ前記半導体チップの固定箇所を除く前記チッ
プ基板上に、熱膨張率が小さいか、または負値である金
属材料の板体を延在させて前記チップ基板に接着固定し
た上で、前記合成樹脂を充填し、 硬化した前記合成樹脂および前記チップ基板を切断する
際は、個々の前記半導体装置に前記板体が含まれないよ
うに切断することを特徴とする半導体装置の製造方法。A plurality of semiconductor chips are bonded and fixed on a chip substrate made of a synthetic resin at intervals from each other, and at least on the chip substrate around the semiconductor chip,
After heating and filling the synthetic resin in a fluidized state, and after the filled synthetic resin is cured by cooling, the synthetic resin and the chip substrate are cut between the adjacent semiconductor chips, and each is at least one. A method of manufacturing a semiconductor device for obtaining an individual semiconductor device including the semiconductor chip, comprising: forming a metal material having a small coefficient of thermal expansion or a negative value on the chip substrate excluding a fixing portion of the semiconductor chip in advance; When the plate body is extended and bonded and fixed to the chip substrate and then filled with the synthetic resin and the cured synthetic resin and the chip substrate are cut, the individual semiconductor devices include the plate body. A method for manufacturing a semiconductor device, comprising cutting the semiconductor device so that the semiconductor device is not cut. 【請求項２】 前記板体はアンバであることを特徴とす
る請求項１記載の半導体装置の製造方法。2. The method according to claim 1, wherein said plate is made of Invar. 【請求項３】 前記板体は前記半導体チップを囲んで延
在させることを特徴とする請求項１記載の半導体装置の
製造方法。3. The method according to claim 1, wherein the plate extends around the semiconductor chip. 【請求項４】 前記チップ基板には開口が形成されると
ともに、前記半導体チップと反対側の下面に導電性材料
から成るパターンが被着されており、前記半導体チップ
の端子と前記パターンとは、前記開口を通じて敷設した
導電性材料から成るワイヤにより接続することを特徴と
する請求項１記載の半導体装置の製造方法。4. An opening is formed in the chip substrate, and a pattern made of a conductive material is adhered to a lower surface opposite to the semiconductor chip, wherein terminals of the semiconductor chip and the pattern are 2. The method according to claim 1, wherein the connection is made by a wire made of a conductive material laid through the opening. 【請求項５】 前記チップ基板の前記開口および前記ワ
イヤの周辺箇所にも前記合成樹脂を充填する一方、前記
パターンは前記チップ基板の下面において少なくとも一
部を露出させることを特徴とする請求項４記載の半導体
装置の製造方法。5. The pattern according to claim 4, wherein the synthetic resin is also filled in the openings of the chip substrate and the peripheral portions of the wires, while the pattern exposes at least a part of the lower surface of the chip substrate. The manufacturing method of the semiconductor device described in the above. 【請求項６】 前記チップ基板はガラスエポキシ樹脂に
より形成されていることを特徴とする請求項１記載の半
導体装置の製造方法。6. The method according to claim 1, wherein the chip substrate is formed of a glass epoxy resin. 【請求項７】 前記チップ基板はフィルム状に形成され
ていることを特徴とする請求項１記載の半導体装置の製
造方法。7. The method according to claim 1, wherein the chip substrate is formed in a film shape.
JP2000140714A 2000-05-12 2000-05-12 Manufacturing method of semiconductor device Pending JP2001326236A (en)

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