JP2001326236A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

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Publication number
JP2001326236A
JP2001326236A JP2000140714A JP2000140714A JP2001326236A JP 2001326236 A JP2001326236 A JP 2001326236A JP 2000140714 A JP2000140714 A JP 2000140714A JP 2000140714 A JP2000140714 A JP 2000140714A JP 2001326236 A JP2001326236 A JP 2001326236A
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JP
Japan
Prior art keywords
chip
synthetic resin
chip substrate
semiconductor device
semiconductor
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP2000140714A
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Japanese (ja)
Inventor
Naoto Kimura
直人 木村
Original Assignee
Nec Kyushu Ltd
九州日本電気株式会社
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Application filed by Nec Kyushu Ltd, 九州日本電気株式会社 filed Critical Nec Kyushu Ltd
Priority to JP2000140714A priority Critical patent/JP2001326236A/en
Publication of JP2001326236A publication Critical patent/JP2001326236A/en
Application status is Pending legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

PROBLEM TO BE SOLVED: To prevent the warpage of a semiconductor device caused by synthetic resin sealing.
SOLUTION: On a chip substrate 2 made of a synthetic resin, a plurality of semiconductor chips 4 are mutually bonded and fixed at intervals. On the chip substrate 2 around at least each semiconductor chip 4, a synthetic resin 18 that is heated for fluidizing is filled. After the filled synthetic resin 18 is cooled for curing, the synthetic resin 18 and the chip substrate 2 are cut between adjacent semiconductor chips 4 for obtaining each semiconductor device 20. At that time, on a region on the chip substrate 2 other than a place where the semiconductor chip 4 is fixed, an invar plate 12 where a coefficient of thermal expansion is small or negative is extended for bonding and fixing to the chip substrate 2 in advance. The synthetic resin 18 after the curing and chip substrate 2 is cut so that the plate 12 is not included in each semiconductor device 20.
COPYRIGHT: (C)2001,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は半導体装置の製造方法に関し、特にチップ基板上に配置した半導体チップを合成樹脂により封止する工程を含む半導体装置の製造方法に関するものである。 The present invention relates to relates to a method of manufacturing a semiconductor device, a method for manufacturing a semiconductor device comprising the step of sealing the particular semiconductor chip arranged on the chip substrate of a synthetic resin.

【0002】 [0002]

【従来の技術】半導体チップの1つの実装形態として、 One implementation of a semiconductor chip,
合成樹脂から成るチップ基板上に半導体チップを接着固定し、半導体チップの周辺あるいは全体を合成樹脂により封止する方式が用いられる。 The semiconductor chip on a chip substrate made of synthetic resin is bonded and fixed, a method of sealing is used a peripheral or whole of the semiconductor chip by a synthetic resin. 半導体チップを封止するための合成樹脂は、加熱して溶融させ、流動状態にして半導体チップ周辺などに供給される。 Synthetic resin for sealing the semiconductor chip, heated to melt, supplied like the semiconductor chip periphery in a fluid state. そして、合成樹脂の温度が低下し、硬化した段階で各半導体チップごとに個々の半導体装置とすべく合成樹脂およびチップ基板が切断される。 Then, the temperature of the synthetic resin is reduced, cured stage synthetic resin and the chip substrate so as to the individual semiconductor devices in each semiconductor chip is cut.

【0003】 [0003]

【発明が解決しようとする課題】ところで、チップ基板、チップ、ならびに封止用の合成樹脂はそれぞれ熱膨張率が異なり、特に封止用の合成樹脂は冷却時の収縮率が大きいため、バイメタルの変形と同じ原理で、チップ基板全体は、チップ基板側に凸の状態で反ったものとなってしまう。 [SUMMARY OF THE INVENTION Incidentally, different chip substrate, chip, and each synthetic resin thermal expansion coefficient of the sealing, particularly for the synthetic resin for sealing has a large cooling time shrinkage, bimetallic the same principle as modified, the entire chip substrate, becomes that warped in the form of convex to the chip substrate. このような反りは切断前のみならず、切断により個々の半導体装置とした状態でも生じており、その結果、半導体装置をプリント基板に搭載して半田ボールにより接合する場合に、半田ボールとの間に隙間が生じるなどして接合不良を引き起こすことがある。 Such warping not only prior to cutting, the cutting has occurred even in a state where the individual semiconductor devices by, as a result, in the case of bonding by the solder balls by mounting a semiconductor device on a printed circuit board, between the solder balls it may cause to bonding failure such gap is formed.

【0004】本発明はこのような問題を解決するためになされたもので、その目的は、合成樹脂封止に伴う半導体装置の反りを防止できる半導体装置の製造方法を提供することにある。 [0004] The present invention has been made in order to solve such problems, and its object is to provide a method of manufacturing a semiconductor device capable of preventing the warpage of the semiconductor device with a synthetic resin encapsulation.

【0005】 [0005]

【課題を解決するための手段】本発明は、上記目的を達成するため、合成樹脂から成るチップ基板上に、相互に間隔をおいて複数の半導体チップを接着固定し、少なくとも前記半導体チップの周辺の前記チップ基板上に、加熱して流動状態の前記合成樹脂を充填し、充填した前記合成樹脂が冷却により硬化した後、隣接する前記半導体チップの間で前記合成樹脂および前記チップ基板を切断して、それぞれが少なくとも1つの前記半導体チップを含む個々の半導体装置を得る半導体装置の製造方法であって、あらかじめ前記半導体チップの固定箇所を除く前記チップ基板上に、熱膨張率が小さいか、または負値である金属材料の板体を延在させて前記チップ基板に接着固定した上で、前記合成樹脂を充填し、硬化した前記合成樹脂および前記 The present invention SUMMARY OF THE INVENTION In order to achieve the above object, on a chip substrate made of synthetic resin mutually at intervals and adhere the plurality of semiconductor chips, at least the periphery of said semiconductor chip wherein the chip on the substrate, heated to filling the synthetic resin in a fluid state, after filled the synthetic resin is hardened by cooling, and cutting the synthetic resin and the chip substrate between said semiconductor chip adjacent Te, each method for manufacturing a semiconductor device for obtaining individual semiconductor device comprising at least one of said semiconductor chip, on said chip substrate in advance except for the fixing portion of the semiconductor chip, or the thermal expansion coefficient is small, or after having bonded and fixed to the chip substrate by extending a plate of metal material is a negative value, filling the synthetic resin, cured the synthetic resin and the ップ基板を切断する際は、個々の前記半導体装置に前記板体が含まれないように切断することを特徴とする。 When cutting the-up substrate, wherein the cutting so that it does not contain the plate member to each of said semiconductor device.

【0006】このように、本発明の半導体装置の製造方法では、半導体チップが固定されている箇所を除くチップ基板上の領域に、熱膨張率が小さいか、または負値である金属材料の板体をあらかじめ延在させてチップ基板に接着固定しておくので、チップ基板が金属材料の板体により補強され、充填する合成樹脂の熱膨張率が大きい場合でも、合成樹脂が硬化した際のチップ基板の反りは大幅に緩和される。 [0006] Thus, in the manufacturing method of the semiconductor device of the present invention, the area on the chip substrate except the portion where the semiconductor chip is fixed, a plate of metallic material is either thermal expansion coefficient is small or negative value since by Zaisa previously extended the body keep bonded to the chip substrate, the chip substrate is reinforced by a plate of a metal material, even if the thermal expansion coefficient of the synthetic resin to be filled is large, the chip when the synthetic resin has cured warping of the substrate is greatly reduced. そのため、半田ボールによりプリント基板と接合する場合の接合不良発生の問題を解決することができる。 Therefore, it is possible to solve the problem of bonding failure when bonded to the printed circuit board by solder balls. また、合成樹脂およびチップ基板を切断する際は、個々の半導体装置に板体が含まれないように切断するので、半導体装置が大型化したり、重量が増すことはなく、本半導体装置を使用する装置の小型・軽量化に有利である。 Also, when cutting the synthetic resin and the chip substrate, since the cut so that it does not contain plate member into individual semiconductor device, a semiconductor device or size, rather than the weight increase, to use the semiconductor device which is advantageous in size and weight of the device.

【0007】 [0007]

【発明の実施の形態】次に本発明の実施の形態例について図面を参照して説明する。 Embodiment examples of the embodiment of the invention] the present invention will now be described with reference to the drawings. 図1は本発明の製造方法により製造したチップ基板切断前の半導体装置の一例を示す断面側面図、図2は本発明の製造方法により製造したチップ基板切断後の半導体装置の一例を示す断面側面図である。 Figure 1 is a sectional side view showing an example of a semiconductor device before the chip substrate cleavage produced by the production method of the present invention, cross-sectional side of an example of FIG. 2 is a semiconductor device after the chip substrate cleavage produced by the production method of the present invention it is a diagram. 本実施の形態例では、まず、一例としてガラスエポキシ樹脂から成るチップ基板2上に、相互に間隔をおいて複数の半導体チップ4を接着剤6により接着固定する。 In this embodiment, first, on the chip substrate 2 made of a glass epoxy resin as an example, another at intervals adhering fixing a plurality of semiconductor chips 4 by the adhesive 6. より具体的には、半導体チップ4は平面視略矩形であり、このような半導体チップ4をチップ基板2上にマトリクス状に配置して固定する。 More specifically, the semiconductor chip 4 is substantially rectangular in plan view, to secure such a semiconductor chip 4 arranged in a matrix on the chip substrate 2. また、チップ基板2 In addition, the chip substrate 2
には半導体チップ4の配置個所近傍に開口8が形成されるとともに、半導体チップ4と反対側の面、すなわち下面には導電性材料から成るパターン10が被着されている。 The an opening 8 is formed near placement location of the semiconductor chip 4, the opposite surface to the semiconductor chip 4, i.e. the lower surface pattern 10 of conductive material have been deposited.

【0008】その後、半導体チップ4が固定されている箇所を除くチップ基板2上の領域に、熱膨張率が小さいか、または負値である金属材料としてアンバ(または超アンバ)の板体12を延在させてチップ基板2に接着固定する。 [0008] Then, the region on the chip substrate 2 except the portion where the semiconductor chip 4 is fixed, the plate member 12 of the Amba (or super invar) as metallic material which is either a thermal expansion coefficient is small or negative value by extending fixedly bonded to the chip substrate 2. この板体12は本実施の形態例では、各半導体チップ4を囲み、縦横の格子状に延在させる。 In the embodiment of the plate member 12 is present, surrounding the respective semiconductor chips 4, extend in the vertical and horizontal grid pattern. ここで、 here,
板体12の寸法としては、幅はたとえば2mm程度、厚みはたとえば50μm〜100μm程度とすることで良好な結果を得ることができる。 The dimensions of the plate member 12, the width, for example about 2mm, thickness can be obtained good results by, for example 50μm~100μm about.

【0009】つづいて、半導体チップ4の端子14とパターン10とを、開口8を通じて敷設した導電性材料から成るワイヤ16により接続する。 [0009] Subsequently, the terminal 14 and the pattern 10 of the semiconductor chip 4 are connected by wire 16 made of laying the conductive material through the opening 8. その後、本実施の形態例では一例として半導体チップ4の周辺のチップ基板2上に、加熱して流動状態の合成樹脂18を充填する。 Thereafter, on the periphery of the chip substrate 2 of the semiconductor chip 4 as an example in the present embodiment, heating to fill the synthetic resin 18 in a fluid state.
ここで、合成樹脂18は、図1に示したように、チップ基板2の下面側も含め、チップ基板2の開口8およびワイヤ16の周辺箇所にも充填する。 Here, the synthetic resin 18, as shown in FIG. 1, including the lower surface of the chip substrate 2, also filled around portions of the opening 8 and the wire 16 of the chip substrate 2. ただし、チップ基板2の下面に形成されたパターン10の箇所は少なくとも一部を露出させておく。 However, portions of the pattern 10 formed on the lower surface of the chip substrate 2 is allowed to expose at least a portion.

【0010】そして、充填した合成樹脂18が冷却により硬化した後、隣接する半導体チップ4の間で合成樹脂18およびチップ基板2を切断して、それぞれが1つの半導体チップ4を含む個々の半導体装置20を得る。 [0010] After the synthetic resin 18 filled is hardened by cooling, by cutting the synthetic resin 18 and the chip substrate 2 between the adjacent semiconductor chips 4, each individual semiconductor device including a single semiconductor chip 4 get a 20. ここで、合成樹脂18およびチップ基板2を切断する際には、個々の半導体装置20に板体12が含まれないように切断し、したがって切断後の半導体装置20は図2に示したようなものとなる。 Here, when cutting the synthetic resin 18 and the chip substrate 2, such as to cut so that it does not contain plate member 12 into individual semiconductor devices 20, thus the semiconductor device 20 after the cutting are shown in FIG. 2 the things. 作製した半導体装置20は、 Semiconductor device 20 was fabricated,
図2に示したように、プリント基板22上のパターン2 As shown in FIG. 2, the pattern 2 on the printed board 22
4とチップ基板2下面のパターン10との間に半田ボール26を介在させた状態で、加熱により半田ボール26 4 and in a state in which the solder ball 26 is interposed between the chip substrate 2 the lower surface of the pattern 10, the solder by heating ball 26
を溶融させ、パターン10とパターン24とを接合する。 It was melted, bonding the patterns 10 and 24.

【0011】そして、本実施の形態例では、上述のように、半導体チップ4が固定されている箇所を除くチップ基板2上の領域にアンバの板体12を、あらかじめ延在させてチップ基板2に接着固定しておくので、チップ基板2が金属材料の板体12により補強され、充填する合成樹脂18の熱膨張率が大きい場合でも、合成樹脂18 [0011] In the present embodiment, as described above, the amber plate member 12 in the area on the chip substrate 2 except the portion where the semiconductor chip 4 is fixed, the chip substrate 2 by Zaisa pre-rolled because keep bonded to the chip substrate 2 is reinforced by the plate member 12 of metallic material, even when the thermal expansion coefficient of the synthetic resin 18 to be filled is large, the synthetic resin 18
が硬化した際のチップ基板2の反りは大幅に緩和される。 There warpage of the chip substrate 2 when cured is significantly mitigated. そのため、半田ボール26によりプリント基板22 Therefore, printed circuit board 22 by solder balls 26
と接合する場合の接合不良発生の問題を解決することができる。 It is possible to solve the problem of bonding failure when bonded to the. また、合成樹脂18およびチップ基板2を切断する際は、個々の半導体装置20に板体12が含まれないように切断するので、半導体装置20が大型化したり、重量が増すことはなく、本半導体装置を使用する装置の小型・軽量化に有利である。 Also, when cutting the synthetic resin 18 and the chip substrate 2, since the cut so that it does not contain plate member 12 into individual semiconductor devices 20, or the size of the semiconductor device 20 is not the weight is increased, the which is advantageous in size and weight of the device using a semiconductor device.

【0012】なお、本実施の形態例では、チップ基板2 [0012] Incidentally, in this embodiment, the chip substrate 2
はガラスエポキシ樹脂により形成されているとしたが、 Although a is formed by a glass epoxy resin,
チップ基板2が合成樹脂によりフィルム状に形成されている場合にも本発明は無論有効である。 Also the present invention when the chip substrate 2 is formed into a film of synthetic resin is of course effective. また、合成樹脂18は半導体チップ4の周辺に限らず、半導体チップ4 Further, the synthetic resin 18 is not limited to the periphery of the semiconductor chip 4, the semiconductor chip 4
の上部にも充填してよく、その場合にも同様に板体12 It may be also filled into the upper, as well when the plate body 12
の作用によりチップ基板2の反りを防止できる。 It can prevent warpage of the chip substrate 2 by the action.

【0013】 [0013]

【発明の効果】以上説明したように本発明は、合成樹脂から成るチップ基板上に、相互に間隔をおいて複数の半導体チップを接着固定し、少なくとも前記半導体チップの周辺の前記チップ基板上に、加熱して流動状態の前記合成樹脂を充填し、充填した前記合成樹脂が冷却により硬化した後、隣接する前記半導体チップの間で前記合成樹脂および前記チップ基板を切断して、それぞれが少なくとも1つの前記半導体チップを含む個々の半導体装置を得る半導体装置の製造方法であって、あらかじめ前記半導体チップの固定箇所を除く前記チップ基板上に、熱膨張率が小さいか、または負値である金属材料の板体を延在させて前記チップ基板に接着固定した上で、前記合成樹脂を充填し、硬化した前記合成樹脂および前記チップ基板を切断する The present invention described above, according to the present invention has, on a chip substrate made of synthetic resin mutually at intervals and adhere the plurality of semiconductor chips, on the chip substrate near at least said semiconductor chip , heated to filling the synthetic resin in a fluid state, after filled the synthetic resin is hardened by cooling, and cutting the synthetic resin and the chip substrate between the semiconductor chips adjacent each of at least 1 one of the method for manufacturing a semiconductor device for obtaining individual semiconductor device including a semiconductor chip, a metal material in advance the on the chip substrate except the fixed portion of the semiconductor chip, or the thermal expansion coefficient is small or negative value in terms of of the plate member is extended and bonded to the chip substrate, the synthetic resin is filled, cutting the synthetic resin and the chip substrate and cured は、個々の前記半導体装置に前記板体が含まれないように切断することを特徴とする。 It is characterized by cutting so that it does not contain the plate member to each of said semiconductor device.

【0014】このように、本発明の半導体装置の製造方法では、半導体チップが固定されている箇所を除くチップ基板上の領域に、熱膨張率が小さいか、または負値である金属材料の板体をあらかじめ延在させてチップ基板に接着固定しておくので、チップ基板が金属材料の板体により補強され、充填する合成樹脂の熱膨張率が大きい場合でも、合成樹脂が硬化した際のチップ基板の反りは大幅に緩和される。 [0014] Thus, in the manufacturing method of the semiconductor device of the present invention, the area on the chip substrate except the portion where the semiconductor chip is fixed, a plate of metallic material is either thermal expansion coefficient is small or negative value since by Zaisa previously extended the body keep bonded to the chip substrate, the chip substrate is reinforced by a plate of a metal material, even if the thermal expansion coefficient of the synthetic resin to be filled is large, the chip when the synthetic resin has cured warping of the substrate is greatly reduced. そのため、半田ボールによりプリント基板と接合する場合の接合不良発生の問題を解決することができる。 Therefore, it is possible to solve the problem of bonding failure when bonded to the printed circuit board by solder balls. また、合成樹脂およびチップ基板を切断する際は、個々の半導体装置に板体が含まれないように切断するので、半導体装置が大型化したり、重量が増すことはなく、本半導体装置を使用する装置の小型・軽量化に有利である。 Also, when cutting the synthetic resin and the chip substrate, since the cut so that it does not contain plate member into individual semiconductor device, a semiconductor device or size, rather than the weight increase, to use the semiconductor device which is advantageous in size and weight of the device.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の製造方法により製造したチップ基板切断前の半導体装置の一例を示す断面側面図である。 1 is a cross-sectional side view showing an example of a semiconductor device before the chip substrate cleavage produced by the production method of the present invention.

【図2】本発明の製造方法により製造したチップ基板切断後の半導体装置の一例を示す断面側面図である。 2 is a cross-sectional side view showing an example of a semiconductor device after the chip substrate cleavage produced by the production method of the present invention.

【符号の説明】 2……チップ基板、4……半導体チップ、6……接着剤、8……開口、10……パターン、12……板体、1 [Reference Numerals] 2 ...... chip substrate, 4 ...... semiconductor chip, 6 ...... adhesives, 8 ...... opening, 10 ...... pattern, 12 ...... plate member, 1
4……端子、16……ワイヤ、18……合成樹脂、20 4 ...... terminal, 16 ...... wire, 18 ...... synthetic resin, 20
……半導体装置、22……プリント基板、24……パターン、26……半田ボール。 ...... semiconductor device, 22 ...... PCB, 24 ...... pattern, 26 ...... solder balls.

Claims (7)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 合成樹脂から成るチップ基板上に、相互に間隔をおいて複数の半導体チップを接着固定し、少なくとも前記半導体チップの周辺の前記チップ基板上に、 To 1. A chip substrate made of synthetic resin mutually at intervals and adhere the plurality of semiconductor chips, on the chip substrate near at least the semiconductor chip,
    加熱して流動状態の前記合成樹脂を充填し、充填した前記合成樹脂が冷却により硬化した後、隣接する前記半導体チップの間で前記合成樹脂および前記チップ基板を切断して、それぞれが少なくとも1つの前記半導体チップを含む個々の半導体装置を得る半導体装置の製造方法であって、 あらかじめ前記半導体チップの固定箇所を除く前記チップ基板上に、熱膨張率が小さいか、または負値である金属材料の板体を延在させて前記チップ基板に接着固定した上で、前記合成樹脂を充填し、 硬化した前記合成樹脂および前記チップ基板を切断する際は、個々の前記半導体装置に前記板体が含まれないように切断することを特徴とする半導体装置の製造方法。 Heated to filling the synthetic resin in a fluid state, after filled the synthetic resin is hardened by cooling, and cutting the synthetic resin and the chip substrate between the semiconductor chips adjacent respectively at least one the method of manufacturing a semiconductor device for obtaining individual semiconductor device including a semiconductor chip, on said chip substrate in advance except for the fixing portion of the semiconductor chip, or the thermal expansion coefficient is small, or the metallic material is a negative value after having bonded and fixed to the chip substrate by extending the plate body, the synthetic resin was filled, when cured cutting the synthetic resin and the chip substrate, the plate member is included in each of the semiconductor device the method of manufacturing a semiconductor device characterized by cutting so as not to.
  2. 【請求項2】 前記板体はアンバであることを特徴とする請求項1記載の半導体装置の製造方法。 2. A method for manufacturing a plate body semiconductor device according to claim 1, wherein it is invar.
  3. 【請求項3】 前記板体は前記半導体チップを囲んで延在させることを特徴とする請求項1記載の半導体装置の製造方法。 3. A method according to claim 1, wherein said plate member, characterized in that the extend surrounds the semiconductor chip.
  4. 【請求項4】 前記チップ基板には開口が形成されるとともに、前記半導体チップと反対側の下面に導電性材料から成るパターンが被着されており、前記半導体チップの端子と前記パターンとは、前記開口を通じて敷設した導電性材料から成るワイヤにより接続することを特徴とする請求項1記載の半導体装置の製造方法。 An opening is formed in the method according to claim 4, wherein the chip substrate, the semiconductor chip and the lower surface of a conductive material pattern on the opposite side has been deposited, the terminal and the pattern of the semiconductor chip, the method according to claim 1, wherein the connecting by a wire made of a conductive material laid through the opening.
  5. 【請求項5】 前記チップ基板の前記開口および前記ワイヤの周辺箇所にも前記合成樹脂を充填する一方、前記パターンは前記チップ基板の下面において少なくとも一部を露出させることを特徴とする請求項4記載の半導体装置の製造方法。 While wherein in peripheral portions of the opening and the wire of the chip substrate to fill the synthetic resin, according to claim wherein the pattern is characterized by exposing at least part in a lower surface of the chip substrate 4 the method of manufacturing a semiconductor device according.
  6. 【請求項6】 前記チップ基板はガラスエポキシ樹脂により形成されていることを特徴とする請求項1記載の半導体装置の製造方法。 Wherein said chip substrate manufacturing method of a semiconductor device according to claim 1, characterized in that it is formed of glass epoxy resin.
  7. 【請求項7】 前記チップ基板はフィルム状に形成されていることを特徴とする請求項1記載の半導体装置の製造方法。 Wherein said chip substrate manufacturing method of a semiconductor device according to claim 1, characterized in that it is formed into a film.
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