JPH118335A - Circuit board, manufacture thereof, and manufacturing semiconductor package using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a semiconductor chip which is parallel to the top face of a chip mounting region by positioning at least three casing legs having equal heights, so that the gravity center of the chip agrees with the center of the mounting region at mounting of the chip. SOLUTION: A semiconductor chip 30 is mounted on a flexible printed circuit board 10a with at least three casing legs 90 having equal heights which are positioned, so that the weight center of the chip 30 agrees with the center of a semiconductor chip-mounting region 25. The chip 30 contacts at the bottom to the tops of the legs 30, a liq. epoxy resin is filled in a space between the bottom of the chip 30 and a mounting region 35, the space has the same height as that of the legs 90 having equal heights, hence the resin hardens to form an adhesive layer 40 having precisely identical thickness, thereby forming the chip parallel with respect to the top face of the chip-mounting region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board, a method for manufacturing the same, and a method for manufacturing a semiconductor package using the same. The present invention relates to a circuit board having the same, a method of manufacturing the same, and a method of manufacturing a semiconductor package using the same.

[0002]

2. Description of the Related Art Conventionally, a QFP (Q
uad Flat Semiconductor Package) or Chip Scale Semiconductor Packag
e) or a ball grid array semiconductor package using a rigid printed circuit board or a flexible printed circuit board (B
all Grid Array Semiconductor Package)
Since the semiconductor chip mounting area on the semiconductor chip supporting plate of the lead frame or the printed circuit board has a smooth surface structure, the semiconductor chip and the smooth surface are bonded when the semiconductor chip is bonded after dispensing the liquid adhesive resin on the upper surface. There has been a problem that it is extremely difficult to adhere in an exactly parallel state.

Accordingly, in a high temperature process in a semiconductor package manufacturing process subsequent to a semiconductor chip mounting process, for example, in a high temperature environment such as a resin encapsulation molding process, a wire bonding process, and / or a solder ball fusion process. Alternatively, in a heating environment during operation of the completed semiconductor package, thermal stress is concentrated on the bonding interface due to a relatively large difference in thermal expansion coefficient between the lead frame or the printed circuit board and the semiconductor chip, and the bonding layer When the thickness is not uniform, a cohesion concentration phenomenon appears in a portion where the adhesive force is relatively weak, and there is a high possibility that an interface peeling phenomenon will occur from that portion. When such an interface separation phenomenon appears, heat is not efficiently dissipated during operation of the semiconductor chip and is locally biased, and moisture can easily penetrate, so that the performance of the semiconductor chip deteriorates and defects occur. This causes a problem, and when such a problem becomes serious, a bending phenomenon or a bonding wire breaking phenomenon of the semiconductor package appears.

FIG. 16A shows a conventional printed circuit board 10 '.
FIG. 16 is a cross-sectional view showing a mounting state of a semiconductor chip 30 by taking a conventional ball grid array semiconductor package 1 ′ using FIG. 16 as an example, showing that the thickness of an adhesive layer 40 is not uniform; FIG. 16B shows an adhesive layer 4 having an uneven thickness in the semiconductor package of FIG.
FIG. 9 is an exemplary cross-sectional view showing an interface peeling phenomenon (see the reference numeral 45 in the drawing) and a breaking phenomenon of the bonding wire 50 which may be caused by 0.

[0005]

Accordingly, the first aspect of the present invention is as follows.
An object is to easily position a semiconductor chip in a completely parallel state with respect to an upper surface of a semiconductor chip mounting area when mounting the semiconductor chip on a semiconductor chip mounting area of a circuit board using a liquid adhesive resin. It is to provide a circuit board.

A second object of the present invention is to provide a method of manufacturing a circuit board according to the first object of the present invention.

A third object of the present invention is to mount a semiconductor chip on a semiconductor chip mounting area of a circuit board with a strictly uniform bonding thickness, thereby effectively suppressing an interface peeling phenomenon at the bonding portion. It is an object of the present invention to provide a method of manufacturing a semiconductor package using a circuit board according to the first object of the present invention, which can improve quality reliability.

[0008]

In order to achieve the above object, a circuit board according to the present invention comprises a semiconductor chip mounting area and a plurality of circuits formed on an outer peripheral edge of the circuit board at a distance from the semiconductor chip mounting area. And at least three casing legs having a uniform height for uniformly controlling the thickness of the adhesive layer on an upper surface of the semiconductor chip mounting area in the circuit board including the input / output terminal portions, The casing leg is positioned so that the center of the weight of the semiconductor chip and the center of the semiconductor chip mounting area coincide with each other when the semiconductor chip is mounted.

The height of the casing legs is 0.5 to 0.5.
It is characterized by being formed at a height of 3 mils.

[0010] Further, the invention is characterized in that the casing legs are formed as a solder mask.

In addition, a circuit board is formed in a resin substrate, an outer peripheral region of an upper surface of the resin board, and a plurality of conductive traces as a circuit having a wire bonding portion at an inner end thereof; A plurality of via holes formed in the resin substrate, and formed in a region adjacent to the via hole on a bottom surface of the resin substrate, and electrically connected to the conductive trace on an upper surface of the resin substrate. A plurality of solder ball lands, a semiconductor chip mounting area at the center of the resin substrate, an insulating solder mask formed on upper and lower surfaces of the resin substrate excluding the solder ball lands and the wire bonding portion, and a semiconductor chip. Rigid printed circuit composed of a plurality of casing legs of uniform height formed on an insulating solder mask on the mounting area Characterized in that it is a plate.

A circuit board is formed in a flexible resin board and a plurality of conductive traces as a circuit formed in an outer peripheral area of the upper surface of the flexible resin board and having a wire bonding portion at an inner end thereof. A plurality of solder ball lands electrically connected to the conductive traces on the upper surface of the resin substrate; a semiconductor chip mounting region at the center of the resin substrate; and a plurality of casing legs formed on the semiconductor chip mounting region. And a flexible printed circuit board comprising:

A circuit board supports the semiconductor chip support plate, the plurality of tie bars having the downset portion formed thereon, and a circuit formed on an outer peripheral edge of the semiconductor chip support plate. A lead frame comprising: a plurality of linear leads; a plurality of tie bars; a dam bar supporting the plurality of leads; and a plurality of casing legs formed on the semiconductor chip support plate. Features.

The circuit board has a bent portion on the same plane, and a plurality of leads as circuits divided into a plurality of groups having different depths extending into the semiconductor chip mounting region; A dam bar for supporting an outer end of each of the leads, and a lead end formed to have an extended area at an inner end of each of the plurality of leads, and having a protruding end as an input / output terminal at a bottom central portion thereof. And a plurality of casing legs formed on the upper surface of the selected lead end located in the semiconductor chip mounting area.

Further, the lead end grid array frame has a bent portion on another plane.
(t) part. Also, the lead end grid array frame has a semiconductor chip support plate, the semiconductor chip support plate is supported by one end of a tie bar, the other end of the tie bar is supported by the dam bar, and a plurality of the casing legs are connected to the semiconductor leg. Not only the top surface of the selected lead end located in the chip mounting area,
It is also formed on the semiconductor chip support plate.

According to another aspect of the present invention, there is provided a method of manufacturing a circuit board, comprising the steps of: performing a masking step, an ultraviolet irradiation step, a phenomena step, and an etching step of a circuit board original plate in order; In the method for manufacturing a circuit board, after a circuit pattern forming step of forming the circuit board from a semiconductor chip mounting region, a plurality of circuits formed on an outer peripheral edge of the semiconductor chip mounting region at a distance from the semiconductor chip mounting region, and an input / output terminal portion Performing a casing leg forming step of forming at least three casing legs having a uniform height on the upper surface of the semiconductor chip mounting area to uniformly control the thickness of the adhesive layer, wherein the casing legs are connected to the semiconductor chip. It is preferable that the semiconductor chip is formed at a position such that the center of weight of the semiconductor chip and the center of the semiconductor chip mounting area coincide with each other during mounting. And butterflies.

Further, the height of the casing legs is set at 0.5 to 0.5.
It is characterized by being formed at a height of 3 mil.

Further, the invention is characterized in that the casing legs are formed as a solder mask.

Also, the original board for a circuit board is an original board for a printed circuit board in which a conductive metal thin film is coated on the upper and lower surfaces of a resin board, and a perforation for forming a via hole in the disc for the circuit board before a masking step. A (drilling) step and a plating step of forming a conductive metal plating layer on an inner peripheral surface of the via hole are sequentially performed, and are formed on an outer peripheral region of the upper surface of the resin substrate, electrically connected to the via hole, and inside the via hole. A plurality of conductive traces as a circuit having a wire bonding portion at an end; and a plurality of conductive traces formed in a region adjacent to the via hole on a bottom surface of the resin substrate and electrically connected to the conductive traces on a top surface of the resin substrate. After performing a circuit pattern forming step of forming a plurality of solder ball lands, the solder ball lands and the wire bonding are removed. Forming a solder mask on the upper and lower surfaces of the resin substrate.

Further, the semiconductor chip mounting area is formed by a die pad made of a conductive metal having a top surface coated with a solder mask.

Further, the original board for a circuit board is an original board for a printed circuit board in which a conductive metal thin film is coated on the upper surface of a flexible resin substrate, and the outer peripheral area of the upper surface of the flexible resin substrate is formed in a circuit pattern forming step. A plurality of conductive traces as a circuit having a wire bonding portion at an inner end thereof, and a plurality of solder ball lands electrically connected to the conductive traces and formed on the bottom surface of the resin substrate. It is characterized by being formed.

Further, a method for manufacturing a circuit board, wherein the original board for a circuit board is a conductive metal sheet and the circuit pattern forming step is constituted by the following steps: (A) A photoresist thin film is coated on the entire upper and lower surfaces of a conductive metal thin plate, and has a predetermined pattern including a plurality of lead regions having a lead end region having an expanded area, and an area smaller than the lead end region. (B) masking a photomask onto the photoresist thin film on the upper and lower surfaces so as to correspond to a predetermined pattern including a protruding end region located at the center of the lower surface of the lead end region; Irradiating the upper and lower surfaces of the conductive metal sheet with ultraviolet rays; (C) a phenomenon step of forming the predetermined lead pattern and the predetermined protruding end pattern on the upper and lower photoresist thin films, respectively; The portion between the lead regions which are not masked by both, and the lead region is fully etched. Of the lower surface area corresponding to the lead end region masked on the upper surface, the unmasked without the masked projecting end regions moiety is partially etched, etching step of patterning the conductive metal sheet.

Also, a semiconductor chip supporting plate is formed in a circuit pattern forming step, the semiconductor chip supporting plate is supported by the other end of a tie bar, one end of which is supported by a dam bar, and a plurality of the casing legs are mounted on the semiconductor chip. The semiconductor device is formed not only on the upper surface of the selected lead end located in the region but also on the semiconductor chip support plate.

In the masking step, the protruding end region is masked in a circular shape.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package, comprising: dispensing a liquid adhesive resin on a semiconductor chip mounting area of a circuit board; The upper surfaces of the plurality of casing legs formed at positions that match the center of the semiconductor chip mounting area are in contact with the bottom surface of the semiconductor chip, and the bottom surface of the semiconductor chip is limited by the height of the casing legs. A semiconductor chip mounting step of pressing and bonding the semiconductor chip so that the liquid adhesive resin is filled in a space between the semiconductor chip mounting area and the upper surface of the semiconductor chip mounting area without voids; An electrical connection step of electrically connecting the semiconductor chip and the conductive wire with each other by protecting the semiconductor chip and the conductive wire from an external environment. Characterized in that it is composed of a molding step of forming the resin sealing portion.

The method may further include, after the molding step, a solder ball fusing step of fusing solder balls as input / output terminals.

In the present specification, the term “circuit board” is used for a rigid or flexible printed circuit board and a quad flat semiconductor package or a chip scale used in a ball grid array semiconductor package unless otherwise specified. It is used to include all lead frames used for semiconductor packages and the like, and the term 'circuit' in this specification refers to conductive traces on a printed circuit board and leads of a lead frame unless otherwise specified. Used in the sense to include. In addition, the term 'semiconductor chip mounting area' in this specification refers to an area where a semiconductor chip is mounted so as to be in contact with a 'circuit board', and unless otherwise specified, a lead frame. Meaning including a semiconductor chip supporting plate, or a region including a semiconductor chip supporting plate and a certain area of leads, a die pad on a printed circuit board, or an area on a printed circuit board on which a semiconductor chip is mounted when a die pad is formed. Used in.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is an exemplary sectional view of a rigid printed circuit board 10 to which the present invention is applied. According to FIG. 1, a printed circuit board 10 is formed in an outer peripheral region of a top surface of a resin substrate 16 and a wire bonding portion 11 is attached to an inner end thereof.
a plurality of conductive traces 11 having a, a plurality of via holes 13 electrically connected to the conductive traces 11 and perforated in the resin substrate 16, and adjacent to the via holes 13 on the bottom surface of the resin substrate 16. A plurality of solder ball lands 15 formed in the region and electrically connected to the conductive traces 11 on the upper surface of the resin substrate 16; a semiconductor chip mounting region in the center of the resin substrate 16;
And the resin substrate 16 excluding the wire bonding portion 11a
And a plurality of casing legs 90 of uniform height formed on the insulating solder mask 14 on the semiconductor chip mounting area. In FIG. 1, the semiconductor chip mounting area is the die pad 1.
2 and a solder mask 14 coated on the upper surface thereof, such a die pad 12 is optional and not restrictive in the present invention.

When the semiconductor chip is mounted, the casing leg 90 is positioned between the center of the weight of the semiconductor chip and the semiconductor chip mounting area 25.
There is no special limitation on the number and position of the casing legs 90 as long as the condition that the centers of the casing legs 90 coincide is satisfied, but the number must be at least three or more. The shape is not particularly limited, but the height is preferably 0.5 to 3 mil. If the height is less than 0.5 mil, the height of the adhesive layer 40 formed when the liquid adhesive resin is cured by dispensing exceeds the height of the casing legs 90. If it exceeds 3 mils, the height of the adhesive layer 40 may not reach the height of the casing leg 90, and a void layer may be formed. Further, the material of the casing legs 90 may be any material such as metal or resin, and is not limited. However, it is preferable from the viewpoint of process efficiency to partially laminate the material using the same material as the solder mask.

The planar configuration of the printed circuit board 10 is basically the same as that shown in FIG. 2B, which will be described later.

FIG. 2A is an exemplary sectional view of a flexible printed circuit board 10a to which the present invention is applied. According to FIG. 2A, the flexible printed circuit board 10a has a thickness of 20 to 150.
A plurality of conductive traces 11 formed in an outer peripheral region of a flexible resin substrate 16 ′ having a wire bonding portion 11 a at an inner end thereof; Conductive trace 1
A plurality of solder ball lands 15 electrically connected to one
And a semiconductor chip mounting area 25 at the center of the resin substrate 16 '.
And a plurality of casing legs 90 formed on the semiconductor chip mounting area 25. Whether or not the die pad and the solder mask can be formed is optional and not restrictive in the present invention, and matters relating to the number, shape, and position of the casing legs 90 are the same as those described in FIG.

FIG. 2A shows a carrier frame 80 having a double-sided adhesive tape 42 on the outer periphery of the upper surface of the flexible circuit board 16 '.
Indicate a state in which they are attached, but these are not elements constituting the flexible circuit board 16 ′ of the present invention,
This is for maintaining the flexible circuit board 16 'in a rigid state in order to enhance the process efficiency in manufacturing the semiconductor package.

FIG. 2B is an exemplary plan view of the flexible printed circuit board 16 'to which the present invention is applied, in a state where the carrier frame 80 is not attached, and the semiconductor chip mounting area 25 at the center is shown.
4 shows an example in which four casing legs 90 are formed, and a plurality of conductive traces 11 on which a wire bonding portion 11a and a solder ball land 15 are formed are formed on the outer peripheral edge of the semiconductor chip mounting region 25. I have.

FIG. 3 is an exemplary plan view of the lead frame 20 to which the present invention is applied. According to FIG. 3, the lead frame 20 supports the semiconductor chip supporting plate 22 at the center thereof, the plurality of tie bars 23 supporting the semiconductor chip supporting plate 22 and the downset portion 234 formed, and the semiconductor chip supporting plate 2.
2, a plurality of linear leads 21 formed on the outer peripheral edge of
It comprises a plurality of tie bars 23, a dam bar 24 supporting the plurality of leads 21, and a plurality of casing legs 90 formed on the semiconductor chip support plate 22. Matters relating to the number, shape and position of the casing legs 90 are the same as those described in FIG.

FIGS. 4A and 4B are a plan view and a bottom view, respectively, of the lead end grid array lead frame 20a to which the present invention is applied, which will be described together for convenience.

The lead end grid array lead frame 20a has a bent portion 213 on the same plane, and a plurality of leads 21 divided into a plurality of groups having different lengths extending into the semiconductor chip mounting area 25. And a dam bar 24 for supporting each outer end of the plurality of leads 21, and an expanded area formed on each inner end of the plurality of leads 21. It comprises a lead end 211 having a functioning protruding end 212 and a plurality of casing legs 90 formed on the upper surface of the selected lead end 211 located in the semiconductor chip mounting area 25.

More specifically, in the lead frame 20a, a plurality of leads 21 divided into a plurality of groups having different lengths are bent on the same plane at the bent portion 213 and / or on another plane. Is bent at least once by a downset portion 214 (see FIG. 13), which is a bent portion of FIG. The down-set portion 214 is optional and is preferably formed at a position adjacent to the dam bar 24 to reduce the chip scale of the semiconductor package. One end of each of the plurality of leads 21 is supported by a dam bar 24, the other end is formed with a lead end 211 having an enlarged area, and a protruding end 212 functioning as an input / output terminal is formed at the bottom center. . The protruding end 212 is formed in the bottom area of the lead end 211 having an enlarged area, and its shape is not particularly limited, but a solder ball (see FIG. 15) is used as an input / output terminal when manufacturing a semiconductor package. In this case, it is preferable that the solder ball is formed in a circular shape so that the solder ball is easily fused to the exact center of the protruding end 212. Also, the projecting end 21
2 functions as an input / output terminal, the entire protruding end 212 should maintain high flatness.

In FIGS. 4A and 4B, the semiconductor chip support plate 22 is formed at the center of the lead frame 20a, but this is not restrictive but selective. The semiconductor chip support plate 22 is supported by a tie bar 23 connected to a dam bar 24. The tie bar 23 has a downset portion 234, which is a bent portion on another plane, identical to the downset portion 214 formed on the lead 21. At the same angle. Further, by forming the extension portion 231 on the tie bar 23, it is possible to increase the support area when mounting the semiconductor chip. A protruding end 232 having the same shape and height as the protruding end 212 formed on the bottom surface of the lead end 211 may be formed on the bottom surfaces of the semiconductor chip support plate 22 and the extension portion 231. Can be used for grounding and the like, and at the same time, it functions usefully as a heat release path.

FIG. 4A shows an example in which eight casing legs 90 are formed, four of which are formed on the semiconductor chip support plate 22. As long as the center and the center of the semiconductor chip mounting area 25 coincide with each other, the number, shape and position of the casing legs 90 are not particularly limited as described above.

FIG. 5 is a flowchart showing a method of manufacturing the printed circuit board 10 shown in FIG.
7 and 8 are sequential explanatory views for explaining a method of manufacturing the printed circuit board 10 of FIG. 1, and will be described together for convenience.

FIG. 7A shows a PCB original plate having a conductive metal thin film 11 ′, for example, a copper thin film formed on the upper and lower surfaces of a resin substrate 16, and FIG.
Drill Bit or laser beam,
Alternatively, it illustrates a drilling step of forming the via hole 13 by a chemical etching method.

FIG. 7C shows a conductive metal plating layer 17 formed by plating the inner peripheral surface of the via hole 13 with a conductive metal, for example, copper.
FIG. 6 shows a step of plating the inner peripheral surface of the via hole to connect the conductive metal thin film 11 ′ on the upper surface of the original plate for PCB and the conductive metal thin film 11 ′ on the bottom surface by forming the substrate.

FIGS. 7D and 7E show a masking step. The masking step is divided into a photoresist thin film coating step and a photomask transfer step as described below.

Specifically, FIG. 7D shows a step of coating a photoresist thin film, in which a normal photoresist thin film 18 is coated on the upper and lower surfaces of a PCB original plate for manufacturing the lead frame 10. Generally, copper or an alloy of nickel and iron is used for the conductive metal thin film 11 ′ on the upper and lower surfaces of the PCB disk.

FIG. 7E shows a photomask transfer step, in which a predetermined pattern on the upper surface composed of a plurality of conductive traces 11 and a predetermined pattern on the lower surface electrically connected to the plurality of conductive traces 11 are shown. To correspond to the pattern,
A photomask 19 is transferred onto the upper and lower photoresist thin films 18, respectively.

FIG. 8A shows the step of irradiating the ultraviolet rays. The masked original plate for PCB is irradiated with ultraviolet rays. In the positive type lithography, the photoresist 18 in the portion irradiated with the ultraviolet rays is nucleated and solubilized due to nucleation, so that the photoresist 18 can be removed.
8 is polymerized and insolubilized, so that the photoresist 18 in the portion where the ultraviolet rays are blocked by the photomask 19 can be removed. FIG. 8A shows a positive photoresist in a state where a photomask 19 is laminated on a photoresist thin film 18. In the case of a negative photoresist, the position of the laminated photomask 19 is positive. Is the opposite of the case.

FIG. 8 (B) shows a phenomenon stage. After irradiating the masked original plate for PCB with ultraviolet rays, the solubilized photoresist 18 is washed and removed to remove the PCB disk. The conductive trace 11 pattern is formed on the upper surface, and the solder ball land 15 pattern is formed on the lower surface.

FIG. 8D shows the etching step, in which the pattern consisting of the masked conductive traces 11 and the masked solder ball lands 15 are shown.
Since the pattern consisting of the regions is not etched and the region between the conductive traces 11 that are not masked on both the upper and lower surfaces is etched, the circuit pattern composed of the plurality of conductive traces 11 is formed on the upper surface of the PCB original plate. A circuit pattern including a plurality of solder ball lands 15 is formed on the lower surface. The remaining photoresist thin film 18 and photomask 19 are removed using a normal removing solution.

FIG. 8D shows a step of forming a solder mask, in which a solder ball land 15 is formed and a wire bonding area 11a is formed at the inner end of the conductive trace 11 (see FIGS. 1 and 2B). ) Is coated with a solder mask 14.

Finally, although not shown, a casing leg forming step of forming a plurality of casing legs 90 on the upper surface of the solder mask 14 coated on the semiconductor chip mounting area (the die pad 12 in FIG. 1) is performed. .
As described above, the material of the casing leg 90 may be any material such as metal or resin, and is not limited.
It is preferable to partially laminate using a material of the same material as the solder mask because it is convenient in the process.

FIG. 6 is a flow chart showing a method for manufacturing the printed circuit board 20a shown in FIGS. 4A and 4B, and FIG. 9 and FIG. )
5A and 5B are sequential explanatory diagrams illustrating a method of manufacturing the printed circuit board 20a in FIG. 4B, and will be described together for convenience.

FIGS. 9A and 9B show a masking step for the upper and lower surfaces of the conductive metal thin plate 21 ', for example, a copper thin plate. It is divided into a photomask transfer step.

More specifically, FIG. 9A shows a photoresist thin film coating step, in which a normal photoresist thin film 18 is coated on the upper and lower surfaces of a conductive metal thin plate 21 'for manufacturing a lead frame 20a. . Usually, such a thin plate 21 'is a copper thin plate or a nickel and iron alloy thin plate.

FIG. 9B shows a photomask transfer step, in which a predetermined pattern consisting of a plurality of leads 21 having an extended area of a lead end 211 area (see FIG. 4A), and The photo on the upper and lower surfaces has an area smaller than that of the lead end 211 region, and corresponds to a predetermined pattern including a projecting end 212 region (see FIG. 4B) located at the center of the lower surface of the lead end 211 region. The photomask 19 is transferred onto the resist thin film 18, respectively.

FIG. 9C shows the step of irradiating the ultraviolet rays. The upper and lower surfaces of the masked conductive metal sheet 21 'are irradiated with ultraviolet rays. FIG. 9C shows a photoresist thin film 1.
Although the positive type photoresist in a state where the photomask 19 is laminated on 8 is shown, in the case of the negative type photoresist, the position of the laminated photomask 19 is opposite to that in the case of the positive type.

FIG. 10A shows a phenomenon stage.
After irradiating the masked conductive metal sheet 21 ′ with ultraviolet rays, the solubilized photoresist 18 is washed,
After removal, a lead pattern is formed on the upper surface of the conductive metal sheet 21 ', and a protruding end pattern is formed on the lower surface. Top-side masked lead end 21 with enlarged area
At the center of the lower surface area corresponding to one area, there is a masked protruding end 212 area.

FIG. 10B shows an etching step, in which a pattern consisting of the plurality of leads 21 having the masked lead end 211 and a pattern consisting of the masked protruding end 212 are formed. In the formation, the portion between the unmasked lead 21 regions on both the upper and lower surfaces is subjected to full etching 27, and the masked protruding end of the lower surface region corresponding to the lead end 211 region masked on the upper surface is formed. The unmasked portion except for the region 212 is partially etched 28 to form the conductive metal sheet 2.
1 'is manufactured with the patterned lead frame 20a. The remaining photoresist thin film 18 and photomask 19 are removed using a general removing solution.

FIG. 10C shows the stage of forming the casing legs, and the material, number and shape of the casing legs 90 are not particularly limited as described above. As shown in FIG. 4A, the position of the casing leg 90 may be any position as long as the condition that the center of weight of the semiconductor chip to be mounted coincides with the center of the semiconductor chip mounting area 25 is satisfied. It may be formed on the semiconductor chip support plate 22 and / or on the upper surface of the lead end 211 in the semiconductor chip mounting area 25.

Although not shown, a downset portion forming step is performed after the etching step, and a dam bar (FIG. 4) is formed.
The lead 21 portion adjacent to (A) and (24) in FIG. 4 (B) is inclined downward and bent downward to obtain a downset portion (214 in FIGS. 4 (A) and 4 (B)).
Can be formed, but this is optional.

FIGS. 11A to 11D are sequential diagrams for explaining a method of manufacturing the ball grid array semiconductor package 1a using the flexible printed circuit board 10a of FIG. 2A.

FIG. 11A is a sectional view showing the flexible printed circuit board 10a to which the carrier frame 80 of FIG. 2A is attached. The carrier frame 80 is made of copper, copper alloy, aluminum, stainless steel, or the like. Metal materials such as are used mainly, and an oxide film treatment (Anodizin
g) to form a thin film, or nickel N to allow smooth degating from the epoxy molding compound during molding.
Surface treatment can also be performed using i or chromium Cr. A die pad (not shown) may be formed at the exposed central portion of the semiconductor chip, but this is optional.

FIG. 11B is a partial cross-sectional view showing a semiconductor chip mounting step, in which the semiconductor chip 30 is exposed through the carrier frame 80 and the double-sided adhesive tape 42 via the adhesive layer 40. It is mounted on the upper surface of the central part. The semiconductor chip 30 is formed by dispensing a liquid resin adhesive 41 such as an epoxy resin (see FIG. 15) on the upper surface of the central portion of the flexible printed circuit board 10a and then curing the adhesive layer 40.
Implemented via It is desirable to use a silver-filled epoxy resin having excellent thermal conductivity as the liquid resin adhesive 41.

When the semiconductor chip 30 is mounted on the flexible printed circuit board 10a, since the casing legs 90 are formed on the semiconductor chip mounting area 25, the semiconductor chip 3
0 is in contact with the upper surface of the casing leg 90, the liquid epoxy resin 41 is filled in the space between the lower surface of the semiconductor chip 30 and the upper surface of the semiconductor chip mounting area 25, and the height of the space is uniform. Since the height of the plurality of casing legs 90 having the same height is exactly the same, the thickness of the adhesive layer 40 formed by curing the liquid epoxy resin 41 becomes exactly the same. Therefore, even under a high-temperature process such as a subsequent wire bonding step and a molding step, the bonding layer 4 can be formed.
0, the interface peeling phenomenon can be effectively suppressed.

FIG. 11C is a cross-sectional view showing a wire bonding step. The input / output chip pad 31 on the upper surface of the mounted semiconductor chip 30 and the wire bonding portion 11 a of the conductive trace 11 are connected to the conductive wire 50. They are electrically connected by bonding. Conductive wire 50
Usually, a gold session and an aluminum session are used, but the present invention is not limited thereto.

FIG. 11D shows a molding step of forming a resin sealing portion 60 for protecting the conductive wires 50 and the like bonded to the semiconductor chip 30 from the external environment, and thereafter, as an external input / output terminal. Is a singulation step after the step of fusing the solder ball 70 to the solder ball land 15. The carrier frame 80 is dropped by pressing the resin sealing portion 60 downward from above. The semiconductor package 1a is manufactured.

FIG. 13 shows the ball grid array semiconductor package 1a manufactured as described above.

Although this has been mentioned before in the description of the manufacturing method, the overall structure of the flexible resin substrate 16 ′, the wire bonding portion 11 a and the solder ball land 15 A plurality of conductive traces 11 formed on the outer peripheral portion of the upper surface of the flexible resin substrate 16 ′, a semiconductor chip mounting region 25 formed on the central portion of the upper surface of the flexible resin substrate 16 ′, A flexible printed circuit board 10a including a plurality of casing legs 90 formed at a constant height on the chip mounting area 25.
Various electronic circuits and / or wirings are stacked, a plurality of input / output chip pads 31 are formed on the surface thereof, and a plurality of casings having a uniform height on the semiconductor chip mounting area 25. The semiconductor chip 30 mounted by the legs 90 via the adhesive layer 40 having a uniform height
A conductive wire 50 for electrically connecting the input / output chip pad 31 of the semiconductor chip 30 and the wire bonding portion 11a of the flexible circuit board 10a;
And a resin sealing portion 60 for protecting the conductive wires 50 and the like from an external environment; and a solder ball land 15 electrically connected to the conductive traces 11 on the flexible circuit board 10a. And a solder ball 70 fused as an input / output terminal to an unillustrated terminal.

FIG. 12A is a sectional view of a ball grid array semiconductor package 1 using the printed circuit board 10 of FIG.

The manufacturing method is consistent with the flow chart outside the dashed box in FIG. 5, and the manufacturing steps of the semiconductor package 1 after manufacturing the printed circuit board 10 shown in FIG.
1 (B) to FIG. 1 (D) are essentially the same, and a description thereof will be omitted.

The configuration of the ball grid array semiconductor package 1 shown in FIG. 12A is essentially the same as the configuration of the chip scale semiconductor package 1a shown in FIG. 13, but the overall configuration is also the same. It is as follows when it considers.

The resin substrate 16 and the bond finger 11a
And a plurality of conductive traces 11 formed on an outer peripheral portion of an upper surface of a resin substrate 16 and a semiconductor formed on a central portion of an upper surface of the resin substrate 16 having solder ball lands 15 electrically connected to via holes 13. Chip mounting area (Fig. 12
1A, a die pad 12), a printed circuit board 10 including a plurality of casing legs 90 formed at a constant height on the semiconductor chip mounting area; various electronic circuits and / or wirings are stacked. A plurality of input / output chip pads 31 are formed on the surface thereof, and a plurality of casing legs 90 having a uniform height are provided on the semiconductor chip mounting area via an adhesive layer 40 having a uniform height. A semiconductor chip 30 mounted thereon; a conductive wire 50 for electrically connecting an input / output chip pad 31 of the semiconductor chip 30 to a wire bonding portion 11a of the flexible circuit board 10; a semiconductor chip 30 and a conductive wire A resin sealing portion 60 for protecting 50 and the like from an external environment; and a solder board electrically connected to the conductive traces 11 on the flexible circuit board 10. Composed of solder balls 70. which in Rurando 15 is fused as the input and output terminals of the main board.

FIG. 12B is a partial plan view showing a dispensing state of the liquid adhesive resin 41 when the semiconductor chip 30 is mounted on the printed circuit board 10 of FIG. 1 according to the present invention.
Reference numeral 14 denotes an example in which the liquid adhesive resin 41 is dispensed in a dot shape on the internal region of the casing leg 90 on the semiconductor chip mounting area (the die pad 12 and the solder mask laminated thereon in FIG. 12A). Indicates the status.

Referring to FIG. 12A and FIG. 12B together, when the semiconductor chip 30 is pressed and mounted in the state shown in FIG. 12B, the bottom surface of the semiconductor chip 30 Because the upper surface of the casing leg 90 is in contact with the upper surface of the casing leg 90, the space portion having a uniform height by the height limited by the plurality of casing legs 90 having the uniform height is formed by the liquid adhesive resin 41.
Spreads and fills and cures to form an adhesive layer 4 of uniform height
0 is formed. Accordingly, it is possible to efficiently prevent the interface peeling phenomenon in the adhesive layer 40 due to the heat generated during the manufacturing process of the semiconductor package 1 or during the operation of the semiconductor package 1.

FIG. 14 is a cross-sectional view of a quad flat semiconductor package 1b using the lead frame 20 of FIG. 3. The semiconductor package 1b has a plurality of casing legs 90 having a uniform height formed on the upper surface. A semiconductor chip support plate 22, a plurality of leads 21 arranged at an outer portion of the semiconductor chip support plate 22 at a predetermined distance from the semiconductor chip support plate 22, and a plurality of input / output chip pads 31 are formed. A semiconductor chip 30 mounted via an adhesive layer 40 having a uniform height by a plurality of casing legs 90 having
And a resin sealing portion 60 for protecting the semiconductor chip 30, the conductive wire 50, and the like from the external environment.

FIG. 15 is a sectional view of a chip scale semiconductor package 1c using the lead end grid array lead frame 20a shown in FIGS. 4A and 4B.
The manufacturing method is shown in the flow chart outside the dashed box in FIG. 6 and is substantially the same as the flow chart outside the dashed box in FIG. 5, so only the differences will be mainly described.

At the semiconductor chip mounting stage, the semiconductor chip mounting area 25 of the lead frame 20a to which the present invention is applied.
The semiconductor chip 30 is mounted via an adhesive layer 40. The bottom surface of the semiconductor chip 30 contacts the upper surface of the casing leg 90 having a uniform height as shown in FIG. 4A, and the semiconductor chip support plate 22, the lead 21, the lead end 211, the tie bar 23, and the extension 231 are formed. An adhesive layer 40 having the same height as the height of the casing leg 90 is formed on the upper surface. Here, the semiconductor chip support plate 22, the tie bar 23, and the extension 231 are optional elements. In the wire bonding step, the chip pads 31 formed on the upper surface of the semiconductor chip 2 are formed.
And the lead 21 are bonded by a conductive wire 50 to make an electrical connection therebetween.

At the molding stage, the semiconductor chip 30
And a resin sealing portion 60 for protecting the conductive wires 50 and the like from the external environment are formed so that the protruding end 212 of the lead end 211 is exposed on the bottom surface.

The solder ball fusion step is an optional step, and the protruding end 21 exposed on the bottom surface of the resin sealing portion 60 is
The solder balls 70 can be fused to function as input / output terminals.

In the singulation stage, the chip scale semiconductor package 1c is cut into the leads 21 extending outside with the resin sealing portion 60 as a boundary, and separated into units.

The chip scale semiconductor package 1c
Has a bent portion 213 on the same plane and / or a downset portion 214 (FIG. 13) which is a bent portion on another plane.
(See FIG. 1), and is extended at least once or more into the semiconductor chip mounting region 25, has an extended portion 231 at the inner end thereof, and has a protruding end 212 functioning as an input / output terminal formed at the bottom center thereof. A plurality of leads 21 divided into a plurality of groups each having a length; and a selected lead end 211 located in the semiconductor chip mounting area 25.
A plurality of casing legs 90 having a uniform height and a plurality of input / output chip pads 31 are formed on the upper surface of the device. A semiconductor chip 30 mounted via an adhesive layer 40 having a height, a conductive wire 50 for electrically connecting the semiconductor chip 30 and the lead 21, a semiconductor chip 30 and the conductive wire 50, and the like. And a resin sealing portion 60 having a bottom surface of the protruding end 212 exposed to the outside for protection.

[0081]

As described above, according to the method of manufacturing a circuit board according to the present invention, a plurality of casing legs having a uniform height are mounted on a semiconductor chip mounting area of the circuit board when the semiconductor chip is mounted on the semiconductor chip. Forming a semiconductor package using the circuit board manufactured by the method according to the present invention. Can be easily controlled to a strict and accurate uniform state, so that the interface peeling phenomenon in the adhesive layer due to the high temperature environment under the subsequent high temperature process or the heat generated during the operation of the semiconductor package can be efficiently prevented. Therefore, it is a new and useful invention that enhances product reliability.

[Brief description of the drawings]

FIG. 1 shows a printed circuit board (Printed Ci) to which the present invention is applied.
rcuit Board (PCB).

2A is an exemplary cross-sectional view of a flexible printed circuit board to which the present invention is applied, and FIG. 2B is an exemplary plan view of the flexible printed circuit board to which the present invention is applied in a state where a frame is not attached. It is.

FIG. 3 is an exemplary plan view of a lead frame to which the present invention is applied.

4A and 4B are an exemplary plan view and a bottom view of a lead end grid array lead frame to which the present invention is applied.

FIG. 5 is a flowchart illustrating a method of manufacturing the printed circuit board of FIG. 1 and a semiconductor package using the same.

FIG. 6 is a flowchart showing a method of manufacturing the lead end grid array lead frame of FIGS. 4A and 4B and a semiconductor package using the same.

FIGS. 7A to 7E are sequential explanatory diagrams (part 1) illustrating a method of manufacturing the printed circuit board in FIG. 1;

FIGS. 8A to 8D are sequential explanatory views (part 2) for explaining the method of manufacturing the printed circuit board in FIG. 1;

FIGS. 9A to 9C are sequential explanatory diagrams (part 1) illustrating a method of manufacturing the lead end grid array lead frame of FIGS. 4A and 4B.

FIGS. 10A to 10C are FIGS. 4A and 4B.
FIG. 9 is a sequential explanatory view (part 2) for explaining the method of manufacturing the lead end grid array lead frame of FIG.

FIGS. 11A to 11D show a ball grid array (Ball Grid Arra) using the flexible printed circuit board shown in FIG. 2A.
(y: BGA) is a sequential explanatory view for explaining the method of manufacturing the semiconductor package;

12A is a cross-sectional view of a ball grid array (BGA) semiconductor package using the printed circuit board of FIG. 1, and FIG. 12B is a semiconductor chip on the printed circuit board of FIG. 1 according to the present invention; FIG. 4 is a partial plan view showing a dispensing state of an adhesive resin during mounting.

FIG. 13 is a sectional view of a ball grid array semiconductor package using the flexible printed circuit board of FIG. 2A.

FIG. 14 is a view showing a quad flat semiconductor package using the lead frame of FIG. 3;
: QFP).

FIG. 15 shows a chip scale semiconductor package (Chip Scale Semiconductor Package) using the lead end grid array lead frame shown in FIGS. 4 (A) and 4 (B).
It is sectional drawing of (CSP).

16A is a cross-sectional view illustrating a semiconductor chip mounted state in a conventional general ball grid array semiconductor package, and FIG. 16B is a cross-sectional view illustrating an interface peeling phenomenon that may occur in the semiconductor package of FIG. It is sectional drawing.

[Explanation of symbols]

1, 1a, 1b, 1c Semiconductor package of the present invention using circuit board of the present invention 10, 10a Circuit board (printed circuit board) of the present invention 11 Conductive trace 11a Wire bonding portion 11b Circuit pattern Part 11 'Conductive metal thin film 12 Die pad 13 Via hole 14 Solder resist 15 Solder ball land 16 Resin substrate 16' Flexible resin substrate 17 Conductive metal plating layer 18 Photo resist thin film 19 Photo mask 20, 20a Present invention Circuit board (lead frame) 21 lead 21 'conductive metal sheet 211 lead end 212 protruding end 213 coplanar bent part 214 downset part 22 semiconductor chip support plate 23 tie bar 231 extended part 232 Projecting end 234 Down set part 24 Damー 25 Semiconductor chip mounting area 26 Conductive metal thin plate 27 Full etching 28 Partial etching 30 Semiconductor chip 31 Chip pad 40 Adhesive layer 41 Liquid adhesive resin 42 Double-sided adhesive tape 50 Conductive wire 60 Resin sealing part 70 Solder ball 80 Carrier frame 81 Through hole 90 Casing leg

Claims (20)

[Claims] 1. A circuit board comprising: a semiconductor chip mounting area; a plurality of circuits formed on an outer peripheral edge of the semiconductor chip mounting area apart from the semiconductor chip mounting area; and an input / output terminal section; On the upper surface, there are at least three casing legs having a uniform height for uniformly controlling the thickness of the adhesive layer, and the casing legs have a weight center of the semiconductor chip and a semiconductor chip mounting area when the semiconductor chip is mounted. A circuit board characterized in that the centers are positioned so as to coincide with each other. 2. The height of said casing leg is 0.5 to 3 mi.
2. The circuit board according to claim 1, wherein the circuit board is formed at a height of l. 3. The circuit board according to claim 1, wherein the casing legs are formed as a solder mask. 4. A circuit board, comprising: a resin substrate; a plurality of conductive traces as a circuit formed in an outer peripheral region of the upper surface of the resin substrate and having a wire bonding portion at an inner end thereof; A plurality of via holes formed in the resin substrate, and formed in a region adjacent to the via hole on a bottom surface of the resin substrate, and electrically connected to the conductive trace on an upper surface of the resin substrate. A plurality of solder ball lands, a semiconductor chip mounting area at the center of the resin substrate, an insulating solder mask formed on upper and lower surfaces of the resin substrate excluding the solder ball lands and the wire bonding portion, and a semiconductor chip. Rigid printed circuit composed of a plurality of casing legs of uniform height formed on an insulating solder mask on the mounting area Circuit board according to claim 1, characterized in that a plate. 5. A circuit board, comprising: a flexible resin substrate; a plurality of conductive traces formed as a circuit having a wire bonding portion at an inner end thereof formed in an outer peripheral region of the upper surface of the flexible resin substrate; A plurality of solder ball lands electrically connected to the conductive traces on the upper surface of the resin substrate; a semiconductor chip mounting region at the center of the resin substrate; and a plurality of casing legs formed on the semiconductor chip mounting region. 2. The circuit board according to claim 1, wherein the circuit board comprises a flexible printed circuit board. 6. A circuit board, comprising: a semiconductor chip support plate; a plurality of tie bars supporting the semiconductor chip support plate and having a downset portion; and a circuit formed on an outer peripheral edge of the semiconductor chip support plate. A plurality of linear leads, a plurality of tie bars, a dam bar supporting the plurality of leads, and a plurality of casing legs formed on the semiconductor chip support plate. The circuit board according to claim 1, wherein: 7. A circuit board having a bent portion on the same plane, a plurality of leads as circuits divided into a plurality of groups having different depths and extending into a semiconductor chip mounting region; A dam bar for supporting an outer end of each of the leads; and a lead end formed to have an expanded area at an inner end of each of the plurality of leads, and having a protruding end as an input / output terminal at a center of a bottom surface thereof. 2. The circuit according to claim 1, wherein the lead end grid array frame comprises: a plurality of casing legs formed on an upper surface of a selected lead end located in the semiconductor chip mounting area. substrate. 8. The circuit board according to claim 7, wherein the lead end grid array frame has a downset portion that is a bent portion on another plane. 9. The lead end grid array frame has a semiconductor chip support plate, the semiconductor chip support plate is supported by one end of a tie bar, the other end of the tie bar is supported by the dam bar, and a plurality of the casing legs are provided. 8. The circuit board according to claim 7, wherein the first substrate is formed not only on the upper surface of the selected lead end located in the semiconductor chip mounting area but also on the semiconductor chip support plate. 10. A method of manufacturing a circuit board by a normal circuit pattern forming method in which a masking step, an ultraviolet irradiation step, a phenomena step, and an etching step of a circuit board original plate are sequentially performed, the circuit board comprising: a semiconductor chip mounting area; In order to control the thickness of the adhesive layer on the upper surface of the semiconductor chip mounting area uniformly after the step of forming a circuit pattern composed of a plurality of circuits formed on the outer peripheral edge of the semiconductor chip mounting area apart from the chip mounting area and the input / output terminal section Performing a casing leg forming step of forming at least three casing legs having the same height, wherein the center of the weight of the semiconductor chip and the center of the semiconductor chip mounting area when the casing leg is mounted on the semiconductor chip coincide with each other. A method of manufacturing a circuit board, characterized in that the circuit board is formed at a position to be formed. 11. The height of the casing legs is 0.5 to 3 m.
The method for manufacturing a circuit board according to claim 10, wherein the circuit board is formed at a height of il. 12. The method according to claim 10, wherein the casing leg is formed as a solder mask. 13. An original plate for a printed circuit board in which a conductive metal thin film is coated on upper and lower surfaces of a resin substrate, wherein a perforation for forming a via hole in the circuit board disk prior to a masking step. performing a (drilling) step and a plating step of forming a conductive metal plating layer on an inner peripheral surface of the via hole, and forming an electrically conductive metal plating layer on an inner peripheral surface of the via hole. A plurality of conductive traces as a circuit having a wire bond at the end;
After performing a circuit pattern forming step of forming a plurality of solder ball lands formed in a region adjacent to the via hole on the bottom surface of the resin substrate and electrically connected to the conductive traces on the top surface of the resin substrate 11. The method of claim 10, further comprising performing a solder mask forming step of forming an insulating solder mask on upper and lower surfaces of the resin substrate except for the solder ball lands and the wire bonding. 14. The manufacturing method according to claim 13, wherein the semiconductor chip mounting area is formed by a die pad made of a conductive metal having a top surface coated with a solder mask. 15. The original board for a printed circuit board, wherein the original board for a circuit board is a printed circuit board original board in which a conductive metal thin film is coated on an upper surface of a flexible resin substrate, and an outer peripheral area of the upper surface of the flexible resin substrate in a circuit pattern forming step. A plurality of conductive traces as a circuit having a wire bonding portion at an inner end thereof, and a plurality of solder ball lands electrically connected to the conductive traces and formed on the bottom surface of the resin substrate. The method for manufacturing a circuit board according to claim 10, wherein the circuit board is formed. 16. A method for manufacturing a circuit board, wherein the original board for a circuit board is a conductive metal sheet, and a circuit pattern forming step includes the following steps. (A) A photoresist thin film is coated on the entire upper and lower surfaces of a conductive metal thin plate, and has a predetermined pattern including a plurality of lead regions having a lead end region having an expanded area, and an area smaller than the lead end region. A masking step of transferring a photomask onto the photoresist thin film on the upper and lower surfaces so as to correspond to a predetermined pattern comprising a protruding end region located at the center of the lower surface of the lead end region; (C) a phenomenon step of forming the predetermined lead pattern and the predetermined projecting end pattern on the photoresist thin film on the upper and lower surfaces, and (C) an upper and lower surface, respectively. The portion between the lead regions that are not masked by both is fully etched. , Of the lower surface area corresponding to the lead end region masked on the upper surface, the masked unmasked excluding the projecting end region portion is partially etched, etching step of patterning the conductive metal sheet. 17. A semiconductor chip supporting plate is formed in a circuit pattern forming step, the semiconductor chip supporting plate is supported by the other end of a tie bar having one end supported by a dam bar, and a plurality of the casing legs are mounted on the semiconductor chip. 17. The method according to claim 16, wherein the semiconductor device is formed not only on the upper surface of the selected lead end located in the region but also on the semiconductor chip support plate. 18. The method according to claim 17, wherein the protruding end region is masked in a circular shape in the masking step. 19. A method of dispensing a liquid adhesive resin on a semiconductor chip mounting area of a circuit board, and then forming a plurality of semiconductor chips at positions such that the center of weight of the semiconductor chip coincides with the center of the semiconductor chip mounting area. The liquid adhesive resin has a void in a space between the bottom surface of the semiconductor chip and the top surface of the semiconductor chip mounting area, which is limited by the height of the casing leg, while the top surface of the casing leg contacts the bottom surface of the semiconductor chip. A semiconductor chip mounting step of pressing and bonding the semiconductor chip so that the semiconductor chip is filled without contact; an electrical connection step of electrically connecting the semiconductor chip and a circuit by a conductive wire; and connecting the semiconductor chip and the conductive wire. And a molding step for forming a resin sealing portion for protecting from an external environment. The method of manufacturing a semiconductor package using a circuit board according to any one of claim 9. 20. The method of claim 19, further comprising, after the molding step, a solder ball welding step of welding solder balls as input / output terminals.