JPH10116935A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
JPH10116935A
JPH10116935A JP8267607A JP26760796A JPH10116935A JP H10116935 A JPH10116935 A JP H10116935A JP 8267607 A JP8267607 A JP 8267607A JP 26760796 A JP26760796 A JP 26760796A JP H10116935 A JPH10116935 A JP H10116935A
Authority
JP
Japan
Prior art keywords
resin
metal film
layer
chip
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8267607A
Other languages
Japanese (ja)
Other versions
JP3189703B2 (en
Inventor
Yoshiyuki Yoneda
義之 米田
Kazuto Tsuji
和人 辻
Eiji Sakota
英治 迫田
Takashi Nomoto
隆司 埜本
Masanori Onodera
正徳 小野寺
Masaichi Orimo
政一 織茂
Junichi Kasai
純一 河西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP26760796A priority Critical patent/JP3189703B2/en
Priority to US08/744,048 priority patent/US6072239A/en
Priority to KR1019960052529A priority patent/KR100212403B1/en
Priority to EP20020016355 priority patent/EP1261026A1/en
Priority to EP20020016357 priority patent/EP1291911A1/en
Priority to TW085113625A priority patent/TW348306B/en
Priority to EP20020016354 priority patent/EP1284501A1/en
Priority to EP20020016356 priority patent/EP1284502A1/en
Priority to EP19960308093 priority patent/EP0773584B1/en
Priority to CNB2004100476353A priority patent/CN1307698C/en
Priority to CNB96114520XA priority patent/CN1215537C/en
Publication of JPH10116935A publication Critical patent/JPH10116935A/en
Priority to US09/192,445 priority patent/US6159770A/en
Priority to US09/192,201 priority patent/US6376921B1/en
Priority to US09/200,846 priority patent/US6329711B1/en
Priority to US09/442,038 priority patent/US6856017B2/en
Priority to US09/809,105 priority patent/US6573121B2/en
Application granted granted Critical
Publication of JP3189703B2 publication Critical patent/JP3189703B2/en
Priority to US10/856,777 priority patent/US7144754B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the area of mounting for cost reduction, by bonding the electrode pads on the semiconductor chip sealed in a resin package to metal films exposed on almost the same level with the bottom of the resin package using a bonding wire. SOLUTION: One end of a bonding wire 13 is bonded to an electrode pad 12 on a semiconductor chip 11, and the other end is bonded to a metal film 15 exposed on the bottom of a resin package 14 made of mold resin. The metal films 15 are almost flush with the bottom of the resin package. The metal films 15 are 0.4mm in width, 0.75mm in length, and 10μ in height, each, and placed with a pitch of 0.65mm. Because of this structure it is unnecessary to route wires to the inner leads and outer leads of IC, and the area can be reduced accordingly.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、高密度実装を可能
とするリードレス表面実装型の樹脂封止型パッケージの
構造及び製造方法に関する。近年、携帯電話等にみられ
るように、電子機器の小型化により樹脂封止型パッケー
ジに設けられるリードのピッチが小さくなる傾向にあ
る。そのため、樹脂封止型パッケージにおいて、その小
型化を実現する新たな構造、製造方法が必要になってい
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a method for manufacturing a leadless surface-mount type resin-sealed package capable of high-density mounting. In recent years, as seen in mobile phones and the like, the pitch of leads provided in a resin-sealed package tends to be smaller due to miniaturization of electronic devices. Therefore, a new structure and a new manufacturing method for realizing miniaturization of the resin-sealed package are required.

【０００２】[0002]

【従来の技術】図３３，３４は従来の薄型の樹脂封止型
パッケージの断面を示す図である。図３３において、１
は樹脂，２はチップ，３はアウターリード，４は金アル
ミニウム等からなるボンディングワイヤ，５はダイパッ
ドを示す。このパッケージはＳＳＯＰ（SHRINK SMALL O
UTLINE PACKAGE）と呼ばれるタイプのものであり、アウ
ターリード３がガルウイング状に曲げられ、基板に実装
される。2. Description of the Related Art FIGS. 33 and 34 are cross-sectional views of a conventional thin resin-sealed package. In FIG. 33, 1
Denotes a resin, 2 denotes a chip, 3 denotes an outer lead, 4 denotes a bonding wire made of gold aluminum or the like, and 5 denotes a die pad. This package is SSOP (SHRINK SMALL O
UTLINE PACKAGE), in which the outer leads 3 are bent in a gull wing shape and mounted on a substrate.

【０００３】また、図３４において、１は樹脂，２はチ
ップ，４は金アルミニウム等からなるボンディングワイ
ヤ，６はハンダボール，７はチップ２を搭載する搭載基
板を示す。このパッケージはＢＧＡ（BALL GRID ARRAY
）と呼ばれるタイプのものであり、基板に実装される
端子部分がハンダボール６により形成されている。In FIG. 34, reference numeral 1 denotes a resin, 2 denotes a chip, 4 denotes a bonding wire made of gold aluminum or the like, 6 denotes a solder ball, and 7 denotes a mounting substrate on which the chip 2 is mounted. This package is BGA (BALL GRID ARRAY
), And the terminal portion mounted on the substrate is formed by solder balls 6.

【０００４】[0004]

【発明が解決しようとする課題】図３３に示されるＳＳ
ＯＰタイプのパッケージでは、樹脂１内に占めるインナ
ーリード８からアウターリード３への引き回し部分９の
面積や、アウターリード３自身の占める面積が大きく、
実装面積が大きくなってしまうという問題があった。The SS shown in FIG.
In the OP type package, the area of the routing portion 9 from the inner lead 8 to the outer lead 3 occupying the resin 1 and the area occupied by the outer lead 3 itself are large.
There is a problem that the mounting area becomes large.

【０００５】また、図３４に示されるＢＧＡタイプのパ
ッケージでは、搭載基板７を用いる点で、コストが高く
なってしまうという問題があった。そこで本発明は，実
装面積が小さく、コストの低い樹脂封止型半導体装置と
その製造方法を提供することを目的とする。Further, the BGA type package shown in FIG. 34 has a problem in that the mounting substrate 7 is used and the cost is increased. Therefore, an object of the present invention is to provide a resin-sealed semiconductor device having a small mounting area and low cost, and a method of manufacturing the same.

【０００６】[0006]

【課題を解決するための手段】上記課題は以下の手段を
とった半導体装置とその製造方法により解決することが
できる。請求項１記載の発明では、電極パッドを有する
半導体チップと、該半導体チップを封止する樹脂パッケ
ージと、該樹脂パッケージの底面から該底面とほぼ同一
平面で露出する金属膜と、一端が該電極パッドとボンデ
ィングされ、他端が該金属膜とボンディングされたボン
ディングワイヤとを有することを特徴とするものであ
る。The above objects can be attained by a semiconductor device having the following means and a method of manufacturing the same. According to the first aspect of the present invention, a semiconductor chip having an electrode pad, a resin package for encapsulating the semiconductor chip, a metal film exposed from the bottom surface of the resin package on substantially the same plane as the bottom surface, And a bonding wire bonded to the pad and the other end bonded to the metal film.

【０００７】請求項２記載の発明では、電極パッドを有
する半導体チップと、該半導体チップを封止する樹脂パ
ッケージと、該樹脂パッケージ底面に設けられ、該底面
から突出する樹脂突起と、該樹脂突起上に設けられた金
属膜と、該樹脂パッケージ底面の該樹脂突起と該チップ
との間の領域に形成され、該金属膜と接続された導電部
と、一端が該電極パッドとボンディングされ、他端が該
導電部とボンディングされたボンディングワイヤとを有
することを特徴とするものである。According to a second aspect of the present invention, a semiconductor chip having electrode pads, a resin package for sealing the semiconductor chip, a resin projection provided on the bottom surface of the resin package and projecting from the bottom surface, and a resin projection A metal film provided thereon, a conductive portion formed on the bottom surface of the resin package in a region between the resin protrusion and the chip, connected to the metal film, and one end bonded to the electrode pad; The end has a bonding wire bonded to the conductive portion.

【０００８】請求項３の発明では、請求項１及び２に関
し、前記チップと前記樹脂パッケージ底面との間に放熱
部材を設けたことを特徴とするものである。請求項４記
載の発明では、電極パッドを有する半導体チップと、該
半導体チップを封止する樹脂パッケージと、該樹脂パッ
ケージ底面に設けられ、該底面から突出する樹脂突起
と、該樹脂突起上にのみ設けられた金属膜と、一端が該
電極パッドとボンディングされ、他端が該金属膜にボン
ディングされたボンディングワイヤとを有することを特
徴とするものである。According to a third aspect of the present invention, in the first and second aspects, a heat radiating member is provided between the chip and the bottom surface of the resin package. In the invention according to claim 4, a semiconductor chip having an electrode pad, a resin package for sealing the semiconductor chip, a resin projection provided on the bottom surface of the resin package and projecting from the bottom surface, and only on the resin projection It has a metal film provided and a bonding wire having one end bonded to the electrode pad and the other end bonded to the metal film.

【０００９】請求項５記載の発明では、電極パッドを有
する半導体チップと、該半導体チップを封止する樹脂パ
ッケージと、該樹脂パッケージの底面から該底面とほぼ
同一平面で露出する金属膜と、一端が該電極パッドとボ
ンディングされ、他端が該金属膜とボンディングされた
バンプとを有することを特徴とするものである。According to a fifth aspect of the present invention, a semiconductor chip having an electrode pad, a resin package for encapsulating the semiconductor chip, a metal film exposed from the bottom surface of the resin package in substantially the same plane as the bottom surface, Are bonded to the electrode pad, and the other end has a bump bonded to the metal film.

【００１０】請求項６記載の発明では、電極パッドを有
する半導体チップと、該半導体チップを封止する樹脂パ
ッケージと、該樹脂パッケージ底面に設けられ、該底面
から突出する樹脂突起と、該樹脂突起上に設けられた金
属膜と、該樹脂パッケージ底面の該樹脂突起と該チップ
との間の領域に形成され、該金属膜と接続され導電部
と、一端が該電極パッドとボンディングされ、他端が該
導電部とボンディングされたバンプとを有することを特
徴とするものである。According to the present invention, a semiconductor chip having an electrode pad, a resin package for sealing the semiconductor chip, a resin projection provided on the bottom surface of the resin package and projecting from the bottom surface, and a resin projection A metal film provided thereon, a conductive portion formed in a region between the resin protrusion and the chip on the bottom surface of the resin package, connected to the metal film, and one end bonded to the electrode pad; Have the conductive portion and a bump bonded thereto.

【００１１】請求項７記載の発明では、請求項６に関
し、前記導電部に凹部が形成され、前記バンプが該凹部
に嵌合するようにボンディングされていることを特徴と
するものである。請求項８記載の発明では、請求項２，
６，７に関し、前記樹脂突起を除く前記樹脂パッケージ
底面に絶縁膜を形成することを特徴とするものである。According to a seventh aspect of the present invention, in the sixth aspect, a concave portion is formed in the conductive portion, and the bump is bonded so as to fit in the concave portion. According to the eighth aspect of the invention,
6 and 7, wherein an insulating film is formed on the bottom surface of the resin package except for the resin protrusion.

【００１２】請求項９記載の発明では、電極パッドを有
する半導体チップと、該半導体チップを封止する樹脂パ
ッケージと、該樹脂パッケージ底面に設けられ、該底面
から突出する樹脂突起と、該樹脂突起上にのみ設けられ
た金属膜と、一端が該電極パッドとボンディングされ、
他端が該金属膜にボンディングされたバンプとを有する
ことを特徴とするものである。According to the ninth aspect of the present invention, a semiconductor chip having an electrode pad, a resin package for sealing the semiconductor chip, a resin projection provided on a bottom surface of the resin package and projecting from the bottom surface, and a resin projection A metal film provided only on the top, and one end bonded to the electrode pad,
The other end has a bump bonded to the metal film.

【００１３】請求項１０記載の発明では、請求項５乃至
９に関し、前記チップの非電極パッド形成面を前記樹脂
パッケージから露出させたことを特徴とするものであ
る。請求項１１記載の発明では、請求項１０に関し、露
出した前記チップの非電極パッド形成面に放熱板を設け
たことを特徴とするものである。According to a tenth aspect of the present invention, in any one of the fifth to ninth aspects, the non-electrode pad forming surface of the chip is exposed from the resin package. An eleventh aspect of the present invention is directed to the tenth aspect, wherein a heat sink is provided on the exposed surface of the chip where the non-electrode pads are formed.

【００１４】請求項１２記載の発明では、請求項９に関
し、前記チップの電極パッド形成面上に設けられ、前記
樹脂パッケージ底面とほぼ同一平面となるように形成さ
れた絶縁部材を有することを特徴とするものである。請
求項１３記載の発明では、電極パッドを有する半導体チ
ップと、該半導体チップを封止する樹脂パッケージと、
該樹脂パッケージ底面に設けられ、該底面から突出する
樹脂突起と、該樹脂突起上に設けられた金属膜と、該電
極パッドまたは該金属膜に設けられたバンプと、該バン
プと該金属膜との間が異方導電樹脂により導通がとられ
ていることを特徴とするものである。According to a twelfth aspect of the present invention, in accordance with the ninth aspect, there is provided an insulating member provided on the electrode pad forming surface of the chip and formed substantially flush with the bottom surface of the resin package. It is assumed that. In the invention according to claim 13, a semiconductor chip having an electrode pad, a resin package for sealing the semiconductor chip,
A resin protrusion provided on the resin package bottom surface and projecting from the bottom surface, a metal film provided on the resin protrusion, a bump provided on the electrode pad or the metal film, the bump and the metal film; Is electrically connected by an anisotropic conductive resin.

【００１５】請求項１４記載の発明では、請求項１乃至
１３に関し、その金属膜を銀（Ａｇ）またはパラジウム
（Ｐｄ）の一層にて形成する、もしくはＡｇまたはＰｄ
の２層にて形成する、もしくは第１層を最外層とした場
合に、第１層−第２層−第３層をＡｕ−ニッケル（Ｎ
ｉ）−Ａｕ，Ｐｄ−Ｎｉ−Ｐｄ，Ａｕ−Ｐｄ−Ａｕ，半
田−Ｎｉ−Ａｕ，半田−Ｎｉ−Ｐｄの３層にて形成す
る、もしくは第１層−第２層−第３層−第４層を半田−
Ｎｉ−Ｐｄ−Ａｕ，Ｐｄ−Ｎｉ−Ｐｄ−Ａｕ，Ａｕ−Ｐ
ｄ−Ｎｉ−Ｐｄ，Ｐｄ−Ｎｉ−Ａｕ−Ｐｄ 半田−Ｎｉ−Ａｕ−Ｐｄの４層にて形成する、もしくは
第１層−第２層−第３層−第４層−第５層をＡｕ−Ｐｄ
−Ｎｉ−Ｐｄ−Ａｕ，半田−Ｎｉ−Ａｕ−Ｐｄ−Ａｕ Ｐｄ−Ｎｉ−Ａｕ−Ｐｄ−Ａｕ，Ａｕ−Ｐｄ−Ｎｉ−Ａ
ｕ−Ｐｄ Ｐｄ−Ｎｉ−ＣｕーＮｉ−Ｐｄの５層にて形成する、も
しくは第１層−第２層−第３層−第４層−第５層−６層
をＡｕ−Ｐｄ−Ｎｉ−Ａｕ−Ｐｄ−Ａｕ Ｐｄ−Ｎｉ−Ｃｕ−Ｎｉ−Ｐｄ−Ａｕの６層にて形成す
ることを特徴とするものである。According to a fourteenth aspect of the present invention, the metal film is made of silver (Ag) or palladium (Pd), or is made of Ag or Pd.
When the first layer is the outermost layer, the first layer-the second layer-the third layer are formed of Au-nickel (N
i) formed of three layers of -Au, Pd-Ni-Pd, Au-Pd-Au, solder-Ni-Au, and solder-Ni-Pd, or a first layer-second layer-third layer-first layer 4 layers solder
Ni-Pd-Au, Pd-Ni-Pd-Au, Au-P
d-Ni-Pd, Pd-Ni-Au-Pd Solder-Ni-Au-Pd four layers, or the first layer-second layer-third layer-fourth layer-fifth layer is made of Au -Pd
-Ni-Pd-Au, solder-Ni-Au-Pd-Au Pd-Ni-Au-Pd-Au, Au-Pd-Ni-A
u-Pd is formed of five layers of Pd-Ni-Cu-Ni-Pd, or the first layer-second layer-third layer-fourth layer-fifth layer-6 layer is made of Au-Pd-Ni- It is characterized by being formed of six layers of Au-Pd-Au Pd-Ni-Cu-Ni-Pd-Au.

【００１６】請求項１５記載の発明では、リードフレー
ムの所定位置に金属膜を形成する工程と、該リードフレ
ームの所定の位置に半導体チップを搭載する工程と、該
半導体チップの電極パッドと該金属膜とをワイヤまたは
バンプによりボンディングする工程と、該リードフレー
ム面がパッケージの底面となるように該半導体チップを
樹脂モールドする工程と、該リードフレームを除去する
工程とを有することを特徴とするものである。According to a fifteenth aspect of the present invention, a step of forming a metal film at a predetermined position of the lead frame, a step of mounting a semiconductor chip at a predetermined position of the lead frame, an electrode pad of the semiconductor chip and the metal pad A step of bonding the film with a wire or a bump, a step of resin-molding the semiconductor chip so that the lead frame surface becomes the bottom surface of the package, and a step of removing the lead frame. It is.

【００１７】請求項１６記載の発明では、請求項１５に
関し、前記金属膜がメッキにより形成されることを特徴
とするものである。請求項１７記載の発明では、電極パ
ッドを有する電子素子チップと、該チップを封止する封
止樹脂と、該封止樹脂の底面から該底面とほぼ同一平面
で露出する金属膜と、一端が該電極パッドとボンディン
グされ、他端が該金属膜とボンディングされたボンディ
ングワイヤとを有することを特徴とするものである。According to a sixteenth aspect of the present invention, in accordance with the fifteenth aspect, the metal film is formed by plating. In the invention according to claim 17, an electronic element chip having an electrode pad, a sealing resin for sealing the chip, a metal film exposed from the bottom surface of the sealing resin in substantially the same plane as the bottom surface, It has a bonding wire bonded to the electrode pad and the other end bonded to the metal film.

【００１８】請求項１８記載の発明では、電極パッドを
有する電子素子チップと、該チップを封止する封止樹脂
と、該封止樹脂の底面に設けられ、該底面から突出する
樹脂突起と、該樹脂突起上に設けられた金属膜と、該封
止樹脂の底面の該樹脂突起と該チップとの間の領域に形
成され、該金属膜と接続された導電部と、一端が該電極
パッドとボンディングされ、他端が該導電部とボンディ
ングされたボンディングワイヤとを有することを特徴と
するものである。上記の各手段は次のような作用を有す
る。According to the present invention, an electronic element chip having an electrode pad, a sealing resin for sealing the chip, a resin projection provided on a bottom surface of the sealing resin and projecting from the bottom surface, A metal film provided on the resin protrusion, a conductive portion formed on a bottom surface of the sealing resin between the resin protrusion and the chip, and connected to the metal film; And a bonding wire having the other end bonded to the conductive portion. Each of the above means has the following operation.

【００１９】請求項１記載の発明では、従来のＩＣのイ
ンナーリードやアウターリードへの引回しが不要となり
その分の面積が削減できるとともにアウターリード自身
もなくなるので、実装密度も向上できる。また、従来の
ＢＧＡのようなハンダボールを形成するための搭載基板
を用いる必要もない。請求項２記載の発明では、樹脂突
起を設けることにより、金属膜が樹脂パッケージの底面
と同一平面でなくなり、パッケージの反りを吸収できる
とともに、実装時に半田が流れて隣の金属膜と接触する
半田ブリッジも防止できる。また、金属膜を導電部によ
り引き回すことにより、樹脂突起に形成される金属膜の
ピッチを広げることができる。この効果は特に樹脂突起
をパッケージ底面全体に形成するエリアバンプ方式に特
に有効であり、ピッチの狭い凹部にワイヤを打つことな
く狭いピッチのエリアバンプを形成することができる。According to the first aspect of the present invention, it is not necessary to route the conventional IC to the inner lead and the outer lead, so that the area can be reduced and the outer lead itself is eliminated, so that the mounting density can be improved. Also, there is no need to use a mounting substrate for forming solder balls as in a conventional BGA. According to the second aspect of the present invention, by providing the resin protrusion, the metal film is not flush with the bottom surface of the resin package, the warpage of the package can be absorbed, and the solder flows during mounting and comes into contact with the adjacent metal film. Bridges can also be prevented. In addition, the pitch of the metal film formed on the resin protrusion can be increased by drawing the metal film through the conductive portion. This effect is particularly effective in an area bump method in which resin protrusions are formed on the entire bottom surface of the package, and an area bump having a narrow pitch can be formed without hitting a wire in a narrow recess.

【００２０】請求項３記載の発明では、消費電力大きい
チップを搭載した際に、チップの熱を良好に放熱するこ
とができる。請求項４記載の発明では、それほど樹脂突
起のピッチが狭くない時に用いる場合に有効であり、バ
ンプを介してワイヤを金属膜に接続することにより、強
固にワイヤを金属膜に接続することができる。According to the third aspect of the present invention, when a chip with large power consumption is mounted, the heat of the chip can be radiated well. The invention according to claim 4 is effective when used when the pitch of the resin protrusions is not so narrow. By connecting the wire to the metal film via the bump, the wire can be firmly connected to the metal film. .

【００２１】請求項５記載の発明では、バンプを用いる
ことにより、より薄型のパッケージを実現でき、またボ
ンディング箇所が多い場合ワイヤボンディング工程に比
べてフリップチップボンディング工程の方が早いので、
ボンディング時間の短縮もできる。請求項６記載の発明
では、請求項２記載の作用と同様に、金属膜を導電部に
より引き回すことにより、樹脂突起に形成される金属膜
のピッチを広げることができる。According to the fifth aspect of the present invention, a thinner package can be realized by using bumps, and the flip-chip bonding step is faster than the wire bonding step when there are many bonding points.
The bonding time can be reduced. According to the sixth aspect of the invention, similarly to the operation of the second aspect, the pitch of the metal film formed on the resin protrusion can be increased by drawing the metal film through the conductive portion.

【００２２】請求項７記載の発明では、バンプ４２を凹
部４３に嵌合させてボンディングするので、位置合わせ
が容易となる。請求項８記載の発明では、実装時に半田
接合される領域を制限でき、引き回しパターンの酸化等
に起因する特性の劣化を防止でき、半田ブリッジも防止
することができる。According to the seventh aspect of the present invention, since the bumps 42 are fitted into the recesses 43 and bonded, the alignment is facilitated. According to the eighth aspect of the present invention, it is possible to limit a region to be soldered at the time of mounting, prevent deterioration of characteristics due to oxidation of a wiring pattern and the like, and also prevent a solder bridge.

【００２３】請求項９記載の発明では、バンプをリード
フレームに搭載する最、リードフレームの凹部に嵌合さ
せるので、位置合わせを容易にすることができる。請求
項１０記載の発明では、チップ背面が露出しているの
で、チップで発生した熱が外部に放熱しやすくなる。請
求項１１記載の発明では、露出したチップ背面に放熱板
を設けているので、単にチップ背面を露出させた場合よ
り、さらに放熱効率を向上させることができる。According to the ninth aspect of the present invention, since the bump is fitted into the concave portion of the lead frame when the bump is mounted on the lead frame, the positioning can be facilitated. According to the tenth aspect of the present invention, since the back surface of the chip is exposed, heat generated in the chip is easily radiated to the outside. According to the eleventh aspect of the present invention, since the heat radiating plate is provided on the exposed chip rear surface, the heat radiation efficiency can be further improved as compared with the case where the chip rear surface is simply exposed.

【００２４】請求項１２記載の発明では、チップの素子
形成面に絶縁部材４７を形成しておくので、極めて隙間
が小さいチップとリードフレームとの間にモールド樹脂
が入り込み難くなる問題がなくなり、封止の不良といっ
た不都合はなくすことができる。請求項１３記載の発明
では、異方導電樹脂を用いることにより、基板への実装
時に隣接するバンプと電気的にショートする可能性をな
くすことができる。According to the twelfth aspect of the present invention, since the insulating member 47 is formed on the element forming surface of the chip, the problem that it becomes difficult for the molding resin to enter between the chip and the lead frame having a very small gap is eliminated, and the sealing is performed. Inconvenience such as poor stopping can be eliminated. According to the thirteenth aspect of the present invention, by using an anisotropic conductive resin, it is possible to eliminate the possibility of an electrical short-circuit with an adjacent bump during mounting on a substrate.

【００２５】請求項１４記載の発明では、ボンディング
性が良好であることと、半田付け性が良好であることの
要求が満たされる金属膜が得られる。請求項１５記載の
発明では、従来必要とされたリードの切断処理、及びリ
ードを所定形状（例えばガルウィング形状）に成形する
工程は不要となり、半導体装置の製造工程を簡略化する
ことができる。According to the fourteenth aspect of the present invention, it is possible to obtain a metal film which satisfies the requirements of good bonding properties and good solderability. According to the fifteenth aspect of the present invention, the step of cutting the lead and the step of forming the lead into a predetermined shape (for example, a gull wing shape), which are conventionally required, become unnecessary, and the manufacturing process of the semiconductor device can be simplified.

【００２６】請求項１６記載の発明では、金属膜をメッ
キにより形成することにより、多くの金属膜を同時に簡
単に形成することができる。According to the sixteenth aspect of the present invention, since the metal film is formed by plating, many metal films can be simultaneously formed easily.

【００２７】[0027]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

〔第１実施形態〕以下本発明の実施形態を、図１〜３２
により具体的に説明する。図１は、本発明の第１実施形
態を示す断面図であり、図２はその底面透視図である。
図１は図２において点線で示される部分にて切断したも
のを示している。図中、１１はチップ、１２は電極パッ
ド、１３はボンディングワイヤ、１４は樹脂パッケー
ジ、１５は金属膜、を示している。なお、以下の実施形
態では、チップの代表例として半導体チップを用いて説
明しているが、この他に表面弾性波デバイス（ＳＡＷデ
バイス）やマルチチップモジュール（ＭＣＭモジュー
ル）を用いてもよい。[First Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
This will be described more specifically. FIG. 1 is a sectional view showing a first embodiment of the present invention, and FIG. 2 is a bottom perspective view thereof.
FIG. 1 shows a section taken along the dotted line in FIG. In the figure, 11 is a chip, 12 is an electrode pad, 13 is a bonding wire, 14 is a resin package, and 15 is a metal film. In the following embodiments, a semiconductor chip is described as a typical example of a chip, but a surface acoustic wave device (SAW device) or a multi-chip module (MCM module) may be used.

【００２８】この半導体装置は、チップ１１上の電極パ
ッド１２に対し、ボンディングワイヤー１３の一端がボ
ンディングされ、その他端がモールド樹脂により構成さ
れた樹脂パッケージ１４の底面より露出する金属膜１５
にボンディングされている。金属膜１５と樹脂パッケー
ジ底面とはほぼ同一平面となっている。この金属膜１５
は、幅０．４mm, 長さ０．７５mm, 高さ１０μで形成さ
れ、そのピッチは０．６５mmで形成されている。In this semiconductor device, one end of a bonding wire 13 is bonded to an electrode pad 12 on a chip 11 and the other end is exposed from a bottom surface of a resin package 14 made of a mold resin.
Bonding. The metal film 15 and the bottom surface of the resin package are substantially flush with each other. This metal film 15
Are formed with a width of 0.4 mm, a length of 0.75 mm, and a height of 10 μ, and a pitch of 0.65 mm.

【００２９】この構造により、従来のＩＣのインナーリ
ードやアウターリードへの引回しが不要となりその分の
面積が削減できるとともにアウターリード自身もなくな
るので、実装密度も向上できる。また、従来のＢＧＡの
ようなハンダボールを形成するための搭載基板を用いる
必要もない。金属膜１５は、前記のようにワイヤ１３に
より半導体素子１１と電気的に接続する構成とされてい
る。また、この金属膜１５は半導体装置の外部接続端子
として機能するものであり、半導体装置を実装基板（図
示せず）に実装する時には、金属膜１５は実装基板に形
成された電極部に半田付けされる。With this structure, it is not necessary to route the conventional IC to the inner leads and the outer leads, so that the area can be reduced and the outer leads themselves can be eliminated, so that the mounting density can be improved. Also, there is no need to use a mounting substrate for forming solder balls as in a conventional BGA. The metal film 15 is configured to be electrically connected to the semiconductor element 11 by the wire 13 as described above. The metal film 15 functions as an external connection terminal of the semiconductor device. When the semiconductor device is mounted on a mounting substrate (not shown), the metal film 15 is soldered to an electrode portion formed on the mounting substrate. Is done.

【００３０】この金属膜１５は、単層の金属層により形
成しても、また複数の金属層を積層して形成した構成と
してもよい。次に、金属膜１５について図３〜図６を用
いて説明する。各図は、金属膜１５の配設位置近傍を拡
大して示す図である。図３は単層の金属層により金属膜
１５Ａを形成したものであり、図４〜図６は複数の金属
層を積層して金属膜１５Ｂ〜１５Ｄを形成したものであ
る。The metal film 15 may be formed by a single metal layer, or may be formed by laminating a plurality of metal layers. Next, the metal film 15 will be described with reference to FIGS. Each drawing is an enlarged view showing the vicinity of the disposition position of the metal film 15. FIG. 3 shows a metal film 15A formed by a single metal layer, and FIGS. 4 to 6 show metal films 15B to 15D formed by laminating a plurality of metal layers.

【００３１】金属膜１５（１５Ａ〜１５Ｄ）の材質を選
定するに際し、前記のように金属膜１５はその内側にワ
イヤ１３が接続されると共に外側は実装基板に半田付け
が行われるため、金属膜１５の最内層はボンディング性
が良好であることが要求され、また最外層は半田付け性
が良好であることが要求される（以下、この金属膜１５
に要求される条件を金属膜要求特性という）。この金属
膜要求特性を満たす金属膜１５（１５Ａ〜１５Ｄ）の材
質としては、次のようなものが考えられる。When selecting the material of the metal film 15 (15A to 15D), the metal film 15 is connected to the wire 13 on the inside and soldered to the mounting substrate on the outside as described above. The innermost layer 15 is required to have good bonding properties, and the outermost layer is required to have good soldering properties (hereinafter, this metal film 15).
The condition required for the metal film is called a metal film required characteristic). As the material of the metal film 15 (15A to 15D) satisfying the required characteristics of the metal film, the following materials can be considered.

【００３２】図３に示される単層の金属膜１５Ａでは、
金属膜１５Ａの材質としてボンディング性及び半田付け
性が共に良好な材質を選定する必要がある。これを満足
する材料としては、例えば銀（Ａｇ），或いはパラジウ
ム（Ｐｄ）がある。また、図４に示されるような外層１
５Ｂ-1と内層１５Ｂ-2とを積層した２層構造の金属膜１
５Ｂでは、金属膜要求特性を満たす外層１５Ｂ-1と内層
１５Ｂ-2との組み合わせとして、外層１５Ｂ-1をパラジ
ウム（Ｐｄ）により厚さ０．０５〜２μｍで形成し、内
層１５Ｂ-2を金（Ａｕ）により厚さ１０Å〜０．５μｍ
で形成する組み合わせが考えられる。またＡｕとＰｄの
順番は逆でもよい。In the single-layer metal film 15A shown in FIG.
It is necessary to select a material having good bonding and soldering properties as the material of the metal film 15A. Materials satisfying this include, for example, silver (Ag) or palladium (Pd). The outer layer 1 as shown in FIG.
Metal film 1 having a two-layer structure in which 5B-1 and inner layer 15B-2 are laminated.
5B, as the combination of the outer layer 15B-1 and the inner layer 15B-2 satisfying the required properties of the metal film, the outer layer 15B-1 is formed with palladium (Pd) to a thickness of 0.05 to 2 μm, and the inner layer 15B-2 is formed of gold. (Au) 10 ~ 0.5μm thick
Can be considered. The order of Au and Pd may be reversed.

【００３３】また、図５に示されるような外層１５Ｃ-
1，中間層１５Ｃ-2, 内層１５Ｃ-3とを積層した３層構
造の金属膜１５Ｃでは、外層１５Ｃ-1を金（Ａｕ）によ
り厚さ１０Å〜０．５μｍで形成し、中間層１５Ｃ-2を
ニッケル（Ｎｉ）により厚さ０．５〜２０μｍで形成
し、内層１５Ｃ-3を金（Ａｕ）により厚さ０．１〜０．
５μｍで形成する組み合わせが考えられる。The outer layer 15C- as shown in FIG.
1. In the metal film 15C having a three-layer structure in which the intermediate layer 15C-2 and the inner layer 15C-3 are laminated, the outer layer 15C-1 is formed of gold (Au) to a thickness of 10Å to 0.5 μm, and the intermediate layer 15C- 2 is formed of nickel (Ni) with a thickness of 0.5 to 20 μm, and the inner layer 15C-3 is formed of gold (Au) with a thickness of 0.1 to 0.2 μm.
A combination formed at 5 μm is conceivable.

【００３４】また、他の組み合わせとしては、 ・外層１５Ｃ-1に金（Ａｕ），中間層１５Ｃ-2にニッケ
ル（Ｎｉ），内層１５Ｃ-3に金（Ａｕ）を用いる組み合
わせ ・外層１５Ｃ-1にパラジウム（Ｐｄ），中間層１５Ｃ-2
にニッケル（Ｎｉ），内層１５Ｃ-3にパラジウム（Ｐ
ｄ）を用いる組み合わせ ・外層１５Ｃ-1に金（Ａｕ），中間層１５Ｃ-2にパラジ
ウム（Ｐｄ），内層１５Ｃ-3に金（Ａｕ）を用いる組み
合わせ ・外層１５Ｃ-1に半田，中間層１５Ｃ-2にニッケル（Ｎ
ｉ），内層１５Ｃ-3に金（Ａｕ）を用いる組み合わせ ・外層１５Ｃ-1に半田，中間層１５Ｃ-2にニッケル（Ｎ
ｉ），内層１５Ｃ-3にパラジウム（Ｐｄ）を用いる組み
合わせが考えられる。上記した各組み合わせにより金属
膜１５Ｃを構成することにより、金属膜要求特性を満た
すと共に、中間層１５Ｃ-2による外層１５Ｃ-1と内層１
５Ｃ-3との接合性を向上することができる。Other combinations include a combination using gold (Au) for the outer layer 15C-1, nickel (Ni) for the intermediate layer 15C-2, and gold (Au) for the inner layer 15C-3. On palladium (Pd), middle layer 15C-2
Nickel (Ni) and palladium (P
Combination using d)-Combination using gold (Au) for outer layer 15C-1, palladium (Pd) for intermediate layer 15C-2, and gold (Au) for inner layer 15C-3-Solder for outer layer 15C-1 and intermediate layer 15C -2 to nickel (N
i) Combination using gold (Au) for the inner layer 15C-3. Solder for the outer layer 15C-1 and nickel (N
i), a combination using palladium (Pd) for the inner layer 15C-3 is conceivable. By configuring the metal film 15C by the above-described combinations, the required characteristics of the metal film are satisfied, and the outer layer 15C-1 and the inner layer 1 formed by the intermediate layer 15C-2 are satisfied.
The bondability with 5C-3 can be improved.

【００３５】また、図６に示されるような外層１５Ｄ-
1，第１中間層１５Ｄ-2, 第２中間層１５Ｄ-3, 内層１
５Ｄ-4とを積層した４層構造の金属膜１５Ｄでは、外層
１５Ｄ-1を半田により厚さ５〜２０μｍ形成し、第１中
間層１５Ｄ-2をニッケル（Ｎｉ）により厚さ１〜２０μ
ｍで形成し、第２中間層１５Ｄ-3をパラジウム（Ｐｄ）
により厚さ０．０５〜２μｍで形成し、内層１５Ｄ-4を
金（Ａｕ）により厚さ１０Å〜０．５μｍで形成する組
み合わせが考えられる。The outer layer 15D- as shown in FIG.
1, first intermediate layer 15D-2, second intermediate layer 15D-3, inner layer 1
In the metal film 15D having a four-layer structure laminated with 5D-4, the outer layer 15D-1 is formed with a thickness of 5 to 20 μm by soldering, and the first intermediate layer 15D-2 is formed of nickel (Ni) with a thickness of 1 to 20 μm.
m, and the second intermediate layer 15D-3 is formed of palladium (Pd).
In which the inner layer 15D-4 is formed of gold (Au) with a thickness of 10 ° to 0.5 μm.

【００３６】また、他の組み合わせとしては、外層１５
Ｄ-1をパラジウム（Ｐｄ）により厚さ０．０５〜２μｍ
形成し、第１中間層１５Ｄ-2をニッケル（Ｎｉ）により
厚さ１〜２０μｍ形成し、第２中間層１５Ｄ-3をパラジ
ウム（Ｐｄ）により厚さ１０Å〜０．５μｍ形成し、内
層１５Ｄ-4を金（Ａｕ）により厚さ１０Å〜０．５μｍ
形成する組み合わせとしてもよい。（この構造をＰｄ−
Ｎｉ−Ｐｄ−Ａｕと表示するものとし、以下省略して示
す。） また、Ａｕ−Ｐｄ−Ｎｉ−Ｐｄ，Ｐｄ−Ｎｉ−Ａｕ−Ｐ
ｄ 半田−Ｎｉ−Ａｕ−Ｐｄ でもよい。As another combination, the outer layer 15
D-1 is made of palladium (Pd) and has a thickness of 0.05 to 2 μm.
The first intermediate layer 15D-2 is formed of nickel (Ni) with a thickness of 1 to 20 μm, the second intermediate layer 15D-3 is formed of palladium (Pd) with a thickness of 10 ° to 0.5 μm, and the inner layer 15D- 4 is made of gold (Au) and has a thickness of 10 mm to 0.5 μm.
It may be a combination to form. (This structure is called Pd-
It is indicated as Ni-Pd-Au, and is omitted below. ) Also, Au-Pd-Ni-Pd, Pd-Ni-Au-P
d Solder-Ni-Au-Pd may be used.

【００３７】上記した各組み合わせにより金属膜１５Ｄ
を構成することにより、金属膜要求特性を満たすと共
に、第１及び第２中間層１５Ｄ-2，１５Ｄ-3による外層
１５Ｄ-1と内層１５Ｄ-4との接合性を向上することがで
きる。さらに、図示しないが、層構造を５層とし、以下
の組み合わせでもよい。 Ａｕ−Ｐｄ−Ｎｉ−Ｐｄ−Ａｕ，半田−Ｎｉ−Ａｕ−Ｐ
ｄ−Ａｕ Ｐｄ−Ｎｉ−Ａｕ−Ｐｄ−Ａｕ，Ａｕ−Ｐｄ−Ｎｉ−Ａ
ｕ−Ｐｄ Ｐｄ−Ｎｉ−ＣｕーＮｉ−Ｐｄ これも図示しないが、６層構造でＡｕ−Ｐｄ−Ｎｉ−Ａ
ｕ−Ｐｄ−Ａｕ Ｐｄ−Ｎｉ−Ｃｕ−Ｎｉ−Ｐｄ−Ａｕの組み合わせでも
よい。続いて、上記した第１実施形態に係る半導体装置
の製造方法について説明する。尚、以下の説明では、金
属膜１５として外層１５Ｃ-1，中間層１５Ｃ-2, 内層１
５Ｃ-3とを積層した３層構造の金属膜１５Ｃを設けた構
成を例に挙げて説明するものとする。The metal film 15D is formed by the above combinations.
With this configuration, the required characteristics of the metal film can be satisfied, and the bonding property between the outer layer 15D-1 and the inner layer 15D-4 by the first and second intermediate layers 15D-2 and 15D-3 can be improved. Further, although not shown, the layer structure may be five layers, and the following combinations may be used. Au-Pd-Ni-Pd-Au, solder-Ni-Au-P
d-Au Pd-Ni-Au-Pd-Au, Au-Pd-Ni-A
u-Pd Pd-Ni-Cu-Ni-Pd Although not shown, Au-Pd-Ni-A has a six-layer structure.
u-Pd-Au A combination of Pd-Ni-Cu-Ni-Pd-Au may be used. Subsequently, a method of manufacturing the semiconductor device according to the first embodiment will be described. In the following description, the outer layer 15C-1, the intermediate layer 15C-2, the inner layer 1
The configuration in which a three-layer metal film 15C formed by laminating 5C-3 is provided will be described as an example.

【００３８】半導体装置は、図１２に示されるリードフ
レーム２０を用いて製造される。このリードフレーム２
０は、導電性金属基材２１の所定の位置に金属膜１５Ｃ
が形成された構成とされている。また後述するように、
リードフレーム２０は複数の半導体装置を一括的に形成
できるよう（即ち、いわゆる複数個取りができるよう）
構成されており、従って金属膜１５Ｃは１枚の金属基材
２１に複数組形成されている（図９参照）。尚、図中２
３はリードフレーム２０をハンドリングする時に治具が
係合する治具穴である。The semiconductor device is manufactured using the lead frame 20 shown in FIG. This lead frame 2
0 is a metal film 15C at a predetermined position on the conductive metal substrate 21.
Is formed. Also, as described below,
The lead frame 20 is formed so that a plurality of semiconductor devices can be formed collectively (that is, so-called a plurality can be obtained).
Thus, a plurality of sets of metal films 15C are formed on one metal base 21 (see FIG. 9). In addition, 2 in the figure
Reference numeral 3 denotes a jig hole with which the jig is engaged when the lead frame 20 is handled.

【００３９】ここで、半導体装置の製造方法を説明する
前に、先ずリードフレーム２０の製造方法について図７
〜図１2 を用いて説明する。リードフレーム２０を製造
するには、先ず図７に示すように、導電材料（例えば
銅）よりなる平板状の金属基材２１を用意し、この金属
基材２１の上下両面にエッチングレジスト２４を塗布す
る（レジスト塗布工程）。このエッチングレジスト２４
は、例えば感光性樹脂であり、コーター等を用いて所定
膜厚に塗布される。なお、エッチングレジストを塗布す
る前に、リードフレームの端部にスタンピング等により
治具穴を形成しておく。Here, before explaining the method of manufacturing the semiconductor device, first, the method of manufacturing the lead frame 20 will be described with reference to FIG.
This will be described with reference to FIGS. In order to manufacture the lead frame 20, first, as shown in FIG. 7, a flat metal substrate 21 made of a conductive material (for example, copper) is prepared, and an etching resist 24 is applied to both upper and lower surfaces of the metal substrate 21. (Resist coating step). This etching resist 24
Is a photosensitive resin, for example, and is applied to a predetermined film thickness using a coater or the like. Before applying the etching resist, a jig hole is formed in the end of the lead frame by stamping or the like.

【００４０】次に、エッチングレジスト２４に図示しな
いマスクを用いて露光処理を行い、その後に現像処理を
行うことによりエッチングレジスト２４の金属膜形成位
置に対応する部位を除去し、図８に示すレジストパター
ン２４ａを形成する（レジストパターン形成工程）。ま
た、本実施例ではこのレジストパターン形成工程におい
て、給電部２５の形成位置（給電部形成位置）に対応す
る部位に配設されたエッチングレジスト２４を除去する
構成としている。尚、給電部２５は、後述する金属膜形
成工程においてメッキ電極が配設される部位である（図
９参照）。Next, an exposure process is performed on the etching resist 24 using a mask (not shown), and then a development process is performed to remove a portion of the etching resist 24 corresponding to the metal film forming position. The pattern 24a is formed (resist pattern forming step). Further, in the present embodiment, in the resist pattern forming step, the etching resist 24 provided at the position corresponding to the formation position of the power supply unit 25 (the power supply unit formation position) is removed. The power supply section 25 is a portion where a plating electrode is provided in a metal film forming step described later (see FIG. 9).

【００４１】図９に示されるように、この給電部２５は
金属基材２１の長手方向両端部に夫々形成されており、
この給電部２５では導電性金属よりなる金属基材２１が
露出した状態となっている。このため、給電部２５にメ
ッキ用電極を配設することにより、金属基材２１に所定
の電位を印加することが可能となる。また、図９に矢印
Ａで示す矩形状の破線は１個の半導体装置の形成領域を
示しているが、同図に示されるように１枚の金属基材２
１には複数個（図１１に示す例では３４個）の半導体装
置が一括的に形成されるよう（多数個取りができるよ
う）構成されている。As shown in FIG. 9, the power supply portions 25 are formed at both ends of the metal base 21 in the longitudinal direction, respectively.
In the power supply unit 25, the metal base 21 made of a conductive metal is exposed. For this reason, by disposing the plating electrode in the power supply unit 25, it is possible to apply a predetermined potential to the metal base 21. Further, a rectangular broken line indicated by an arrow A in FIG. 9 indicates a formation region of one semiconductor device, but as shown in FIG.
1 is configured such that a plurality of (three in the example shown in FIG. 11) semiconductor devices are formed collectively (so that a large number of semiconductor devices can be obtained).

【００４２】ところで、更なる多数個取りを行うため
に、図１０に示されるように、枠状部２６に左右一対の
連結部２７を介して複数個の金属基材２１が連結された
リードフレームユニット２８を形成することが考えられ
る。この構成においても給電部２５を形成する必要があ
るが、複数の金属基材２１は連結部２７を介して枠状部
２６に電気的に接続されているため、枠状部２６に給電
部２５を形成することにより複数の金属基材２１に一括
的に給電することが可能となる。As shown in FIG. 10, a lead frame in which a plurality of metal bases 21 are connected to a frame 26 via a pair of left and right connecting portions 27 in order to perform further multi-piece mounting. It is conceivable to form a unit 28. In this configuration as well, it is necessary to form the power supply portion 25, but since the plurality of metal bases 21 are electrically connected to the frame portion 26 via the connection portions 27, the power supply portion 25 is formed on the frame portion 26. Is formed, it is possible to collectively supply power to the plurality of metal bases 21.

【００４３】よって、上記構成とすることにより半導体
装置の製造効率を更に向上できると共に、各金属基材２
１に給電部２５を形成する構成に比べてレジストパター
ン形成工程及び金属膜のメッキ工程を簡単化することが
できる。金属膜形成位置のレジストも窓開けが終わる
と、続いて金属膜形成工程が実施され金属膜１５Ｃが形
成される。本実施例においては、金属膜１５Ｃの形成に
メッキ法を用いており、前記した給電部２５にメッキ用
電極を配設すると共に、金属基材２１をメッキ槽に浸漬
して電界メッキを行う。Therefore, with the above configuration, the manufacturing efficiency of the semiconductor device can be further improved, and each metal substrate 2
1, the resist pattern forming step and the metal film plating step can be simplified as compared with the configuration in which the power supply unit 25 is formed. When the opening of the resist at the metal film forming position is completed, a metal film forming step is subsequently performed to form a metal film 15C. In the present embodiment, a plating method is used to form the metal film 15C, and a plating electrode is provided in the above-described power supply unit 25, and the metal substrate 21 is immersed in a plating bath to perform electrolytic plating.

【００４４】本実施例に係る金属膜１５Ｃは、外層１５
Ｃ-1, 中間層１５Ｃ-2, 及び内層１５Ｃ-3を積層した３
層構造とされているため、各層毎にメッキ処理を行う。
具体的には、外層１５Ｃ-1として金（Ａｕ）, 中間層１
５Ｃ-2としてパラジウム（Ｐｄ）, 内層１５Ｃ-3として
金（Ａｕ）を用いた場合には、先ず内層１５Ｃ-3となる
金メッキを行い、続いて中間層１５Ｃ-2となるパラジウ
ムメッキを行い、最後に外層１５Ｃ-1となる金メッキを
行う。この金属膜１５Ｃを構成する各層１５Ｃ-1〜１５
Ｃ-3の厚さは、メッキ時間を制御することにより任意に
設定することができる。図１１は金属膜１５Ｃが形成さ
れた金属基材２１を示している。The metal film 15C according to the present embodiment has the outer layer 15
C-1, an intermediate layer 15C-2, and an inner layer 15C-3
Because of the layer structure, plating is performed for each layer.
Specifically, as the outer layer 15C-1, gold (Au), the intermediate layer 1
When palladium (Pd) is used as the 5C-2 and gold (Au) is used as the inner layer 15C-3, first, gold plating for the inner layer 15C-3 is performed, and then palladium plating for the intermediate layer 15C-2 is performed. Finally, gold plating for the outer layer 15C-1 is performed. Each layer 15C-1 to 15C constituting the metal film 15C
The thickness of C-3 can be arbitrarily set by controlling the plating time. FIG. 11 shows the metal base 21 on which the metal film 15C is formed.

【００４５】上記の処理を実施することにより金属膜１
５Ｃは金属基材２１に形成されるが、後に説明するよう
に分離工程において、金属基材２１に形成された金属膜
１５Ｃは、樹脂パッケージ１２をリードフレーム２０か
ら分離する際に、樹脂パッケージ１２と共にリードフレ
ーム２０から離脱する必要がある。このため、金属膜１
５Ｃは金属基材２１に対しある程度の分離性も要求され
る。By performing the above processing, the metal film 1
5C is formed on the metal base 21, but as will be described later, the metal film 15C formed on the metal base 21 separates the resin package 12 from the lead frame 20 in the separation step. Together with the lead frame 20. Therefore, the metal film 1
5C also requires a certain degree of separation from the metal substrate 21.

【００４６】従って、金属膜１５Ｃを形成するのに先立
ち、上記分離性を確保するために、金属膜を形成する領
域に導電性のペースト等の分離性を向上させる部材を塗
布しておき、その上部に金属膜１５Ｃを形成する構成と
してもよい。尚、上記した金属膜形成工程では、メッキ
法を用いて金属膜１５Ｃを形成する方法を説明したが、
金属膜１５Ｃの形成はメッキ法に限定されるものではな
く、例えば蒸着法，スパッタリング法等の他の膜形成技
術を用いて形成する構成としてもよい。Therefore, prior to the formation of the metal film 15C, in order to secure the above-mentioned separation property, a member for improving the separation property such as a conductive paste is applied to the region where the metal film is to be formed. A configuration in which the metal film 15C is formed on the upper portion may be employed. In the above-described metal film forming step, a method of forming the metal film 15C using a plating method has been described.
The formation of the metal film 15C is not limited to the plating method, and may be formed by using another film forming technique such as a vapor deposition method or a sputtering method.

【００４７】上記のように金属膜形成工程において所定
の場所に金属膜１５Ｃが形成されると、続いてレジスト
パターン２４ａ（エッチングレジスト２４）を除去する
レジスト除去工程が実施され、図１２に示されるリード
フレーム２０が形成される。上記したリードフレーム２
０の製造方法では、レジスト塗布，レジストパターン形
成，金属膜形成，及びレジスト除去等の簡単な工程によ
りリードフレーム２０を形成することができる。When the metal film 15C is formed at a predetermined position in the metal film forming step as described above, a resist removing step of removing the resist pattern 24a (etching resist 24) is subsequently performed, as shown in FIG. The lead frame 20 is formed. Lead frame 2 described above
In the manufacturing method 0, the lead frame 20 can be formed by simple steps such as resist coating, resist pattern formation, metal film formation, and resist removal.

【００４８】次に、上記のようにして製造されるリード
フレーム２０を用いて半導体装置を製造する製造方法に
ついて図１３乃至図２２を用いて説明する。半導体装置
を製造するには、図１３に示すように、リードフレーム
２０の所定チップ搭載位置にチップ固定樹脂１６を塗布
すると共に、チップ固定樹脂１６の上部に半導体チップ
１１を搭載する（チップ搭載工程）。チップ固定樹脂１
６は絶縁性を有すると共に接着剤として機能し、よって
半導体チップ１１はリードフレーム２０上にチップ固定
樹脂１６の接着力により搭載された状態となる。Next, a method of manufacturing a semiconductor device using the lead frame 20 manufactured as described above will be described with reference to FIGS. In order to manufacture a semiconductor device, as shown in FIG. 13, a chip fixing resin 16 is applied to a predetermined chip mounting position of a lead frame 20, and a semiconductor chip 11 is mounted on the chip fixing resin 16 (chip mounting step). ). Chip fixing resin 1
Numeral 6 has an insulating property and also functions as an adhesive, so that the semiconductor chip 11 is mounted on the lead frame 20 by the adhesive force of the chip fixing resin 16.

【００４９】チップ搭載工程が終了すると、リードフレ
ーム２０はワイヤボンディング装置に装着され、図１４
に示されるように、半導体チップ１１に形成された電極
パッド１２と、リードフレーム２０に形成されている金
属膜１５Ｃ（具体的には、内層内層１５Ｃ-3）との間に
ワイヤ１３を配設し、半導体チップ１１と金属膜１５Ｃ
とを電気的に接続する（接続工程）。When the chip mounting process is completed, the lead frame 20 is mounted on a wire bonding apparatus,
As shown in FIG. 1, a wire 13 is provided between an electrode pad 12 formed on a semiconductor chip 11 and a metal film 15C (specifically, an inner layer 15C-3) formed on a lead frame 20. And the semiconductor chip 11 and the metal film 15C
Are electrically connected to each other (connection step).

【００５０】このワイヤ１３を電極パッド１２と金属膜
１５Ｃとの間でワイヤボンディングする際、図１４に示
す例では、先ず電極パッド１２にワイヤ１３の一端をボ
ンディングし（ファーストボンディング）し、続いてワ
イヤ１３の他端を金属膜１５Ｃにボンディング（セカン
ドボンディング）する方法を採用した。また、図１５に
示すように、先ず金属膜１５Ｃにワイヤ１３の一端を接
続し、続いて金属膜１５Ｃから電極パッド１２にワイヤ
１３を引き出した上で、ワイヤ１３の他端部を電極パッ
ド１２に接続する方法を採用してもよい。When the wire 13 is wire-bonded between the electrode pad 12 and the metal film 15C, in the example shown in FIG. 14, one end of the wire 13 is first bonded to the electrode pad 12 (first bonding), and subsequently, A method of bonding (second bonding) the other end of the wire 13 to the metal film 15C was adopted. As shown in FIG. 15, first, one end of the wire 13 is connected to the metal film 15C, and then the wire 13 is drawn out from the metal film 15C to the electrode pad 12, and the other end of the wire 13 is connected to the electrode pad 12 as shown in FIG. May be adopted.

【００５１】このように、先ず金属膜１５Ｃにワイヤ１
３の一端を接続し、その後にワイヤ１３の他端部を電極
パッド１２に接続する、いわゆる逆打ちのワイヤボンデ
ィング法を用いたことにより、ワイヤループの低背化を
図ることができ、これに伴い半導体装置の低背化を図る
ことができる。また、一般に電極パッド１２の配設ピッ
チは金属膜１５Ｃの配設ピッチに比べて狭く、またワイ
ヤボンディング処理においてファーストボンディングの
ボンディング領域はセカンドボンディングのボンディン
グ領域よりも広い。よって、配設ピッチの広い金属膜１
５Ｃにファーストボンディングを行い、配設ピッチの狭
い電極パッド１２にセカンドボンディングを行う構成と
することにより、高密度にワイヤ１３の配設を行うこと
が可能となる。As described above, first, the wire 1 is applied to the metal film 15C.
3 is connected, and then the other end of the wire 13 is connected to the electrode pad 12, so that a so-called reverse wire bonding method is used, so that the wire loop can be reduced in height. Accordingly, the height of the semiconductor device can be reduced. In general, the arrangement pitch of the electrode pads 12 is narrower than the arrangement pitch of the metal films 15C, and the bonding region of the first bonding in the wire bonding process is wider than the bonding region of the second bonding. Therefore, the metal film 1 having a wide arrangement pitch
By performing the first bonding on 5C and the second bonding on the electrode pads 12 having a narrow arrangement pitch, the wires 13 can be arranged at a high density.

【００５２】上記の接続工程が終了すると、続いてリー
ドフレーム２０上に半導体チップ１１を封止するよう樹
脂モールドを施し樹脂パッケージ１４を形成する封止工
程を実施する。本実施例では、樹脂パッケージ１４をモ
ールド成形する方法について説明するが、ボッティング
により形成することも可能である。図１６は、接続工程
が終了したリードフレーム２０をモールド金型に装着し
て樹脂２９（梨地で示す）をモールドした直後の状態を
示す概略構成図であり、３０はカル，３１はランナー，
３２はゲートを夫々示している。同図に示されるよう
に、樹脂パッケージ１４はリードフレーム２０に一括的
に複数個形成される。尚、モールド直後の状態では、複
数個形成された各樹脂パッケージ１４はゲート３２に存
在する樹脂２９（以下、ゲート内樹脂という）により連
結した状態となっている。When the above connection step is completed, subsequently, a sealing step of forming a resin package 14 by applying a resin mold to seal the semiconductor chip 11 on the lead frame 20 is performed. In the present embodiment, a method of molding the resin package 14 will be described, but the resin package 14 may be formed by botting. FIG. 16 is a schematic configuration diagram showing a state immediately after the lead frame 20 after the connection process is mounted on a mold and resin 29 (shown in satin) is molded, where 30 is a cull, 31 is a runner,
Reference numeral 32 denotes each gate. As shown in the figure, a plurality of resin packages 14 are collectively formed on a lead frame 20. Immediately after the molding, the plurality of resin packages 14 formed are connected by a resin 29 (hereinafter, referred to as a resin in the gate) existing in the gate 32.

【００５３】図１７は、１個の半導体装置に対応する樹
脂パッケージ１４を拡大して示す図である。同図に示さ
れるように、樹脂はモールド金型（上型）に形成されて
いるキャビティ（図示せず）により所定形状に形成され
ると共に、リードフレーム２０が下型の機能を奏してい
る。この状態において、樹脂パッケージ１４は図１８に
示されるようにリードフレーム２０に添着された状態と
されている。FIG. 17 is an enlarged view showing the resin package 14 corresponding to one semiconductor device. As shown in the figure, the resin is formed into a predetermined shape by a cavity (not shown) formed in a mold (upper die), and the lead frame 20 has a lower mold function. In this state, the resin package 14 is attached to the lead frame 20 as shown in FIG.

【００５４】上記のように樹脂パッケージ１４が形成さ
れると、各樹脂パッケージ１４間に形成されていたゲー
ト内樹脂，ランナー３１内に残存した樹脂，及びカル３
０は除去され、各樹脂パッケージ１４は個々独立した構
成となる。しかるに、前述したように各樹脂パッケージ
１４はリードフレーム２０に添着された状態となってい
るため、個々独立した状態となっても各樹脂パッケージ
１４がリードフレーム２０から離脱することはない。When the resin packages 14 are formed as described above, the resin in the gate formed between the resin packages 14, the resin remaining in the runner 31, and the cull 3
0 is removed, and each resin package 14 becomes an independent configuration. However, since each resin package 14 is attached to the lead frame 20 as described above, each resin package 14 does not separate from the lead frame 20 even when they become independent.

【００５５】上記した封止工程が終了すると、続いてテ
ープ配設工程が実施される。テープ配設工程では、図１
９に示されるように個々独立した状態とされた各樹脂パ
ッケージ１４の上部に接着テープ等のテープ部材３３
（ハッチングを付して示している）を配設する。このテ
ープ部材３３は、ベーステープの一面に接着剤を塗布し
た構成とされており、またベーステープは後に実施され
る分離工程において用いるエッチング液により損傷を受
けない材料により形成されている。このように、複数の
樹脂パッケージ１４の上部をテープ部材３３で連結する
ことにより、リードフレーム２０から各樹脂パッケージ
１４を分離しても、個々の樹脂パッケージ１４をテープ
部材３３により位置規制することができる。When the above sealing step is completed, a tape arranging step is subsequently performed. In the tape installation process,
As shown in FIG. 9, a tape member 33 such as an adhesive tape is provided on the upper part of each resin package 14 which is in an independent state.
(Indicated by hatching). The tape member 33 has a configuration in which an adhesive is applied to one surface of a base tape, and the base tape is formed of a material that is not damaged by an etchant used in a separation process performed later. As described above, by connecting the upper portions of the plurality of resin packages 14 with the tape member 33, even if each resin package 14 is separated from the lead frame 20, the position of each resin package 14 can be regulated by the tape member 33. it can.

【００５６】尚、このテープ部材３３を配設するタイミ
ングは、樹脂パッケージ１４が形成された後に限定され
るものではなく、例えば封止工程実施前にモールド金型
内に配設しておくことにより、形成された時点で複数の
樹脂パッケージ１４がテープ部材３３により連結される
構成としてもよい。上記したテープ配設工程が終了する
と、続いて樹脂パッケージ１４をリードフレーム２０か
ら分離され半導体装置を形成する分離工程が実施され
る。図２０は分離工程を示しており、同図に示す例では
リードフレーム２０をエッチング液に浸漬させて溶解す
ることにより樹脂パッケージ１２をリードフレーム２０
から分離させる方法が示されている。The timing of disposing the tape member 33 is not limited to the timing after the resin package 14 is formed. For example, the timing of disposing the tape member 33 in a molding die before the encapsulating step is performed. A plurality of resin packages 14 may be connected by a tape member 33 when formed. When the above-described tape arranging step is completed, subsequently, a separating step of separating the resin package 14 from the lead frame 20 and forming a semiconductor device is performed. FIG. 20 shows a separation step. In the example shown in FIG. 20, the lead frame 20 is immersed in an etching solution to dissolve the resin package 12 so that the resin
The method of separating from the target is shown.

【００５７】この分離工程で用いられるエッチング液
は、リードフレーム２０のみを溶解し、金属膜１５Ｃは
溶解しない性質を有するエッチング液（例えば、アンモ
ニア系アルカリエッチャント）を選定している。従っ
て、リードフレーム２０が完全に溶解されることにより
樹脂パッケージ１４はリードフレーム２０から分離され
る。この際、金属膜１５Ｃは樹脂パッケージ１４の底面
に配設された状態となるため、図１に示す半導体装置が
形成される。As an etching solution used in this separation step, an etching solution (for example, an ammonia-based alkali etchant) having a property of dissolving only the lead frame 20 and not dissolving the metal film 15C is selected. Therefore, the resin package 14 is separated from the lead frame 20 by completely dissolving the lead frame 20. At this time, since the metal film 15C is disposed on the bottom surface of the resin package 14, the semiconductor device shown in FIG. 1 is formed.

【００５８】上記のように、リードフレーム２０を溶解
することにより樹脂パッケージ１４をリードフレーム２
０から分離する方法を用いることにより、リードフレー
ム２０からの樹脂パッケージ１４の分離処理を確実かつ
容易に行うことができ、歩留りを向上することができ
る。図２１は、分離工程が終了した状態を示している。
同図に示されるように、分離工程が終了した時点で複数
の半導体装置はテープ部材３３に接着された状態を維持
している。従って、分離工程の終了後における半導体装
置の扱いを容易とすることができる。更に、図２１に示
される状態でテープ部材３３を巻回し出荷することによ
り、チップ部品と同様に実装時において半導体装置を実
装基板に自動装填を行うことも可能となる。As described above, by dissolving the lead frame 20, the resin package 14 is connected to the lead frame 2.
By using the method of separating from the lead frame 20, the separation process of the resin package 14 from the lead frame 20 can be performed reliably and easily, and the yield can be improved. FIG. 21 shows a state in which the separation step has been completed.
As shown in the figure, the plurality of semiconductor devices maintain the state of being bonded to the tape member 33 at the time when the separation step is completed. Therefore, the handling of the semiconductor device after the completion of the separation step can be facilitated. Further, by winding and shipping the tape member 33 in the state shown in FIG. 21, it becomes possible to automatically load the semiconductor device onto the mounting board at the time of mounting, similarly to the case of the chip component.

【００５９】上記してきた製造方法により半導体装置を
製造することにより、従来必要とされたリードの切断処
理、及びリードを所定形状（例えばガルウィング形状）
に成形する工程は不要となり、半導体装置の製造工程を
簡単化することができる。また、図２２は分離工程の変
形例を示している。前述した実施例においては、樹脂パ
ッケージ１４をリードフレーム２０から分離するのにす
る方法を用いたが、本変形例では、リードフレーム２０
を溶解することなく、樹脂パッケージ１４をリードフレ
ーム２０から引き剥がすことにより、機械的に樹脂パッ
ケージ１４をリードフレーム２０から分離することを特
徴としている。By manufacturing the semiconductor device by the above-described manufacturing method, the lead cutting process and the lead required in the related art can be formed into a predetermined shape (for example, a gull wing shape).
This eliminates the need for a step of forming the semiconductor device, thereby simplifying the manufacturing process of the semiconductor device. FIG. 22 shows a modification of the separation step. In the above-described embodiment, the method of separating the resin package 14 from the lead frame 20 is used.
The resin package 14 is peeled off from the lead frame 20 without dissolving the resin package 14, thereby mechanically separating the resin package 14 from the lead frame 20.

【００６０】この分離方法では、前記した実施例に係る
方法に比べて、エッチング液が不要となりまた分離工程
に要する時間を短縮することができる。しかるに、機械
的に樹脂パッケージ１４をリードフレーム２０から分離
するため、金属膜１５Ｃがリードフレーム２０から確実
に樹脂パッケージ１４に移動するかどうかに問題点があ
るが、この点はリードフレーム２０の製造工程の金属膜
形成工程において、予め金属膜形成箇所に金属膜１５Ｃ
の分離性を向上させる部材を予め配設した上で金属膜１
５Ｃを形成することにより解決することができる。In this separation method, an etching solution is not required and the time required for the separation step can be reduced as compared with the method according to the above-described embodiment. However, since the resin package 14 is mechanically separated from the lead frame 20, there is a problem in whether the metal film 15 </ b> C surely moves from the lead frame 20 to the resin package 14. In the metal film forming step of the step, the metal film 15C is
After the member for improving the separability of the metal film 1
The problem can be solved by forming 5C.

【００６１】以上第１実施形態の半導体装置の製造方法
について説明したが、以下に説明する各実施形態におい
ても、主要部は同様な製造方法によって製造することが
できる。 〔第２実施形態〕図２３（ａ），（ｂ）は本発明の第２
実施形態を示す図である。The method of manufacturing the semiconductor device according to the first embodiment has been described above. In each of the embodiments described below, a main part can be manufactured by the same manufacturing method. [Second Embodiment] FIGS. 23A and 23B show a second embodiment of the present invention.
It is a figure showing an embodiment.

【００６２】第１実施形態との違いは、金属膜１５が図
２３（ａ）に示されるように樹脂突起１８上に設けられ
ている点と、樹脂パッケージ１４の底面に絶縁膜１７が
形成されている点、及び図２３（ａ）の底面図である図
２３（ｂ）に示されるように金属膜１５がチップ１１側
に１５１で示されるように引き回されている点であり、
その他の点は前述の実施例とほぼ同様である。The difference from the first embodiment is that the metal film 15 is provided on the resin protrusion 18 as shown in FIG. 23A, and the insulating film 17 is formed on the bottom of the resin package 14. 23 (b), which is a bottom view of FIG. 23 (a), and the metal film 15 is routed to the chip 11 side as indicated by 151,
Other points are almost the same as those of the above-described embodiment.

【００６３】樹脂突起１８を設けることにより、金属膜
１５が樹脂パッケージ１４の底面と同一平面でなくな
り、パッケージの反りを吸収できるとともに、実装時に
半田が流れて隣の金属膜と接触する半田ブリッジも防止
できる。また、金属膜１５を１５１で示されるようにチ
ップ側に引き回すことにより、樹脂突起に形成される金
属膜１５のピッチを広げることができる。この効果は特
に樹脂突起１５をパッケージ底面全体に形成するエリア
バンプ方式に特に有効であり、ピッチの狭い凹部にワイ
ヤを打つことなく狭いピッチのエリアバンプを形成する
ことができる。さらに、絶縁膜１７を形成することに
り、実装時に半田接合される領域を制限でき、引き回し
パターンの酸化等に起因する特性の劣化を防止でき、半
田ブリッジも防止することができる。By providing the resin projections 18, the metal film 15 is no longer flush with the bottom surface of the resin package 14, so that the warpage of the package can be absorbed, and the solder bridge that flows and contacts the adjacent metal film during mounting. Can be prevented. In addition, by laying the metal film 15 toward the chip as indicated by 151, the pitch of the metal film 15 formed on the resin protrusion can be increased. This effect is particularly effective in the area bump method in which the resin protrusion 15 is formed on the entire bottom surface of the package, and an area bump having a narrow pitch can be formed without hitting a wire in a recess having a narrow pitch. Further, by forming the insulating film 17, it is possible to limit a region to be soldered at the time of mounting, prevent deterioration of characteristics due to oxidation of a wiring pattern and the like, and also prevent a solder bridge.

【００６４】本実施例の製造方法は、基本的には第１実
施形態のものと変わりはないが、図８の工程において樹
脂突起を形成する領域のレジストに窓開けし、リードフ
レームにハーフエッチングを施し、凹部を形成した後、
この凹部に金属膜を形成しそこにワイヤボンディングを
施せばよい。ワイヤは、前述した金属膜１５の引き回さ
れた１５１の部分とチップの電極パッド１２とを結ぶよ
うに打てばよい。絶縁膜１７を形成する時は、凹部を形
成する最に絶縁膜をマスクとして凹部を窓開けし、その
後凹部に金属膜を形成した後、引き回し部を形成する領
域を画定するようにレジストを形成し、このレジストを
マスクにして引き回し部をメッキ等により形成すること
により、所望の領域に絶縁膜を形成することができる。
その後のワイヤボンディング工程以降は前述のものと同
様である。 〔第３実施形態〕図２４は本発明の第３実施形態を説明
する図であり、放熱部材４０を図２３で示される半導体
装置に埋め込んだものであり、アルミニウム等の熱導電
率の高い材料で形成されている。絶縁膜１７は放熱の妨
げになるので削除してもよい。その他の構成要件は前述
の実施例とほぼ同様である。Although the manufacturing method of this embodiment is basically the same as that of the first embodiment, a window is formed in a resist in a region where a resin projection is to be formed in the step of FIG. After forming the recess,
A metal film may be formed in the recess and wire bonding may be performed there. The wire may be struck so as to connect the routed portion 151 of the metal film 15 and the electrode pad 12 of the chip. When the insulating film 17 is formed, a window is opened using the insulating film as a mask at the time of forming the concave portion, then a metal film is formed in the concave portion, and then a resist is formed so as to define a region where a wiring portion is formed. Then, by using the resist as a mask to form the routing portion by plating or the like, an insulating film can be formed in a desired region.
The subsequent steps are the same as those described above. [Third Embodiment] FIG. 24 is a view for explaining a third embodiment of the present invention, in which a heat radiating member 40 is embedded in the semiconductor device shown in FIG. 23, and a material having high thermal conductivity such as aluminum is used. It is formed with. The insulating film 17 may be omitted because it hinders heat radiation. Other components are almost the same as those of the above-described embodiment.

【００６５】放熱部材４０のを埋め込むには、チップ１
１をリードフレームにダイス付けする前に、その領域に
予め放熱部材を接着しておき、その上にチップをダイス
付けすることにより埋め込むことができる。この構成に
より、消費電力大きいチップを搭載した際に、チップか
ら発生した熱を良好に放熱することができる。 〔第４実施形態〕図２５は第４実施形態を示す図であ
り、図２３の金属膜１５の引回し部分１５１を用いず
に、樹脂突起１８に金属膜１５と接続するバンプ４１を
設けた点が前述の実施例とは異なる点である。その他の
構成要件はほぼ同様である。To embed the heat radiating member 40, the chip 1
Before the die 1 is mounted on the lead frame, a heat dissipation member may be bonded in advance to the area, and the chip may be embedded by dicing the chip. With this configuration, when a chip with large power consumption is mounted, heat generated from the chip can be radiated well. [Fourth Embodiment] FIG. 25 is a view showing a fourth embodiment, in which a bump 41 connected to the metal film 15 is provided on the resin projection 18 without using the routing portion 151 of the metal film 15 in FIG. This is different from the above-described embodiment. Other components are almost the same.

【００６６】本実施例では、それほど樹脂突起のピッチ
が狭くない時に用いる場合に有効であり、バンプ４１を
介してワイヤ１３を金属膜１５に接続することにより、
強固にワイヤ１３を金属膜１５に接続することができ
る。なお、図２５には絶縁膜放熱部材が示されていない
が、適宜設けても構わない。 〔第５実施形態〕図２６〜図３２は本発明の第５実施形
態を示すものであり、前述した実施例がチップの電極と
金属膜とをワイヤで接続していたのに対し、本実施例の
各図は、ワイヤを用いずにバンプにより接続している点
が共通した相違点である。This embodiment is effective when used when the pitch of the resin projections is not so narrow. By connecting the wire 13 to the metal film 15 via the bump 41,
The wire 13 can be firmly connected to the metal film 15. Although the insulating film heat radiation member is not shown in FIG. 25, it may be provided as appropriate. [Fifth Embodiment] FIGS. 26 to 32 show a fifth embodiment of the present invention. In contrast to the above-described embodiment in which the electrode of the chip and the metal film are connected by wires, the present embodiment Each drawing of the example is a common difference in that connection is made by using bumps without using wires.

【００６７】図２６では、図１に示された半導体装置の
電極パッド１２と金属膜１５との接続をワイヤではなく
バンプを用いた点が特徴であり、その他の点はほぼ同様
である。バンプを用いることにより、より薄型のパッケ
ージを実現でき、またワイヤボンディングの時間よりフ
リップチップボンディングの方が早いので、工程の短縮
もできる。FIG. 26 is characterized in that the connection between electrode pad 12 and metal film 15 of the semiconductor device shown in FIG. 1 is made by using a bump instead of a wire, and the other points are almost the same. By using bumps, a thinner package can be realized, and the process can be shortened because flip-chip bonding is faster than wire bonding time.

【００６８】図２６に示される半導体装置の製造方法
は、第１実施形態の製造方法と基本的には同一である
が、チップ１１をリードフレーム２０に搭載する際に、
ダイス付け材１６を用いずに、バンプ４２により金属膜
１５の形成されたリードフレームに直接フリップチップ
ボンディングすればよい。バンプ４２は、チップ側のパ
ッドに形成してもリードフレーム側に形成してもよい。
その他の工程は、前述の実施例と同様である。The manufacturing method of the semiconductor device shown in FIG. 26 is basically the same as the manufacturing method of the first embodiment, but when mounting the chip 11 on the lead frame 20,
Instead of using the dicing material 16, flip-chip bonding may be directly performed on the lead frame on which the metal film 15 is formed by the bumps. The bumps 42 may be formed on pads on the chip side or on the lead frame side.
Other steps are the same as in the above-described embodiment.

【００６９】図２７（ａ）は、図２３に示される半導体
装置におけるワイヤ接続をバンプ接続にしたものであ
り、金属膜１５の引き出し回し部分１５１にフリップチ
ップボンディングを施したものであり、その他の点は同
様な構成である。金属膜を導電部により引き回すことに
より、樹脂突起に形成される金属膜のピッチを広げるこ
とができる。FIG. 27A shows the semiconductor device shown in FIG. 23 in which the wire connection is changed to a bump connection, and the lead-out portion 151 of the metal film 15 is subjected to flip chip bonding. The point is a similar configuration. The pitch of the metal film formed on the resin protrusion can be increased by drawing the metal film through the conductive portion.

【００７０】図２７（ｂ）は、金属膜１５の引回し部分
１５１に凹部を形成し、そこにバンプ４２を凹部に嵌合
するようにフリップチップボンディングしたものであ
り、その他は図２７（ａ）と同様な構成である。バンプ
４２を凹部４３に嵌合させてボンディングするので、位
置合わせが容易となる。なお、図２７（ａ），（ｂ）の
絶縁膜１７を設けない構成としてもよい。FIG. 27B shows a case where a concave portion is formed in the leading portion 151 of the metal film 15 and a bump 42 is flip-chip bonded to fit the concave portion into the concave portion. ). Since the bumps 42 are fitted into the recesses 43 and bonded, the alignment is facilitated. Note that a configuration in which the insulating film 17 in FIGS. 27A and 27B is not provided may be employed.

【００７１】図２８は、バンプ４２を樹脂突起１８部分
の金属膜１５にボンディングしたものであり、樹脂突起
１８の高さはバンプ４２より低くなっている。この構成
により、バンプ４２をリードフレームに搭載する最、リ
ードフレームの凹部に嵌合させるので、位置合わせを容
易にすることができる。図２９は、図２８で示される半
導体装置のチップ背面に樹脂を設けずに、チップ背面を
露出させたものである。この構成により、チップ背面が
露出しているので、チップから発生した熱を外部に放熱
しやすくなる。FIG. 28 shows a state in which the bump 42 is bonded to the metal film 15 at the resin protrusion 18. The height of the resin protrusion 18 is lower than that of the bump 42. With this configuration, since the bumps 42 are fitted into the recesses of the lead frame when the bumps are mounted on the lead frame, alignment can be facilitated. FIG. 29 shows the semiconductor device shown in FIG. 28 in which the chip back surface is exposed without providing resin on the chip back surface. With this configuration, since the rear surface of the chip is exposed, heat generated from the chip can be easily radiated to the outside.

【００７２】図３０は、図２９に示される半導体装置に
おいて、露出したチップ背面に放熱板を設けたものを示
しており、（ａ）は放熱板４５が設けられたもの、
（ｂ）は放熱フィン４６の付いた放熱板４５が設けられ
たものを示している。放熱フィン付きの（ｂ）の方が放
熱効率が高いので、チップの発熱量に応じた放熱板を設
ければよい。FIG. 30 shows the semiconductor device shown in FIG. 29 in which a heat radiating plate is provided on the exposed chip rear surface. FIG.
(B) shows a case where a heat radiating plate 45 provided with a heat radiating fin 46 is provided. Since the heat radiation efficiency is higher in the case (b) with the heat radiation fins, it is sufficient to provide a heat radiation plate according to the heat value of the chip.

【００７３】図３１は、図２８に示される半導体装置に
おいて、チップの素子形成面側にテープや接着剤等から
なる絶縁部材４７を設けたものであり、樹脂パッケージ
１４の底面と絶縁膜部材４７とはほぼ同一平面となって
いる。図２８の半導体装置をモールドにて形成する際
に、チップ１１とリードフレーム２０との間は極めて隙
間が小さいので、モールド樹脂がこの間に入り込み難い
問題が生じることがある。そこで図３１のように、予め
チップ１１の素子形成面に絶縁部材４７を形成しておけ
ばこの問題はなくなり、封止の不良といった不都合はな
くなる。なお、この絶縁部材４７は予めチップ側に設け
ておいてからリードフレーム２０にフリップチップボン
ディングしても、リードフレーム２０側に設けておいて
からフリップチップボンディングしてもよい。FIG. 31 shows the semiconductor device shown in FIG. 28 in which an insulating member 47 made of a tape, an adhesive or the like is provided on the element forming surface side of the chip. Are almost the same plane. When the semiconductor device of FIG. 28 is formed by molding, since the gap between the chip 11 and the lead frame 20 is extremely small, there may be a problem that the molding resin hardly enters the gap. Therefore, if the insulating member 47 is formed in advance on the element forming surface of the chip 11 as shown in FIG. 31, this problem is eliminated, and the inconvenience such as defective sealing is eliminated. The insulating member 47 may be provided on the chip in advance and then flip-chip bonded to the lead frame 20, or may be provided on the lead frame 20 and then flip-chip bonded.

【００７４】図３２は、図２８に示される半導体装置に
おいて、バンプ４２と金属膜１５とを異方導電樹脂４８
により電気的、機械的に接合したものである。（ａ）に
示されるものは、チップ側の電極パッドにバンプ４２を
設けておき、異方導電樹脂をバンプ４２の上、もしくは
リードフレーム２０の金属膜１５上に形成し、加圧する
ことにより異方導電樹脂中の微小導体がバンプ４２と金
属膜１５との間で連なり、両者の電気的接合が達成され
る。（ｂ）はバンプ４２をリードフレーム２０の金属膜
１５側に設けて形成したものである。（ｃ）は、チップ
側の電極にバンプ４２ａを金属膜側にバンプ４２ｂを設
けておき、異方導電樹脂により接合したものを示してい
る。FIG. 32 is a cross-sectional view of the semiconductor device shown in FIG.
Are electrically and mechanically joined together. In the case shown in (a), bumps 42 are provided on the electrode pads on the chip side, and anisotropic conductive resin is formed on the bumps 42 or on the metal film 15 of the lead frame 20, and the bumps 42 are formed by applying pressure. The minute conductors in the conductive resin are connected between the bumps 42 and the metal film 15, and the electrical connection between the two is achieved. (B) is formed by providing a bump 42 on the metal film 15 side of the lead frame 20. (C) shows a structure in which a bump 42a is provided on an electrode on a chip side and a bump 42b is provided on a metal film side, and the bumps 42a are joined by an anisotropic conductive resin.

【００７５】異方導電樹脂を用いることにより、基板へ
の実装時に隣接するバンプと電気的にショートする可能
性をなくすことができる。By using an anisotropic conductive resin, it is possible to eliminate the possibility of an electrical short-circuit with an adjacent bump during mounting on a substrate.

【００７６】[0076]

【発明の効果】以上のように本発明によれば、実装面積
が小さく、コストの低い樹脂封止型半導体装置とその製
造方法を提供することができる効果を奏する。As described above, according to the present invention, it is possible to provide a resin-encapsulated semiconductor device having a small mounting area and a low cost and a method of manufacturing the same.

【図面の簡単な説明】[Brief description of the drawings]

【図１】第１実施形態の構造を示す図である。FIG. 1 is a diagram showing a structure of a first embodiment.

【図２】第１実施形態の底面透視図である。FIG. 2 is a bottom perspective view of the first embodiment.

【図３】第１実施形態の製造方法を示す図である。FIG. 3 is a diagram illustrating a manufacturing method according to the first embodiment.

【図４】第１実施形態の製造方法を示す図である。FIG. 4 is a diagram illustrating a manufacturing method according to the first embodiment.

【図５】第１実施形態の製造方法を示す図である。FIG. 5 is a diagram illustrating a manufacturing method according to the first embodiment.

【図６】第１実施形態の構造を示す図である。FIG. 6 is a diagram showing the structure of the first embodiment.

【図７】第１実施形態の構造を示す図である。FIG. 7 is a diagram showing the structure of the first embodiment.

【図８】第１実施形態の構造を示す図である。FIG. 8 is a diagram showing the structure of the first embodiment.

【図９】第１実施形態の製造方法を示す図である。FIG. 9 is a diagram illustrating the manufacturing method according to the first embodiment;

【図１０】第１実施形態の製造方法を示す図である。FIG. 10 is a diagram illustrating the manufacturing method according to the first embodiment.

【図１１】第１実施形態の製造方法を示す図である。FIG. 11 is a diagram illustrating the manufacturing method according to the first embodiment;

【図１２】第１実施形態の構造を示す図である。FIG. 12 is a diagram showing the structure of the first embodiment.

【図１３】第１実施形態の構造を示す図である。FIG. 13 is a diagram showing the structure of the first embodiment.

【図１４】第１実施形態の製造方法を示す図である。FIG. 14 is a diagram illustrating the manufacturing method according to the first embodiment;

【図１５】第１実施形態の製造方法を示す図である。FIG. 15 is a diagram illustrating the manufacturing method according to the first embodiment.

【図１６】第１実施形態の製造方法を示す図である。FIG. 16 is a diagram illustrating the manufacturing method according to the first embodiment;

【図１７】第１実施形態の製造方法を示す図である。FIG. 17 is a diagram illustrating the manufacturing method according to the first embodiment;

【図１８】第１実施形態の製造方法を示す図である。FIG. 18 is a diagram illustrating the manufacturing method according to the first embodiment.

【図１９】第１実施形態の製造方法を示す図である。FIG. 19 is a diagram illustrating the manufacturing method according to the first embodiment;

【図２０】第１実施形態の製造方法を示す図である。FIG. 20 is a diagram illustrating the manufacturing method according to the first embodiment;

【図２１】第１実施形態の製造方法を示す図である。FIG. 21 is a diagram illustrating the manufacturing method according to the first embodiment.

【図２２】第１実施形態の製造方法の変形例を示す図で
ある。FIG. 22 is a view showing a modification of the manufacturing method of the first embodiment.

【図２３】第２実施形態の構造及び製造方法を示す図で
ある。FIG. 23 is a view showing the structure and the manufacturing method of the second embodiment.

【図２４】第３実施形態の構造及び製造方法を示す図で
ある。FIG. 24 is a diagram showing a structure and a manufacturing method of the third embodiment.

【図２５】第４実施形態の構造及び製造方法を示す図で
ある。FIG. 25 is a view showing the structure and the manufacturing method of the fourth embodiment.

【図２６】第５実施形態の構造を示す図である。FIG. 26 is a diagram showing the structure of the fifth embodiment.

【図２７】第５実施形態の構造を示す図である。FIG. 27 is a view showing the structure of the fifth embodiment.

【図２８】第５実施形態の構造を示す図である。FIG. 28 is a view showing the structure of the fifth embodiment.

【図２９】第５実施形態の構造を示す図である。FIG. 29 is a diagram showing the structure of the fifth embodiment.

【図３０】第５実施形態の構造を示す図である。FIG. 30 is a diagram showing a structure of a fifth embodiment.

【図３１】第５実施形態の構造を示す図である。FIG. 31 is a diagram showing a structure of a fifth embodiment.

【図３２】第５実施形態の構造を示す図である。FIG. 32 is a view showing the structure of the fifth embodiment.

【図３３】従来例を示す図である。FIG. 33 is a diagram showing a conventional example.

【図３４】従来例を示す図である。FIG. 34 is a diagram showing a conventional example.

【符号の説明】 １・・・樹脂 ２・・・チッ
プ ３・・・アウターリード ４・・・ワイ
ヤ ５・・・ダイステージ ６・・・ハン
ダボール ７・・・搭載基板 ８・・・イン
ナーリード 11・・・チップ 12・・・電極
パッド 13・・・・ボンディングワイヤ 14・・・モー
ルド樹脂 15・・・金属膜 16・・・ダイ
ス付け材 17・・・絶縁膜 18・・・樹脂
突起 21・・・金属基材 23・・・治具
穴 24・・・レジスト 25・・・給電
部 33・・・テープ部材 40・・・放熱
部材 41・・・バンプ 42・・・バン
プ 43・・・凹部 44・・・接着
剤 45・・・放熱板 46・・・放熱
フィン 47・・・絶縁部材[Description of Signs] 1 Resin 2 Chip 3 Outer lead 4 Wire 5 Die stage 6 Solder ball 7 Mounting board 8 Inner lead 11 ... Chip 12 ... Electrode pad 13 ... Bonding wire 14 ... Mold resin 15 ... Metal film 16 ... Die material 17 ... Insulating film 18 ... Resin protrusion 21 ... Metal base material 23 ... Jig hole 24 ... Resist 25 ... Power supply part 33 ... Tape member 40 ... Heat radiation member 41 ... Bump 42 ... Bump 43 ... Recess 44 ・ ・ ・ Adhesive 45 ・ ・ ・ Heat radiation plate 46 ・ ・ ・ Heat radiation fin 47 ・ ・ ・ Insulation member

フロントページの続き (72)発明者 迫田 英治 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 埜本 隆司 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 小野寺 正徳 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 織茂 政一 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 河西 純一 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内Continued on the front page (72) Inventor Eiji Sakota 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Takashi Nomoto 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. Within Fujitsu Limited (72) Inventor Masanori Onodera 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Seiichi Orimo 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Fujitsu Limited (72) Inventor Junichi Kasai 4-1-1 Kamikodanaka Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Fujitsu Limited

Claims (18)

【特許請求の範囲】[Claims] 【請求項１】電極パッドを有する半導体チップと、 該半導体チップを封止する樹脂パッケージと、 該樹脂パッケージの底面から該底面とほぼ同一平面で露
出する金属膜と、 一端が該電極パッドとボンディングされ、他端が該金属
膜とボンディングされたボンディングワイヤとを有する
ことを特徴とする半導体装置。1. A semiconductor chip having an electrode pad, a resin package for encapsulating the semiconductor chip, a metal film exposed from the bottom surface of the resin package on substantially the same plane as the bottom surface, and one end bonded to the electrode pad. And a bonding wire having the other end bonded to the metal film. 【請求項２】電極パッドを有する半導体チップと、 該半導体チップを封止する樹脂パッケージと、 該樹脂パッケージ底面に設けられ、該底面から突出する
樹脂突起と、 該樹脂突起上に設けられた金属膜と、 該樹脂パッケージ底面の該樹脂突起と該チップとの間の
領域に形成され、該金属膜と接続された導電部と、 一端が該電極パッドとボンディングされ、他端が該導電
部とボンディングされたボンディングワイヤとを有する
ことを特徴とする半導体装置。2. A semiconductor chip having electrode pads, a resin package for encapsulating the semiconductor chip, a resin projection provided on a bottom surface of the resin package, protruding from the bottom surface, and a metal provided on the resin projection. A conductive portion formed in a region between the resin protrusion and the chip on the bottom surface of the resin package and connected to the metal film; one end is bonded to the electrode pad; and the other end is connected to the conductive portion. A semiconductor device comprising: a bonded wire that has been bonded. 【請求項３】前記チップと前記樹脂パッケージ底面との
間に放熱部材を設けたことを特徴とする請求項１及び２
記載の半導体装置。3. A heat radiation member is provided between the chip and the bottom surface of the resin package.
13. The semiconductor device according to claim 1. 【請求項４】電極パッドを有する半導体チップと、 該半導体チップを封止する樹脂パッケージと、 該樹脂パッケージ底面に設けられ、該底面から突出する
樹脂突起と、 該樹脂突起上にのみ設けられた金属膜と、 一端が該電極パッドとボンディングされ、他端が該金属
膜にボンディングされたボンディングワイヤとを有する
ことを特徴とする半導体装置。4. A semiconductor chip having electrode pads, a resin package for encapsulating the semiconductor chip, a resin projection provided on a bottom surface of the resin package, protruding from the bottom surface, and provided only on the resin projection. A semiconductor device comprising: a metal film; and a bonding wire having one end bonded to the electrode pad and the other end bonded to the metal film. 【請求項５】電極パッドを有する半導体チップと、 該半導体チップを封止する樹脂パッケージと、 該樹脂パッケージの底面から該底面とほぼ同一平面で露
出する金属膜と、 一端が該電極パッドとボンディングされ、他端が該金属
膜とボンディングされたバンプとを有することを特徴と
する半導体装置。5. A semiconductor chip having an electrode pad, a resin package for encapsulating the semiconductor chip, a metal film exposed from a bottom surface of the resin package on substantially the same plane as the bottom surface, and one end bonded to the electrode pad. Wherein the other end has a bump bonded to the metal film. 【請求項６】電極パッドを有する半導体チップと、 該半導体チップを封止する樹脂パッケージと、 該樹脂パッケージ底面に設けられ、該底面から突出する
樹脂突起と、 該樹脂突起上に設けられた金属膜と、 該樹脂パッケージ底面の該樹脂突起と該チップとの間の
領域に形成され、該金属膜と接続され導電部と、 一端が該電極パッドとボンディングされ、他端が該導電
部とボンディングされたバンプとを有することを特徴と
する半導体装置。6. A semiconductor chip having an electrode pad, a resin package for encapsulating the semiconductor chip, a resin projection provided on a bottom surface of the resin package, protruding from the bottom surface, and a metal provided on the resin projection. A conductive portion formed on the bottom surface of the resin package between the resin protrusion and the chip and connected to the metal film; one end bonded to the electrode pad; and the other end bonded to the conductive portion. A semiconductor device comprising: 【請求項７】前記導電部に凹部が形成され、前記バンプ
が該凹部に嵌合するようにボンディングされていること
を特徴とする請求項６記載の半導体装置。7. The semiconductor device according to claim 6, wherein a recess is formed in said conductive portion, and said bump is bonded so as to fit in said recess. 【請求項８】前記樹脂突起を除く前記樹脂パッケージ底
面に絶縁膜を形成することを特徴とする請求項２，６，
７記載の半導体装置。8. An insulating film is formed on the bottom surface of the resin package except for the resin protrusion.
8. The semiconductor device according to 7. 【請求項９】電極パッドを有する半導体チップと、 該半導体チップを封止する樹脂パッケージと、 該樹脂パッケージ底面に設けられ、該底面から突出する
樹脂突起と、 該樹脂突起上にのみ設けられた金属膜と、 一端が該電極パッドとボンディングされ、他端が該金属
膜にボンディングされたバンプとを有することを特徴と
する半導体装置。9. A semiconductor chip having an electrode pad, a resin package for encapsulating the semiconductor chip, a resin projection provided on the bottom surface of the resin package, protruding from the bottom surface, and provided only on the resin projection. A semiconductor device comprising: a metal film; and a bump having one end bonded to the electrode pad and the other end bonded to the metal film. 【請求項１０】前記チップの非電極パッド形成面を前記
樹脂パッケージから露出させたことを特徴とする請求項
５乃至９記載の半導体装置。10. The semiconductor device according to claim 5, wherein a non-electrode pad forming surface of said chip is exposed from said resin package. 【請求項１１】露出した前記チップの非電極パッド形成
面に放熱板を設けたことを特徴とする請求項１０記載の
半導体装置。11. The semiconductor device according to claim 10, wherein a heat sink is provided on the exposed surface of the chip where the non-electrode pads are formed. 【請求項１２】前記チップの電極パッド形成面上に設け
られ、前記樹脂パッケージ底面とほぼ同一平面となるよ
うに形成された絶縁部材を有することを特徴とする請求
項９記載の半導体装置。12. The semiconductor device according to claim 9, further comprising an insulating member provided on an electrode pad forming surface of said chip and formed substantially flush with a bottom surface of said resin package. 【請求項１３】電極パッドを有する半導体チップと、 該半導体チップを封止する樹脂パッケージと、 該樹脂パッケージ底面に設けられ、該底面から突出する
樹脂突起と、 該樹脂突起上に設けられた金属膜と、 該電極パッドまたは該金属膜に設けられたバンプと、 該バンプと該金属膜との間が異方導電樹脂により導通が
とられていることを特徴とする半導体装置。13. A semiconductor chip having an electrode pad, a resin package for encapsulating the semiconductor chip, a resin protrusion provided on a bottom surface of the resin package, protruding from the bottom surface, and a metal provided on the resin protrusion. A semiconductor device comprising: a film; a bump provided on the electrode pad or the metal film; and an anisotropic conductive resin between the bump and the metal film. 【請求項１４】請求項１乃至１３の金属膜を銀（Ａｇ）
またはパラジウム（Ｐｄ）の一層にて形成する、もしく
はＡｇまたはＰｄの２層にて形成する、もしくは第１層
を最外層とした場合に、第１層−第２層−第３層をＡｕ
−ニッケル（Ｎｉ）−Ａｕ，Ｐｄ−Ｎｉ−Ｐｄ，Ａｕ−
Ｐｄ−Ａｕ，半田−Ｎｉ−Ａｕ，半田−Ｎｉ−Ｐｄの３
層にて形成する、もしくは第１層−第２層−第３層−第
４層を半田−Ｎｉ−Ｐｄ−Ａｕ，Ｐｄ−Ｎｉ−Ｐｄ−Ａ
ｕ，Ａｕ−Ｐｄ−Ｎｉ−Ｐｄ，Ｐｄ−Ｎｉ−Ａｕ−Ｐｄ 半田−Ｎｉ−Ａｕ−Ｐｄの４層にて形成する、もしくは
第１層−第２層−第３層−第４層−第５層をＡｕ−Ｐｄ
−Ｎｉ−Ｐｄ−Ａｕ，半田−Ｎｉ−Ａｕ−Ｐｄ−Ａｕ Ｐｄ−Ｎｉ−Ａｕ−Ｐｄ−Ａｕ，Ａｕ−Ｐｄ−Ｎｉ−Ａ
ｕ−Ｐｄ Ｐｄ−Ｎｉ−ＣｕーＮｉ−Ｐｄの５層にて形成する、も
しくは第１層−第２層−第３層−第４層−第５層−６層
をＡｕ−Ｐｄ−Ｎｉ−Ａｕ−Ｐｄ−Ａｕ Ｐｄ−Ｎｉ−Ｃｕ−Ｎｉ−Ｐｄ−Ａｕの６層にて形成す
ることを特徴とする半導体装置。14. The method according to claim 1, wherein the metal film is silver (Ag).
Alternatively, when the first layer is formed of one layer of palladium (Pd), or is formed of two layers of Ag or Pd, or the first layer is the outermost layer, the first layer, the second layer, and the third layer are formed of Au.
-Nickel (Ni) -Au, Pd-Ni-Pd, Au-
Pd-Au, solder-Ni-Au, solder-Ni-Pd
Or a first layer-second layer-third layer-fourth layer of solder-Ni-Pd-Au, Pd-Ni-Pd-A
u, Au-Pd-Ni-Pd, Pd-Ni-Au-Pd Solder-Ni-Au-Pd, or a first layer-second layer-third layer-fourth layer-fourth layer Five layers of Au-Pd
-Ni-Pd-Au, solder-Ni-Au-Pd-Au Pd-Ni-Au-Pd-Au, Au-Pd-Ni-A
u-Pd Pd-Ni-Cu-Ni-Pd is formed of five layers, or the first layer-second layer-third layer-fourth layer-fifth layer-sixth layer is made of Au-Pd-Ni- A semiconductor device formed of six layers of Au-Pd-AuPd-Ni-Cu-Ni-Pd-Au. 【請求項１５】リードフレームの所定位置に金属膜を形
成する工程と、 該リードフレームの所定の位置に半導体チップを搭載す
る工程と、 該半導体チップの電極パッドと該金属膜とをワイヤまた
はバンプによりボンディングする工程と、 該リードフレーム面がパッケージの底面となるように該
半導体チップを樹脂モールドする工程と、 該リードフレームを除去する工程とを有することを特徴
とする半導体装置の製造方法。15. A step of forming a metal film at a predetermined position of a lead frame, a step of mounting a semiconductor chip at a predetermined position of the lead frame, and connecting wires or bumps of the electrode pads of the semiconductor chip and the metal film. A semiconductor device manufacturing method, comprising the steps of: bonding the semiconductor chip with a resin so that the lead frame surface becomes the bottom surface of the package; and removing the lead frame. 【請求項１６】前記金属膜がメッキにより形成されるこ
とを特徴とする請求項１５記載の半導体装置の製造方
法。16. The method according to claim 15, wherein said metal film is formed by plating. 【請求項１７】電極パッドを有する電子素子チップと、 該チップを封止する封止樹脂と、 該封止樹脂の底面から該底面とほぼ同一平面で露出する
金属膜と、 一端が該電極パッドとボンディングされ、他端が該金属
膜とボンディングされたボンディングワイヤとを有する
ことを特徴とする樹脂パッケージ。17. An electronic element chip having an electrode pad, a sealing resin for sealing the chip, a metal film exposed from a bottom surface of the sealing resin on substantially the same plane as the bottom surface, and one end of the electrode pad. And a bonding wire having the other end bonded to the metal film. 【請求項１８】電極パッドを有する電子素子チップと、 該チップを封止する封止樹脂と、 該封止樹脂の底面に設けられ、該底面から突出する樹脂
突起と、 該樹脂突起上に設けられた金属膜と、 該封止樹脂の底面の該樹脂突起と該チップとの間の領域
に形成され、該金属膜と接続された導電部と、 一端が該電極パッドとボンディングされ、他端が該導電
部とボンディングされたボンディングワイヤとを有する
ことを特徴とする樹脂パッケージ。18. An electronic element chip having an electrode pad, a sealing resin for sealing the chip, a resin projection provided on a bottom surface of the sealing resin and projecting from the bottom surface, and provided on the resin projection. A conductive portion formed in a region between the resin protrusion and the chip on the bottom surface of the sealing resin and connected to the metal film; one end is bonded to the electrode pad; Has a bonding wire bonded to the conductive portion.
JP26760796A 1995-11-08 1996-10-08 Semiconductor device and manufacturing method thereof Expired - Lifetime JP3189703B2 (en)

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Application Number Priority Date Filing Date Title
JP26760796A JP3189703B2 (en) 1996-10-08 1996-10-08 Semiconductor device and manufacturing method thereof
US08/744,048 US6072239A (en) 1995-11-08 1996-11-06 Device having resin package with projections
EP20020016355 EP1261026A1 (en) 1995-11-08 1996-11-07 Device having resin package and method of producing the same
EP20020016357 EP1291911A1 (en) 1995-11-08 1996-11-07 Method having resin package and method of producing the same
TW085113625A TW348306B (en) 1995-11-08 1996-11-07 Device having resin package and method of producing the same
EP20020016354 EP1284501A1 (en) 1995-11-08 1996-11-07 Device having resin package and method of producing the same
EP20020016356 EP1284502A1 (en) 1995-11-08 1996-11-07 Device having resin package and method of producing the same
EP19960308093 EP0773584B1 (en) 1995-11-08 1996-11-07 Device having resin package and method of producing the same
KR1019960052529A KR100212403B1 (en) 1995-11-08 1996-11-07 Device having resin package and method of producing the same
CNB96114520XA CN1215537C (en) 1995-11-08 1996-11-08 Elements with resin shell capsulation and making method
CNB2004100476353A CN1307698C (en) 1995-11-08 1996-11-08 Device having resin package and method of producing the same
US09/192,445 US6159770A (en) 1995-11-08 1998-11-16 Method and apparatus for fabricating semiconductor device
US09/192,201 US6376921B1 (en) 1995-11-08 1998-11-16 Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame
US09/200,846 US6329711B1 (en) 1995-11-08 1998-11-30 Semiconductor device and mounting structure
US09/442,038 US6856017B2 (en) 1995-11-08 1999-11-17 Device having resin package and method of producing the same
US09/809,105 US6573121B2 (en) 1995-11-08 2001-03-16 Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame
US10/856,777 US7144754B2 (en) 1995-11-08 2004-06-01 Device having resin package and method of producing the same

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