JP4627480B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP4627480B2
JP4627480B2 JP2005309437A JP2005309437A JP4627480B2 JP 4627480 B2 JP4627480 B2 JP 4627480B2 JP 2005309437 A JP2005309437 A JP 2005309437A JP 2005309437 A JP2005309437 A JP 2005309437A JP 4627480 B2 JP4627480 B2 JP 4627480B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
wiring pattern
resin
pad
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005309437A
Other languages
Japanese (ja)
Other versions
JP2007123310A (en
Inventor
俊二 松浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aoi Electronics Co Ltd
Original Assignee
Aoi Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aoi Electronics Co Ltd filed Critical Aoi Electronics Co Ltd
Priority to JP2005309437A priority Critical patent/JP4627480B2/en
Publication of JP2007123310A publication Critical patent/JP2007123310A/en
Application granted granted Critical
Publication of JP4627480B2 publication Critical patent/JP4627480B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

本発明は、半導体チップを実装する回路部材、該回路部材に半導体チップを実装した半導体装置及び該半導体装置の製造方法に関する。   The present invention relates to a circuit member for mounting a semiconductor chip, a semiconductor device having a semiconductor chip mounted on the circuit member, and a method for manufacturing the semiconductor device.

小型で薄型の半導体装置の製造方法として、ステンレス鋼板等の導電性基板にメッキにより外部接続用ランド、半導体チップを電気的に接続する半導体チップ接続用パッドを備えた配線パターンを形成した回路部材の前記半導体チップ接続用パッドと半導体チップのバンプ（例えば、半導体チップの電極部分にスタッドワイヤボンディングで形成された金バンプ）とを電気的に接続し、前記半導体チップを樹脂封止した後、前記導電性基板を剥離して前記樹脂面に前記配線パターンを転写してなる半導体装置の製造方法が知られている。（前記記載事項において、転写により配線パターンを形成した回路部材に係る先行技術について特許文献１、特許文献２、特許文献３参照）   As a manufacturing method of a small and thin semiconductor device, a circuit member in which a wiring pattern including a semiconductor chip connection pad for electrically connecting a semiconductor chip to an external connection land and a semiconductor chip is formed on a conductive substrate such as a stainless steel plate by plating. The semiconductor chip connection pad and a bump of the semiconductor chip (for example, a gold bump formed by stud wire bonding on an electrode portion of the semiconductor chip) are electrically connected, and after the semiconductor chip is sealed with resin, the conductive A method for manufacturing a semiconductor device is known in which a conductive substrate is peeled off and the wiring pattern is transferred onto the resin surface. (Refer to Patent Document 1, Patent Document 2, and Patent Document 3 regarding the prior art relating to the circuit member in which the wiring pattern is formed by transfer in the above description.)

特開平９−２６６２６７号公報JP-A-9-266267 特開平１０−５０８８５号公報Japanese Patent Laid-Open No. 10-50885 特開平１０−１１６９３５号公報Japanese Patent Laid-Open No. 10-116935

以下、前記回路部材に半導体チップを実装する半導体装置の製造方法の一例を図３及び図４を参照しながら説明する。
図３に示す例では半導体チップ４を２個示しているが、実際は半導体チップ４が前記回路部材３上にマトリクス状に配列されて半導体装置が製造される。
ここで、図３は要部断面図を、図４は図３の符号Ｂで示す部分の拡大斜視図をそれぞれ示している。 Hereinafter, an example of a method for manufacturing a semiconductor device in which a semiconductor chip is mounted on the circuit member will be described with reference to FIGS.
In the example shown in FIG. 3, two semiconductor chips 4 are shown, but actually, the semiconductor chip 4 is arranged in a matrix on the circuit member 3 to manufacture a semiconductor device.
Here, FIG. 3 shows a cross-sectional view of the main part, and FIG. 4 shows an enlarged perspective view of a portion indicated by reference numeral B in FIG.

図３及び図４に示ように、ステンレス鋼板などの導電性基板１の配線パターン形成面１ａにメッキにより配線パターン２を形成して回路部材３を作製する。
前記導電性基板１に配線パターン２を形成する方法として、前記導電性基板１の配線パターン形成面１ａにレジストをコートし、該レジストに前記配線パターンのマスクで覆い、露光・現像を行う。残されたレジストをマスクとして前記導電性基板１の配線パターン形成面１ａにニッケル・クロームをメッキし、さらに必要に応じて金メッキを施す。前記メッキ処理の後、前記レジストを除去して前記導電性基板１の配線パターン形成面１ａに目的の配線パターン２を形成する。 As shown in FIGS. 3 and 4, the circuit member 3 is manufactured by forming the wiring pattern 2 on the wiring pattern forming surface 1a of the conductive substrate 1 such as a stainless steel plate by plating.
As a method of forming the wiring pattern 2 on the conductive substrate 1, a resist is coated on the wiring pattern forming surface 1a of the conductive substrate 1, and the resist is covered with a mask of the wiring pattern, and exposure and development are performed. Using the remaining resist as a mask, nickel / chrome is plated on the wiring pattern forming surface 1a of the conductive substrate 1 and, if necessary, gold plating is applied. After the plating process, the resist is removed, and a target wiring pattern 2 is formed on the wiring pattern forming surface 1 a of the conductive substrate 1.

配線パターンの一例として図４に示すように、配線パターン２は半導体チップ４が電気的に接続される半導体チップ接続用パッド２ａと該パッド２ａに連なり裏側（導電性基板側）が外部回路（プリント配線板など）との接続面となる外部接続用ランド２ｂから形成されている。
このように形成された前記配線パターン２の前記パッド２ａと半導体チップ４のバンプ４ａとを超音波フリップチップボンディング法で電気的に接続し、半導体チップ４を前記回路部材３に実装する。 As an example of the wiring pattern, as shown in FIG. 4, the wiring pattern 2 includes a semiconductor chip connection pad 2a to which the semiconductor chip 4 is electrically connected, and the back side (conductive substrate side) connected to the pad 2a. It is formed from an external connection land 2b which becomes a connection surface with a wiring board or the like.
The pads 2a of the wiring pattern 2 thus formed and the bumps 4a of the semiconductor chip 4 are electrically connected by an ultrasonic flip chip bonding method, and the semiconductor chip 4 is mounted on the circuit member 3.

しかる後、前記回路部材３を上金型と下金型（図示せず）に挟んでトランスファーモールド法等で前記配線パターン２及び半導体チップ４を含めて片側全面を一括して樹脂５で封止し（図３）、前記半導体チップ４、前記配線パターン２、樹脂５及び回路部材３が一体の樹脂成形品を作製する。   Thereafter, the circuit member 3 is sandwiched between an upper mold and a lower mold (not shown), and the entire surface of one side including the wiring pattern 2 and the semiconductor chip 4 is sealed with a resin 5 by a transfer molding method or the like. (FIG. 3), a resin molded product in which the semiconductor chip 4, the wiring pattern 2, the resin 5 and the circuit member 3 are integrated is produced.

ここで、前記樹脂５で封止される個所は、前記導電性基板１の前記配線パターン２側において、前記半導体チップ４の周面全体、前記配線パターン２、導電性基板１の配線パターン形成面１ａと前記半導体チップ４との間、前記配線パターン２と前記半導体チップ４との間に樹脂５が充填されるが、本発明の課題である樹脂封止した際の問題点について後述する。   Here, the portions sealed with the resin 5 are the entire peripheral surface of the semiconductor chip 4, the wiring pattern 2, and the wiring pattern forming surface of the conductive substrate 1 on the wiring pattern 2 side of the conductive substrate 1. Resin 5 is filled between 1a and the semiconductor chip 4 and between the wiring pattern 2 and the semiconductor chip 4. The problem when the resin is sealed, which is an object of the present invention, will be described later.

次に、前記回路部材３の配線パターン２を前記樹脂５で封止した成型品から前記導電性基板１を剥離すると、前記導電性基板１に形成された前記配線パターン２が前記樹脂５の底面と同一面となるように前記樹脂５に転写される。この後、前記半導体チップ４間の前記樹脂５を格子状に切断部６で切断することで各半導体装置が作製される。   Next, when the conductive substrate 1 is peeled off from the molded product in which the wiring pattern 2 of the circuit member 3 is sealed with the resin 5, the wiring pattern 2 formed on the conductive substrate 1 becomes the bottom surface of the resin 5. Is transferred to the resin 5 so as to be on the same plane. Thereafter, each of the semiconductor devices is manufactured by cutting the resin 5 between the semiconductor chips 4 in a lattice shape with the cutting portions 6.

超音波フリップチップボンディング法により半導体チップ４のバンプ４ａと前記半導体チップ接続ランド２ａとを電気的に接続する際、前記バンプ４ａの潰れが避けられず、その結果、前記半導体チップ４と前記配線パターン２との間隔は前記バンプ４ａの厚さ２０μｍ程度と非常に狭い状態になる。   When the bumps 4a of the semiconductor chip 4 and the semiconductor chip connection lands 2a are electrically connected by an ultrasonic flip chip bonding method, the bumps 4a cannot be crushed. As a result, the semiconductor chip 4 and the wiring pattern The distance between the bump 2 and the bump 4a is as narrow as about 20 μm.

前記導電性基板１に前記配線パターン２を形成する際、前述のように配線パターン２をメッキ工法で形成するのが一般的である。このとき、配線パターン２をメッキで形成した場合、一例として配線パターン２はその厚さが最大で通常３０μｍ、バンプ４ａの厚さを２０μｍとして樹脂５で封止した結果、図４に示すように、面積が比較的広い前記外部接続用ランド２ｂと半導体チップ４との間において、樹脂未充填領域７（鎖線で囲まれた樹脂が達しない領域）が残る配線パターンが多数発生した。なお、図４では樹脂５は図示していない。
この樹脂未充填領域７の発生により配線パターン２上に空気だまりが多数発生した。その結果、樹脂５への配線パターンの前記転写不良が生じることになる。また、転写不良に到らなくても前記樹脂５と前記配線パターン２との接合面積が小さくなって接合強度の弱い部分が生じることになる。
前記樹脂未充填領域７が発生する要因の一つとして前記樹脂５に結合剤として含まれる無機フィラー（例えば、ガラスの微粒子）の最大粒径が影響することを知見した。 When the wiring pattern 2 is formed on the conductive substrate 1, the wiring pattern 2 is generally formed by a plating method as described above. At this time, when the wiring pattern 2 is formed by plating, as an example, the wiring pattern 2 has a maximum thickness of usually 30 μm and the bump 4a has a thickness of 20 μm and is sealed with the resin 5. As a result, as shown in FIG. A large number of wiring patterns were left between the external connection lands 2b having a relatively large area and the semiconductor chip 4 in which a resin unfilled region 7 (a region surrounded by a chain line and not reaching the resin) remained. In FIG. 4, the resin 5 is not shown.
Due to the generation of the resin unfilled region 7, many air pockets are generated on the wiring pattern 2. As a result, the transfer failure of the wiring pattern to the resin 5 occurs. Even if the transfer failure does not occur, the bonding area between the resin 5 and the wiring pattern 2 is reduced, and a portion having a low bonding strength is generated.
As one of the factors that cause the resin unfilled region 7 to occur, it has been found that the maximum particle size of an inorganic filler (for example, fine particles of glass) contained in the resin 5 as a binder affects.

封止に使用される樹脂の一例としてその特性が、スパイラルフロー（ｃｍ）１７０、ゲル化時間（秒）４５、溶融粘度（Ｐａ・ｓ）６、無機フィラーの最大粒径（μｍ）２４（開口２４μｍのメッシュでふるい落とした無機フィラー）を使用し、トランスファーモールドの成形条件として充填速度２．５ｍｍ／ｓ、充填圧力８．５ＭＰａ、型締め力３９２ＫＮ、金型温度１８０℃で封止を行った。   As an example of resin used for sealing, its characteristics are: spiral flow (cm) 170, gelation time (seconds) 45, melt viscosity (Pa · s) 6, maximum particle size of inorganic filler (μm) 24 (opening Sealing was performed at a filling speed of 2.5 mm / s, a filling pressure of 8.5 MPa, a mold clamping force of 392 KN, and a mold temperature of 180 ° C. using inorganic filler screened off with a 24 μm mesh.

前記配線パターン２全体のメッキ厚が３０μｍ、前記半導体チップ４のバンプ４ａの厚さが２０μｍの場合は、前記配線パターン２と前記半導体チップ４との間に前記特性を有する樹脂が充填されている状態を観察した結果、樹脂が配線パターンと半導体チップ間全体に充填されているものは略１７％であった。
また、配線パターン２全体のメッキ厚を６０μｍとその厚さを大きくしてみたが、この場合、樹脂が全体に充填されているものが約４７％得られたが、製造歩留が良好なものということはできない。
前記樹脂未充填領域７が実際に発生する要因として種々検討した結果、配線パターンと半導体チップ間に充填される樹脂の充填状態は、前記樹脂に含まれる無機フィラーの最大粒径が影響していることが分かった。 When the plating thickness of the entire wiring pattern 2 is 30 μm and the thickness of the bump 4 a of the semiconductor chip 4 is 20 μm, a resin having the above characteristics is filled between the wiring pattern 2 and the semiconductor chip 4. As a result of observing the state, about 17% of the resin is filled between the wiring pattern and the semiconductor chip.
Also, the plating thickness of the entire wiring pattern 2 was increased to 60 μm and the thickness was increased. In this case, about 47% of the resin filled in the whole was obtained, but the manufacturing yield was good. I can't say that.
As a result of various investigations as a factor that the resin unfilled region 7 actually occurs, the filling state of the resin filled between the wiring pattern and the semiconductor chip is influenced by the maximum particle size of the inorganic filler contained in the resin. I understood that.

本発明は、前記樹脂未充填領域を減らし、半導体装置の製造歩留を向上することができる回路部材、該回路部材を利用した半導体装置び半導体装置の製造方法を提供する点にある。   An object of the present invention is to provide a circuit member capable of reducing the resin unfilled region and improving the manufacturing yield of the semiconductor device, and a method of manufacturing a semiconductor device and a semiconductor device using the circuit member.

本発明の半導体装置用回路部材は、導電性基板と、該導電性基板上に、バンプを有する半導体チップを電気的に接続するパッド及び外部接続用ランドを有する配線パターンをメッキにて形成してなる前記配線パターンの前記パッドを前記半導体チップを封止するための樹脂に含まれるフィラーの最大粒径よりも大きな厚さ分厚く形成してなる。   The circuit member for a semiconductor device of the present invention is formed by plating a conductive substrate, pads for electrically connecting a semiconductor chip having bumps, and a wiring pattern having external connection lands on the conductive substrate. The pad of the wiring pattern is formed to be thicker than the maximum particle diameter of the filler contained in the resin for sealing the semiconductor chip.

本発明の半導体装置は、バンプを有する半導体チップを電気的に接続するパッド及び外部接続用ランドを有する配線パターンの前記パッドを前記半導体チップを封止するための樹脂に含まれるフィラーの最大粒径よりも大きな厚さ分厚く形成してなる半導体装置用の回路部材の前記パッドに、前記バンプを有する半導体チップを電気的に接続して実装し、前記半導体チップの全周面及び配線パターンの半導体チップ側を樹脂で封止してなる。   In the semiconductor device of the present invention, the maximum particle size of the filler contained in the resin for sealing the semiconductor chip is the pad for electrically connecting the semiconductor chip having the bump and the pad of the wiring pattern having the land for external connection. A semiconductor chip having the bump is electrically connected to and mounted on the pad of a circuit member for a semiconductor device formed to be thicker than the semiconductor chip. The side is sealed with resin.

本発明の半導体装置の製造方法は、導電性基板と、該導電性基板上に、バンプを有する半導体チップを電気的に接続するパッド及び外部接続用ランドを有する配線パターンをメッキにて形成してなる半導体装置用の回路部材を用い、
前記配線パターンの前記パッドを前記半導体チップを封止するための樹脂に含まれるフィラーの最大粒径よりも大きな厚さ分厚く形成してなる回路部材に半導体チップを実装し、前記半導体チップの全周面及び及び前記配線パターンの前記半導体側を樹脂封止し、前記樹脂から前記導電性基板を剥離する。 According to a method of manufacturing a semiconductor device of the present invention, a conductive substrate, a wiring pattern having a pad for electrically connecting a semiconductor chip having a bump and a land for external connection are formed on the conductive substrate by plating. Using a circuit member for a semiconductor device
A semiconductor chip is mounted on a circuit member in which the pad of the wiring pattern is formed thicker than the maximum particle size of the filler contained in the resin for sealing the semiconductor chip, and the entire circumference of the semiconductor chip The surface and the semiconductor side of the wiring pattern are resin-sealed, and the conductive substrate is peeled from the resin.

本発明は、前記配線パターンの前記パッドを前記半導体チップを封止するための樹脂に含まれるフィラーの最大粒径よりも大きな厚さ分厚く形成することで、配線パターンと半導体チップの間に充填される樹脂の未充填領域を大幅に低減することができる。   In the present invention, the pad of the wiring pattern is formed between the wiring pattern and the semiconductor chip by forming the pad thicker than the maximum particle diameter of the filler contained in the resin for sealing the semiconductor chip. The resin unfilled region can be greatly reduced.

以下、本発明を図１及び図２を参照しながら説明する。なお、従来例（図３、図４）と同一の構成要素には同一の符号を付している。
図１に示す例では半導体チップ４を２個示しているが、実際は半導体チップ４が後述する回路部材上にマトリクス状に配列されて半導体装置が製造される。ここで図１は要部断面図を、図２は図１の符号Ａで示す部分の拡大斜視図を示している。 Hereinafter, the present invention will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected to the component same as a prior art example (FIG. 3, FIG. 4).
In the example shown in FIG. 1, two semiconductor chips 4 are shown, but actually, the semiconductor device is manufactured by arranging the semiconductor chips 4 in a matrix on a circuit member to be described later. Here, FIG. 1 shows a cross-sectional view of the main part, and FIG. 2 shows an enlarged perspective view of a portion indicated by reference numeral A in FIG.

図１及び図２に示ように、ステンレス鋼板などの導電性基板１の配線パターン形成面１ａにメッキにより配線パターン２を形成して回路部材３ａを作製する。
前記導電性基板１に配線パターン２を形成方法として、ステンレス鋼板等の導電性基板の配線パターン形成面１ａにレジストをコートし、該レジストに配線パターンのマスクで覆い、露光・現像を行う。残されたレジストをマスクとして導電性基板の配線パターン形成面１ａにニッケル・クロームをメッキし、さらに必要に応じて金メッキを施す。前記メッキ処理の後、前記レジストを除去して前記導電性基板１の配線パターン形成面１ａに目的の配線パターン２を形成する。 As shown in FIGS. 1 and 2, a wiring member 2 is formed on a wiring pattern forming surface 1a of a conductive substrate 1 such as a stainless steel plate by plating to produce a circuit member 3a.
As a method for forming the wiring pattern 2 on the conductive substrate 1, a resist is coated on the wiring pattern forming surface 1a of a conductive substrate such as a stainless steel plate, and the resist is covered with a mask of the wiring pattern, and exposure and development are performed. Using the remaining resist as a mask, nickel / chrome is plated on the wiring pattern forming surface 1a of the conductive substrate, and further, gold plating is applied if necessary. After the plating process, the resist is removed, and a target wiring pattern 2 is formed on the wiring pattern forming surface 1 a of the conductive substrate 1.

配線パターンの一例として図２に示すように、配線パターン２ａは半導体チップ４が電気的に接続される半導体チップ接続用パッド２ａと該パッド２ａに連なり裏側（導電性基板側）が外部回路（プリント配線板など）との接続面となる外部接続用ランド２ｂから形成されている。
次に、前記半導体チップ接続用パッド２ａの上面に２段目のメッキ層２ｃを形成し、該メッキ層２ｃを樹脂封止するための樹脂に含まれる無機フィラーの最大粒径よりも大きな厚さにメッキする。このようにパッド部分を２段メッキすることで配線パターン２に厚さが（２ａ＋２ｃ）のパッド２ｄを形成する。
このように形成された前記配線パターン２の前記パッド２ｄのメッキ層２ｃと前記半導体チップ４のバンプ４ａとを超音波フリップチップボンディング法で電気的に接続し、半導体チップ４を前記回路部材３ａに実装する。 As an example of the wiring pattern, as shown in FIG. 2, the wiring pattern 2a includes a semiconductor chip connection pad 2a to which the semiconductor chip 4 is electrically connected, and the back side (conductive substrate side) connected to the pad 2a. It is formed from an external connection land 2b which becomes a connection surface with a wiring board or the like.
Next, a second plating layer 2c is formed on the upper surface of the semiconductor chip connection pad 2a, and the thickness is larger than the maximum particle diameter of the inorganic filler contained in the resin for resin-sealing the plating layer 2c. Plate on. Thus, the pad 2d having a thickness of (2a + 2c) is formed on the wiring pattern 2 by plating the pad portion in two steps.
The plating layer 2c of the pad 2d of the wiring pattern 2 thus formed and the bump 4a of the semiconductor chip 4 are electrically connected by an ultrasonic flip chip bonding method, and the semiconductor chip 4 is connected to the circuit member 3a. Implement.

しかる後、前記回路部材３ａを上金型と下金型（図示せず）に挟んでトランスファーモールド法等で前記配線パターン２及び半導体チップ４を含めて片側全面を一括して樹脂５で封止し（図１）、前記半導体チップ４、前記配線パターン２、樹脂５及び回路部材３ａが一体の樹脂成形品を作製する。   Thereafter, the circuit member 3a is sandwiched between an upper mold and a lower mold (not shown), and the entire surface of one side including the wiring pattern 2 and the semiconductor chip 4 is sealed with a resin 5 by a transfer molding method or the like. 1 (FIG. 1), a resin molded product in which the semiconductor chip 4, the wiring pattern 2, the resin 5 and the circuit member 3a are integrated is produced.

ここで、前記樹脂５で封止される個所は、前記導電性基板１の前記配線パターン２側において、前記半導体チップ４の周面全体、前記配線パターン２、導電性基板１の配線パターン形成面１ａと前記半導体チップ４との間、前記配線パターン２と前記半導体チップ４との間に樹脂５が充填される。   Here, the portions sealed with the resin 5 are the entire peripheral surface of the semiconductor chip 4, the wiring pattern 2, and the wiring pattern forming surface of the conductive substrate 1 on the wiring pattern 2 side of the conductive substrate 1. Resin 5 is filled between 1 a and the semiconductor chip 4 and between the wiring pattern 2 and the semiconductor chip 4.

次に、前記回路部材３ａの配線パターン２を樹脂５で封止した成型品から前記導電性基板１を剥離すると、前記導電性基板１に形成された配線パターン２が樹脂５の底面と同一面となるように樹脂５に転写される。この後、前記半導体チップ４間の樹脂を格子状に切断部６で切断することで各半導体装置が作製される。   Next, when the conductive substrate 1 is peeled off from the molded product in which the wiring pattern 2 of the circuit member 3 a is sealed with the resin 5, the wiring pattern 2 formed on the conductive substrate 1 is flush with the bottom surface of the resin 5. Is transferred to the resin 5 so that Thereafter, each semiconductor device is manufactured by cutting the resin between the semiconductor chips 4 in a lattice shape by the cutting portions 6.

本発明は、前記配線パターン２の前記パッド２ｄの前記メッキ層２ｃ厚さを前記半導体チップ４を封止するための樹脂に含まれるフィラーの最大粒径よりも大きな厚さ分厚く形成することで、配線パターン２と半導体チップ４の間に充填される樹脂の未充填領域を大幅に低減することができた。   In the present invention, the thickness of the plating layer 2c of the pad 2d of the wiring pattern 2 is formed to be thicker than the maximum particle diameter of the filler contained in the resin for sealing the semiconductor chip 4, The unfilled region of the resin filled between the wiring pattern 2 and the semiconductor chip 4 could be greatly reduced.

前記配線パターン２のメッキ厚さ（１段目メッキ厚さ）が３０μｍ、前記半導体チップ接続用パッド２ａの上面に施した２段目メッキ層２ｃの厚さ３０μｍとして新たなパッド２ｄの厚さを６０μｍに形成する。
このように形成された前記配線パターン２の前記パッド２ｄと半導体チップ４のバンプ４ａとを超音波フリップチップボンディング法で電気的に接続し、半導体チップ４を前記回路部材３ａに実装する。 The wiring pattern 2 has a plating thickness (first plating thickness) of 30 μm, and the thickness of the second plating layer 2c applied to the upper surface of the semiconductor chip connection pad 2a is 30 μm. It is formed to 60 μm.
The pads 2d of the wiring pattern 2 thus formed and the bumps 4a of the semiconductor chip 4 are electrically connected by an ultrasonic flip chip bonding method, and the semiconductor chip 4 is mounted on the circuit member 3a.

そして、封止に使用される樹脂の一例としてその特性が、スパイラルフロー（ｃｍ）１７０、ゲル化時間（秒）４５、溶融粘度（Ｐａ・ｓ）６、無機フィラーの最大粒径（μｍ）２４（開口２４μｍのメッシュでふるい落とした無機フィラー）を使用し、トランスファーモールドの成形条件として充填速度２．５ｍｍ／ｓ、充填圧力８．５ＭＰａ、型締め力３９２ＫＮ、金型温度１８０℃で封止を行った。   As an example of the resin used for sealing, the characteristics are as follows: spiral flow (cm) 170, gelation time (seconds) 45, melt viscosity (Pa · s) 6, maximum particle size (μm) of inorganic filler 24 (Inorganic filler screened off with a mesh of 24 μm opening) is used, and the molding is performed at a filling speed of 2.5 mm / s, a filling pressure of 8.5 MPa, a clamping force of 392 KN, and a mold temperature of 180 ° C. It was.

すると、前記配線パターン２と前記半導体チップ４との間に前記特性を有する樹脂が充填されている状態を観察した結果、樹脂５が前記配線パターン２と前記半導体チップ４との間全体に前記樹脂が充填されているものが８０％以上となり、半導体装置の製造歩留をかなり高めることができた。
これは、前記パッド２ｄの厚さを６０μｍとしたことで前記配線パターン２と前記半導体チップ４との間隔が略５０μｍ（メッキ層２ｃとバンプ４ａの厚さ）となるが、これは前記樹脂５に含まれる無機フィラーの最大粒径２４μｍよりも十分に大きくしたことによるものである。
前記実施例では、前記配線パターンの前記パッド２ｄの厚さの調整を２段メッキで行ったが、前記樹脂に含まれる無機フィラーの最大粒径に応じてメッキの回数を増加して実施することもできる。 Then, as a result of observing a state in which the resin having the above characteristics is filled between the wiring pattern 2 and the semiconductor chip 4, the resin 5 is entirely placed between the wiring pattern 2 and the semiconductor chip 4. 80% or more is filled, and the manufacturing yield of the semiconductor device can be considerably increased.
This is because when the thickness of the pad 2d is 60 μm, the distance between the wiring pattern 2 and the semiconductor chip 4 becomes approximately 50 μm (the thickness of the plating layer 2c and the bump 4a). This is because the inorganic filler contained in is sufficiently larger than the maximum particle size of 24 μm.
In the embodiment, the thickness of the pad 2d of the wiring pattern is adjusted by two-step plating, but the number of plating is increased according to the maximum particle size of the inorganic filler contained in the resin. You can also.

本発明の半導体装置を製造する際の工程を説明する断面図である。It is sectional drawing explaining the process at the time of manufacturing the semiconductor device of this invention. 本発明の半導体装置の配線パターンの要部斜視図である。It is a principal part perspective view of the wiring pattern of the semiconductor device of this invention. 従来の半導体装置を製造する際の工程を説明する断面図である。It is sectional drawing explaining the process at the time of manufacturing the conventional semiconductor device. 従来の半導体装置の配線パターンの要部斜視図である。It is a principal part perspective view of the wiring pattern of the conventional semiconductor device.

符号の説明Explanation of symbols

１・・導電性基板 ２・・配線パターン ４・・半導体チップ ５・・樹脂
２ｄ・・配線パターンのパッド 1 .. Conductive substrate 2 .... Wiring pattern 4 .... Semiconductor chip 5 .... Resin 2d ... Wiring pattern pad

Claims (3)

バンプを有する半導体チップを電気的に接続するパッド及び前記パッドに連なる外部接続用ランドをメッキにて形成してなる配線パターンの前記パッドの厚さを前記半導体チップを封止するための樹脂に含まれるフィラーの最大粒径よりも大きな厚さ分前記外部接続用ランドの厚さよりも厚く形成してなる半導体装置用の回路部材の前記パッドに前記バンプを有する半導体チップを電気的に接続するとともに前記半導体チップが前記ランド上に位置するように実装し、前記半導体チップの全周面及び前記配線パターンの前記半導体チップ側を樹脂で封止してなる半導体装置。 A resin for sealing the electrical connection pads and the semiconductor chip thickness of the pad of Ru wiring pattern name form by plating the external connection land connected to the pad of a semiconductor chip having a bump electrically connecting a semiconductor chip having a front Symbol bump to the pad of the circuit member for a semiconductor device obtained by forming thicker than the thickness of the large thickness min the external connection land than the maximum particle size of the filler contained together with the semiconductor chip is mounted so as to be positioned on the land, the entire peripheral surface and the semiconductor chip side semiconductor device obtained by encapsulating in resin of the wiring pattern of the semiconductor chip. 導電性基板と、該導電性基板上に、バンプを有する半導体チップを電気的に接続するパッド及び前記パッドに連なる外部接続用ランドを有する配線パターンをメッキにて形成してなる半導体装置用の回路部材を用いた半導体装置の製造方法であって、
前記配線パターンの前記パッドの厚さを前記半導体チップを封止するための樹脂に含まれるフィラーの最大粒径よりも大きな厚さ分前記外部接続用ランドの厚さよりも厚く形成してなる回路部材に、前記半導体チップが前記ランド上に位置するように実装し、前記半導体チップの全周面及び及び前記配線パターンの前記半導体チップ側を樹脂で封止し、前記樹脂から前記導電性基板を剥離してなる半導体装置の製造方法。 A conductive substrate, a conductive substrate, the circuit for a semiconductor device comprising a wiring pattern having a pad and the external connection land connected to the pad and electrically connected to form by plating a semiconductor chip having a bump A method of manufacturing a semiconductor device using a member,
A circuit member in which the thickness of the pad of the wiring pattern is formed to be larger than the thickness of the external connection land by a thickness larger than the maximum particle diameter of the filler contained in the resin for sealing the semiconductor chip in the semiconductor chip is mounted so as to be positioned on the land, seals the seal the semiconductor chip side in the resin of the entire circumference and and the wiring pattern of the semiconductor chip, peeling off the conductive substrate from the resin A method for manufacturing a semiconductor device. 前記パッドを２段以上のメッキで形成することを特徴とする請求項２の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 2 , wherein the pad is formed by two or more steps of plating.
JP2005309437A 2005-10-25 2005-10-25 Semiconductor device Expired - Fee Related JP4627480B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005309437A JP4627480B2 (en) 2005-10-25 2005-10-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005309437A JP4627480B2 (en) 2005-10-25 2005-10-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2007123310A JP2007123310A (en) 2007-05-17
JP4627480B2 true JP4627480B2 (en) 2011-02-09

Family

ID=38146870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005309437A Expired - Fee Related JP4627480B2 (en) 2005-10-25 2005-10-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4627480B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162238A (en) * 1995-12-08 1997-06-20 Matsushita Electric Ind Co Ltd Terminal electrode on circuit board, formation thereof, circuit board, and semiconductor module
JPH10116935A (en) * 1996-10-08 1998-05-06 Fujitsu Ltd Semiconductor device and its manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162238A (en) * 1995-12-08 1997-06-20 Matsushita Electric Ind Co Ltd Terminal electrode on circuit board, formation thereof, circuit board, and semiconductor module
JPH10116935A (en) * 1996-10-08 1998-05-06 Fujitsu Ltd Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
JP2007123310A (en) 2007-05-17

Similar Documents

Publication Publication Date Title
US6638790B2 (en) Leadframe and method for manufacturing resin-molded semiconductor device
US6291274B1 (en) Resin molded semiconductor device and method for manufacturing the same
TWI397964B (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7141868B2 (en) Flash preventing substrate and method for fabricating the same
TW200425355A (en) Method for maintaining solder thickness in flipchip attach packaging processes
JP4307362B2 (en) Semiconductor device, lead frame, and lead frame manufacturing method
TWI421993B (en) Quad flat no-lead package, method for forming the same, and metal plate for forming the package
JP4627480B2 (en) Semiconductor device
JP4901776B2 (en) Lead frame, semiconductor device using the same, and production method thereof
JP2008147266A (en) Semiconductor device and its manufacturing method
JP2007208153A (en) Semiconductor device, and manufacturing method thereof
JP2007019275A (en) Substrate, semiconductor device, and manufacturing method thereof
JP2010010634A (en) Lead frame, and method of manufacturing semiconductor device
JP3968321B2 (en) Semiconductor device and manufacturing method thereof
JP2017188604A (en) Lead frame and semiconductor device, and manufacturing method of lead frame and semiconductor device
JP2005191158A (en) Semiconductor device and its manufacturing method
JP3976311B2 (en) Lead frame manufacturing method
JP2007134585A (en) Semiconductor device and its manufacturing method
JP4018853B2 (en) Terminal land frame
KR19990055277A (en) Chip scale package
JP4695672B2 (en) Semiconductor device
JP4705614B2 (en) Resin-sealed semiconductor device
JP4840305B2 (en) Manufacturing method of semiconductor device
TWI231590B (en) Window-type semiconductor package and fabrication method thereof
US6717278B2 (en) Semiconductor device having a resist edge positioned over througholes

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080929

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100916

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100922

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101012

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101105

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101105

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131119

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees