JP3976311B2 - Lead frame manufacturing method - Google Patents

Lead frame manufacturing method Download PDF

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Publication number
JP3976311B2
JP3976311B2 JP2002150063A JP2002150063A JP3976311B2 JP 3976311 B2 JP3976311 B2 JP 3976311B2 JP 2002150063 A JP2002150063 A JP 2002150063A JP 2002150063 A JP2002150063 A JP 2002150063A JP 3976311 B2 JP3976311 B2 JP 3976311B2
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insulating resin
lead frame
lead
surface side
main surface
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JP2003347494A (en
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知加雄 池永
誠一郎 吉田
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Dai Nippon Printing Co Ltd
New Japan Radio Co Ltd
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Dai Nippon Printing Co Ltd
New Japan Radio Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

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  • Lead Frames For Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体パッケージを構成するリードフレームの技術分野に属し、詳しくは、半導体素子を搭載して樹脂封止するタイプの樹脂封止型半導体パッケージに用いられるリードフレームの製造方法に関するものである。
【０００２】
【従来の技術】
近年、基板実装の高密度化に伴い、基板に実装される半導体パッケージの小型化・薄型化が要求されている。ＬＳＩも、高集積化によるチップ数の削減とパッケージの小型・軽量化が厳しく要求され、いわゆるＣＳＰ（Chip Size Package)の普及が急速に進んでいる。特に、リードフレームを用いた薄型の半導体パッケージの開発においては、リードフレームに半導体素子を搭載し、その搭載面をモールド樹脂で封止する片面封止タイプの半導体パッケージが開発されている。
【０００３】
図１は従来の半導体パッケージの一つであるＱＦＮ（Quad Flatpack Non-leaded package) の一例を示す断面図、図２はその封止樹脂を透視した状態で示す平面図である。これらの図に示される半導体パッケージは、リードフレーム１の吊りリード２で支持されたダイパッド３に搭載された半導体素子４と、この半導体素子４の上面の電極とリードフレーム１のリード５とを電気的に接続した金属細線６と、半導体素子４の上側とダイパッド３の下側とを含む半導体素子４の外囲領域を封止した封止樹脂７とを備えている。この半導体パッケージは、いわゆるアウターリードが突き出ておらず、インナーリードとアウターリードの両者がリード５として一体となったノンリードタイプである。また、用いられているリードフレーム１は、ダイパッド３がリード５より上方に位置するように、吊りリード２がアップセット処理されている。このようにダイパッド３は段差を有しているので、ダイパッド３の下側にも封止樹脂７を存在させることができる。
【０００４】
上記のようなノンリードタイプの薄型半導体パッケージ（ＱＦＮ）は、半導体素子のサイズが小型であるため、１枚のフレームの幅方向に複数列配列して製造するマトリックスタイプが主流である。そして、最近では、コストダウンの要求から、図３に示すような個別にモールドするタイプから、図４に示すような一括してモールドするタイプへ移行しつつある。
【０００５】
個別モールドタイプは、図３（Ａ）に示すように、１枚のフレームＦ内に小さなサイズの個々のモールドキャビティＣを分かれた状態で設けるようにし、モールド後は金型により個別に打ち抜いて図３（Ｂ）に示す半導体パッケージＳを得るものである。すなわち、半導体素子を銀ペースト等によりリードフレームのダイパッド上に搭載し、ワイヤーボンディングを実施した後、個々の半導体素子を個別にモールドしてから、金型により個々の半導体パッケージとして打ち抜くのである。
【０００６】
一括モールドタイプは、図４（Ａ）に示すように、１枚のフレームＦ内に大きなサイズの幾つかのモールドキャビティＣを設けるようにし、その一つ一つのモールドキャビティＣ内には多数の半導体素子をマトリックス状に配列し、それらの半導体素子を一括してモールドした後、各リードフレームのグリッドリードＬのところをダイシングソーで切断して図４（Ｂ）に示す半導体パッケージＳを得るものである。すなわち、半導体素子を銀ペースト等によりリードフレームのダイパッド上に搭載し、ワイヤーボンディングを実施した後、複数個配列されている半導体素子を所定のキャビティサイズで一括モールドしてから、ダイシングにより個片化するのである。
【０００７】
そして、最近では、通信機器に欠かせない高周波タイプの半導体素子についても上記のような半導体パッケージが採用されており、このように搭載する半導体素子が高集積化したものになると、発熱が問題となることから、ダイパッド露出型の半導体パッケージの開発が盛んとなっている。
【０００８】
また、搭載する半導体素子が高周波タイプになるのに対応して、半導体パッケージの電気特性も厳しい条件が要求されるようになり、現在では半導体素子とリードフレームの接合をワイヤーボンディング方式からフリップチップボンディング方式へ転換する傾向になっている。高周波タイプの半導体素子は、その特性上、材料が硬いＳｉから軟らかい化合物半導体へと移行しつつあるところ、現在はセラミック等の高価な基板にて実装されているが、上記したような安価な半導体パッケージへの変更が検討されている。
【０００９】
【発明が解決しようとする課題】
上記したノンリードタイプの半導体パッケージは、その製造工程での樹脂封止時においてリードに薄バリが発生するのを防止するため、リードフレームの裏面に予めテープを貼り付けておく必要がある。また、半導体パッケージの製造には熱を伴う工程があり、テープには耐熱性が要求される。ところが、この時に使用するテープは価格が高いという問題がある。また、テープからのコンタミネーションによりワイヤーボンディングを阻害すると言う問題点や封止樹脂の密着性が低下する問題点もあった。さらに、テープの貼り剥がしの際の応力が、半導体パッケージ内の層間剥離を発生させたり、剥がしの際の静電気によりチップが静電破壊される問題点もあった。
【００１０】
また、ダイパッド露出型の半導体パッケージでは、樹脂とリードフレームの熱膨張係数の違いから、樹脂とリードフレームの界面から剥離が発生するという問題点がある。
【００１１】
一方、材料に化合物半導体を用いた半導体素子は、その軟らかさから、フリップチップボンディングのような熱圧力のかかる方法を用いると壊れる恐れがあり、また生産性を向上させる観点からも半田接合による一括リフロー接合の要求が高いが、通常のＱＦＮでは半田接合を行うと、リフロー後に溶融した半田がリード間に流れ込み、ひどいときには端子面にまで回り込み、信頼性を阻害するという問題点があった。
【００１２】
本発明は、このような事情に鑑みてなされたものであり、その目的とするところは、樹脂封止前に裏面への高価なテープの貼り付けを省略でき、しかも封止樹脂の剥離を生じることがなく、さらには半田による一括リフローのフリップチップボンディングを可能としたリードフレームの製造方法を提供することにある。
【００１３】
【課題を解決するための手段】
上記の目的を達成するため、本発明のリードフレームの製造方法は、ダイパッドと、リードと、ダイパッドとリードを接続固定する枠部とを有し、半導体素子を搭載する主面側とその反対の裏面側のうちの少なくとも主面側に絶縁性樹脂積層部を配設してなるリードフレームを製造する方法であって、（ａ）リードフレームのパターンが並んだ所定形状の基材を薄板状金属材料より製作する工程と、（ｂ）リードフレームの基材の少なくとも主面側に、所定の開口部を複数有する絶縁性樹脂積層部を形成する工程と、（ｃ）リード側面間の間隙部に絶縁性樹脂を埋め込む工程とを含み、（ｂ）の絶縁性樹脂積層部を形成する工程、及び（ｃ）の絶縁性樹脂を埋め込む工程を、リードフレームの基材の裏面側に漏れ防止用の剥離性部材を設置した後に、リードフレームの基材の全面に液状絶縁性樹脂を塗布することにより、主面側の絶縁性樹脂積層部の形成とリード側面間の間隙部への埋め込みを同時に行い、絶縁性樹脂の乾燥及び剥離性部材の取外し後に、絶縁性樹脂積層部に所定の開口部を設ける手順で行うことを特徴とするか、（ｂ）の絶縁性樹脂積層部を形成する工程、及び（ｃ）の絶縁性樹脂を埋め込む工程を、所定厚さのフィルム状樹脂をリードフレームの基材の主面側に位置合わせした後、リードフレームの基材の主面側及び各リード側面間の間隙部に、熱圧接及び加圧圧入することにより、絶縁性樹脂積層部と埋め込み部を同時形成し、その後に絶縁性樹脂積層部に所定の開口部を設ける手順で行うことを特徴としている。
【００１４】
【発明の実施の形態】
次に、本発明の実施の形態を図面を参照して説明する。
【００１５】
図５は本発明の方法で製造されたリードフレームの一例を示す平面図、図６は図５に示すリードフレームにおけるＡ−Ａ断面とＢ−Ｂ断面の一部拡大図である。
【００１６】
図示のように、リードフレーム１は、周辺部からの４本の吊りリード２でダイパッド３を支持し、そのダイパッド３に向けて周囲４辺からそれぞれ４本ずつリード５が突き出た状態になっており、半導体素子を搭載する主面側に薄い積層部を形成した状態でリード５の側面間に絶縁性樹脂８が埋め込まれている。そして、半導体素子の電極とのワイヤー接続部分となる各リード５の先端付近のところで、絶縁性樹脂８の薄い積層部に開口が形成され、その開口した部位（図のハッチング部分）にワイヤーボンディング用のめっき９が施されている。さらに、半導体素子の搭載場所となるダイパッドのところで、絶縁性樹脂８の薄い積層部に開口部が形成されており、この開口部（図のハッチング部分）には必要に応じてダイボンディング用のめっき１０が施されている。
【００１７】
図５のリードフレーム１において、主面側に配設される絶縁性樹脂積層部の塗布乾燥後の厚さは、少なくとも５〜５０μｍであることが好ましい。また、リードフレーム１の反り改善の観点からすると、半導体素子を搭載する主面側とは反対の裏面側に、さらに所定の開口部を有する絶縁性樹脂積層部を配設することが好ましい。
【００１８】
そして、リードフレーム１の基材は、熱膨張係数の違いによる信頼性向上の観点から、絶縁性樹脂とは相性の悪い銅材を使用することとし、材質が重量９０％以上の銅を主体とした銅合金を用いることが好ましい。
【００１９】
絶縁性樹脂としては、アクリル樹脂及びポリマーアロイ樹脂系のソルダーレジストを使用するのが好適である。このソルダーレジストは弾性率が５×１０-9Ｐａ程度であり、線膨張係数はＴｇ前後においてα1 ＝５７ｐｐｍ／℃、α2 ＝１４１ｐｐｍ／℃である。具体的な製品としては、太陽インキ製造株式会社製「ＰＦＲ−８００ ＡＵＳ４０２」が挙げられる。
【００２０】
図５に示すリードフレーム１を製造するには、まず、薄板状の金属材料からリードフレームの基材を製作する。すなわち、リードフレームのパターンがマトリックス状に複数個並んだ状態の基材を薄板状金属材料から製作する。そして、このリードフレームの基材の少なくとも主面側に、所定の開口部を複数有する絶縁性樹脂積層部を形成する工程と、リード側面間の間隙部に絶縁性樹脂を埋め込む工程とを行う。
【００２１】
具体的には、リードフレームの基材の裏面側に漏れ防止用の剥離性部材を設置した後に、リードフレームの基材の全面に液状絶縁性樹脂を塗布することにより、主面側の絶縁性樹脂積層部の形成とリード側面間の間隙部への埋め込みを同時に行い、絶縁性樹脂の乾燥及び剥離性部材の取外し後に、絶縁性樹脂積層部に所定の開口部を設ける。
【００２２】
或いは、所定厚さのフィルム状樹脂をリードフレームの基材の主面側に位置合わせした後、リードフレームの基材の主面側及び各リード側面間の間隙部に、熱圧接及び加圧圧入することにより、絶縁性樹脂積層部と埋め込み部を同時形成し、その後に絶縁性樹脂積層部に所定の開口部を設ける。
【００２３】
通常、リードフレームの基材は、表裏両面から片面ずつハーフエッチングしてパターニングするので、側面は図６のように尖鋭形状を持つ断面形状になる。そして、この空間に埋め込まれた絶縁性樹脂８は側面がリードフレーム１に食い込んだ状態となる。なお、図６ではリードフレーム１の板厚の全体に渡って絶縁性樹脂８が埋め込まれているが、表面側から少なくとも板厚の１／３程度以上の深さで埋め込まれていればよい。
【００２４】
主面側の絶縁性樹脂８の積層部に設ける開口はフォトリソグラフィー法で形成する。具体的には、所定のマスクを介しての露光とそれに続く現像によりリード５及びダイパッド３の所定位置にて絶縁性樹脂８に開口をパターニングする。そして、その開口により露出した下の金属部分に銀、金、Ｐｄ等のボンディングに必要なめっきを施すのである。
【００２５】
このリードフレーム１を用いて半導体パッケージを製造する手順は次のようである。まず、ダイパッド３の上に銀ペーストにより半導体素子を搭載し、リード５に施しためっき９のところと半導体素子の上面の電極との間にワイヤーボンディングを実施した後、モールド型にセットして個別にモールドしてから、金型により個々の半導体パッケージに打ち抜く。このモールド時において、リード５間に絶縁性樹脂８が埋め込まれているので、従来のようにリードフレームの裏面にテープを貼り付けなくても、封止樹脂が裏側に回り込むことがない。
【００２６】
このようにして製造された半導体パッケージの断面図を図７に示す。この半導体パッケージは、図示のように、リードフレーム１のダイパッド３上に搭載された半導体素子４の電極とリードフレームのリード５に施しためっき９のところとが金属細線６により電気的に接合されており、リードフレーム１のリード５間に絶縁性樹脂８が埋め込まれ、かつリードフレーム１との間に絶縁性樹脂８を挟んだ状態で封止樹脂７が設けられている。そして、絶縁性樹脂８は、封止樹脂７との密着性が良好であるとともに、封止樹脂７より弾性率が低いためにリードフレーム１との熱膨張係数の差による応力が緩和されるので、剥離等の問題がなくなる。
【００２７】
また、ダイパッド上に搭載された半導体素子の電極とリードフレームのリードとの電気的な接合に、ワイヤーボンディングではなく、フリップチップ方式のワイヤレスボンディングを行う場合、リード５の先端付近に形成した開口のところに半導体素子のバンプを位置合わせし、熱による半田リフローにより接着・接続を行う。この時、開口の回りの絶縁性樹脂８が堰の役割を果たすため、半田流れが防止される。
【００２８】
なお、上記の説明では、個別モールドタイプについて述べたが、一括モールドタイプの半導体パッケージについても同様である。
【００２９】
【発明の効果】
本発明は、ダイパッドと、リードと、ダイパッドとリードを接続固定する枠部とを有し、半導体素子を搭載する主面側とその反対の裏面側のうちの少なくとも主面側に絶縁性樹脂積層部を配設してなるリードフレームの製造方法であって、（ａ）リードフレームのパターンが並んだ所定形状の基材を薄板状金属材料より製作する工程と、（ｂ）リードフレームの基材の少なくとも主面側に、所定の開口部を複数有する絶縁性樹脂積層部を形成する工程と、（ｃ）リード側面間の間隙部に絶縁性樹脂を埋め込む工程とを含み、（ｂ）の絶縁性樹脂積層部を形成する工程、及び（ｃ）の絶縁性樹脂を埋め込む工程を、リードフレームの基材の裏面側に漏れ防止用の剥離性部材を設置した後に、リードフレームの基材の全面に液状絶縁性樹脂を塗布することにより、主面側の絶縁性樹脂積層部の形成とリード側面間の間隙部への埋め込みを同時に行い、絶縁性樹脂の乾燥及び剥離性部材の取外し後に、絶縁性樹脂積層部に所定の開口部を設ける手順で行うことを特徴とするか、（ｂ）の絶縁性樹脂積層部を形成する工程、及び（ｃ）の絶縁性樹脂を埋め込む工程を、所定厚さのフィルム状樹脂をリードフレームの基材の主面側に位置合わせした後、リードフレームの基材の主面側及び各リード側面間の間隙部に、熱圧接及び加圧圧入することにより、絶縁性樹脂積層部と埋め込み部を同時形成し、その後に絶縁性樹脂積層部に所定の開口部を設ける手順で行うことを特徴としているので、封止樹脂のモールドに際して裏面への高価なテープの貼付を省略できるため、製造コストの削減を図ることができる。
【００３０】
また、リードフレームの基材と接する絶縁性樹脂は弾性率が低く、熱膨張係数の違いによる応力が緩和されるため、また絶縁性樹脂と封止樹脂は密着性が非常に高いため、剥離の発生しない信頼性の高い半導体パッケージを提供することができる。
【００３１】
また、絶縁性樹脂積層部に開口を形成することにより、半田による一括リフローのフリップチップボンディングが可能となり、高周波タイプの半導体素子に対応したパッケージを安価なＱＦＮの形態で供給することができる。
【図面の簡単な説明】
【図１】 従来の半導体パッケージの一例を示す断面図である。
【図２】 図１に示す半導体パッケージをその封止樹脂を透視した状態で示す平面図である。
【図３】 個別モールドタイプの半導体パッケージを示す説明図である。
【図４】 一括モールドタイプの半導体パッケージを示す説明図である。
【図５】 本発明の方法で製造されたリードフレームの一例を示す平面図である。
【図６】 図５に示すリードフレームにおけるＡ−Ａ断面とＢ−Ｂ断面の一部拡大図である。
【図７】 図５に示すリードフレームを使用して製造された半導体パッケージを示す断面図である。
【符号の説明】
１ リードフレーム
２ 吊りリード
３ ダイパッド
４ 半導体素子
５ リード
６ 金属細線
７ 封止樹脂
８ 絶縁性樹脂
９ めっき
１０ めっき
Ｃ モールドキャビティ
Ｆ フレーム
Ｌ グリッドリード
Ｓ 半導体パッケージ[0001]
BACKGROUND OF THE INVENTION
The present invention belongs to the technical field of a lead frame constituting a semiconductor package, and particularly relates to a method of manufacturing a lead frame used for a resin-encapsulated semiconductor package of a type in which a semiconductor element is mounted and resin-sealed. .
[0002]
[Prior art]
In recent years, with the increase in the density of substrate mounting, there has been a demand for downsizing and thinning of a semiconductor package mounted on a substrate. LSIs are also required to reduce the number of chips due to high integration and to reduce the size and weight of packages, and so-called CSP (Chip Size Package) is rapidly spreading. In particular, in the development of a thin semiconductor package using a lead frame, a single-side sealed type semiconductor package in which a semiconductor element is mounted on a lead frame and its mounting surface is sealed with a mold resin has been developed.
[0003]
FIG. 1 is a cross-sectional view showing an example of a QFN (Quad Flatpack Non-leaded package) which is one of conventional semiconductor packages, and FIG. 2 is a plan view showing the sealing resin in a transparent state. The semiconductor package shown in these drawings electrically connects the semiconductor element 4 mounted on the die pad 3 supported by the suspension lead 2 of the lead frame 1, the electrode on the upper surface of the semiconductor element 4, and the lead 5 of the lead frame 1. The thin metal wires 6 are connected to each other, and the sealing resin 7 that seals the surrounding region of the semiconductor element 4 including the upper side of the semiconductor element 4 and the lower side of the die pad 3 is provided. This semiconductor package is a non-lead type in which so-called outer leads do not protrude and both inner leads and outer leads are integrated as leads 5. In the lead frame 1 used, the suspension lead 2 is upset so that the die pad 3 is positioned above the lead 5. Thus, since the die pad 3 has a level | step difference, the sealing resin 7 can exist also under the die pad 3. FIG.
[0004]
Since the non-lead type thin semiconductor package (QFN) as described above has a small semiconductor element size, a matrix type manufactured by arranging a plurality of rows in the width direction of one frame is mainly used. Recently, due to the demand for cost reduction, the type of individual molding as shown in FIG. 3 is shifting to the type of batch molding as shown in FIG.
[0005]
In the individual mold type, as shown in FIG. 3A, individual mold cavities C having a small size are provided separately in one frame F, and after molding, the mold is individually punched by a mold. The semiconductor package S shown in 3 (B) is obtained. That is, a semiconductor element is mounted on a die pad of a lead frame with silver paste or the like, wire bonding is performed, individual semiconductor elements are individually molded, and then punched into individual semiconductor packages with a mold.
[0006]
In the collective mold type, as shown in FIG. 4A, several mold cavities C having a large size are provided in one frame F, and each of the mold cavities C has a large number of semiconductors. The elements are arranged in a matrix and the semiconductor elements are molded together, and then the grid leads L of each lead frame are cut with a dicing saw to obtain the semiconductor package S shown in FIG. is there. In other words, a semiconductor element is mounted on a die pad of a lead frame with silver paste or the like, and after wire bonding, a plurality of arrayed semiconductor elements are collectively molded with a predetermined cavity size and then separated by dicing. To do.
[0007]
Recently, the above-described semiconductor package is also used for high-frequency type semiconductor elements that are indispensable for communication equipment. If the semiconductor elements to be mounted in this way become highly integrated, heat generation becomes a problem. Therefore, development of die-pad exposed semiconductor packages has become active.
[0008]
In addition, as semiconductor devices to be mounted become high-frequency types, the electrical characteristics of semiconductor packages have become more demanding, and now semiconductor devices and lead frames are joined from wire bonding to flip chip bonding. There is a tendency to shift to a method. The high-frequency type semiconductor element is moving from a hard Si to a soft compound semiconductor due to its characteristics. Currently, it is mounted on an expensive substrate such as a ceramic. Changes to the package are being considered.
[0009]
[Problems to be solved by the invention]
The above-described non-lead type semiconductor package needs to have a tape attached in advance to the back surface of the lead frame in order to prevent thin burrs from being generated in the lead during resin sealing in the manufacturing process. In addition, there are processes involving heat in the manufacture of semiconductor packages, and heat resistance is required for tapes. However, there is a problem that the tape used at this time is expensive. In addition, there is a problem that wire bonding is hindered by contamination from the tape and a problem that the adhesion of the sealing resin is lowered. Furthermore, the stress when the tape is peeled off may cause delamination in the semiconductor package, or the chip may be electrostatically broken due to static electricity at the time of peeling.
[0010]
In addition, the die pad exposed semiconductor package has a problem that peeling occurs from the interface between the resin and the lead frame due to the difference in thermal expansion coefficient between the resin and the lead frame.
[0011]
On the other hand, a semiconductor device using a compound semiconductor as a material may break due to its softness due to the use of a method that requires thermal pressure such as flip chip bonding. Although there is a high demand for reflow bonding, when solder bonding is performed in a normal QFN, the melted solder flows between the leads after reflow, and in a severe case, it wraps around the terminal surface, which hinders reliability.
[0012]
The present invention has been made in view of such circumstances, and the object of the present invention is to eliminate the need for attaching an expensive tape to the back surface before resin sealing, and to cause peeling of the sealing resin. Further, it is an object of the present invention to provide a method for manufacturing a lead frame that enables flip chip bonding by batch reflow using solder.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a lead frame manufacturing method according to the present invention includes a die pad, a lead, and a frame portion for connecting and fixing the die pad and the lead, and the opposite of the main surface side on which the semiconductor element is mounted. a method of manufacturing a arranged to ing to the lead frame to the least principal surface side insulating resin laminate portion of the back side, the thin plate-shaped substrate having a predetermined shape arranged pattern of (a) a lead frame A step of manufacturing from a metal material, (b) a step of forming an insulating resin laminate having a plurality of predetermined openings on at least the main surface side of the base material of the lead frame, and (c) a gap between the side surfaces of the lead A step of forming an insulating resin laminate portion in (b) and a step of embedding the insulating resin in (c) for preventing leakage on the back side of the base material of the lead frame. Install a peelable member After that, by applying a liquid insulating resin to the entire surface of the lead frame substrate, the insulating resin laminated portion on the main surface side is formed and embedded in the gap between the lead side surfaces at the same time. The step of forming a predetermined opening in the insulating resin laminate after the drying and removal of the peelable member is performed, or the step (b) of forming the insulating resin laminate, and (c) In the process of embedding the insulating resin, after aligning the film-like resin of a predetermined thickness with the main surface side of the lead frame base material, in the gap between the main surface side of the lead frame base material and each lead side surface, It is characterized in that the insulating resin laminated portion and the embedded portion are simultaneously formed by hot pressing and press-fitting, and thereafter a predetermined opening is provided in the insulating resin laminated portion .
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0015]
FIG. 5 is a plan view showing an example of a lead frame manufactured by the method of the present invention, and FIG. 6 is a partially enlarged view of the AA cross section and the BB cross section of the lead frame shown in FIG.
[0016]
As shown in the figure, the lead frame 1 supports the die pad 3 with four suspension leads 2 from the peripheral portion, and four leads 5 protrude from the four sides around the die pad 3 respectively. The insulating resin 8 is embedded between the side surfaces of the leads 5 in a state where a thin laminated portion is formed on the main surface side on which the semiconductor element is mounted. An opening is formed in the thin laminated portion of the insulating resin 8 in the vicinity of the tip of each lead 5 to be a wire connecting portion with the electrode of the semiconductor element, and the opening portion (hatched portion in the figure) is for wire bonding. The plating 9 is applied. Further, an opening is formed in the thin laminated portion of the insulating resin 8 at the die pad where the semiconductor element is mounted, and the opening (hatched portion in the drawing) is plated for die bonding as necessary. 10 is given.
[0017]
In the lead frame 1 of FIG. 5, the thickness of the insulating resin laminated portion disposed on the main surface side after coating and drying is preferably at least 5 to 50 μm. Further, from the viewpoint of improving the warpage of the lead frame 1, it is preferable to dispose an insulating resin laminated portion having a predetermined opening on the back side opposite to the main surface on which the semiconductor element is mounted.
[0018]
The base material of the lead frame 1 is made of a copper material that is incompatible with the insulating resin from the viewpoint of improving the reliability due to the difference in thermal expansion coefficient, and the material is mainly copper having a weight of 90% or more. It is preferable to use a copper alloy.
[0019]
As the insulating resin, it is preferable to use an acrylic resin and a polymer alloy resin solder resist. This solder resist has an elastic modulus of about 5 × 10 −9 Pa and linear expansion coefficients of α 1 = 57 ppm / ° C. and α 2 = 141 ppm / ° C. before and after Tg. Specific products include “PFR-800 AUS402” manufactured by Taiyo Ink Manufacturing Co., Ltd.
[0020]
In order to manufacture the lead frame 1 shown in FIG. 5, first, a base material of the lead frame is manufactured from a thin plate-shaped metal material. That is, a base material in which a plurality of lead frame patterns are arranged in a matrix is manufactured from a thin plate metal material. Then, at least on the main surface side of the base material of the lead frame, comprising the steps that form the insulating resin laminate unit having a plurality of predetermined openings, a step embed an insulating resin into the gap portion between the lead side I do.
[0021]
Specifically, after installing a peelable member for preventing leakage on the back side of the lead frame base material, a liquid insulating resin is applied to the entire surface of the lead frame base material, thereby insulating the main surface side. The resin laminated portion is formed and embedded in the gap between the side surfaces of the lead at the same time, and after the insulating resin is dried and the peelable member is removed, a predetermined opening is provided in the insulating resin laminated portion.
[0022]
Alternatively, after aligning a predetermined thickness of the film-like resin with the main surface side of the lead frame base material, heat pressing and press-fitting into the gap between the main surface side of the lead frame base material and each lead side surface By doing so, the insulating resin laminated portion and the embedded portion are simultaneously formed, and then a predetermined opening is provided in the insulating resin laminated portion.
[0023]
Usually, the base material of the lead frame is patterned by half-etching one surface from both the front and back surfaces, so that the side surface has a sharp cross-sectional shape as shown in FIG. Then, the insulating resin 8 embedded in the space is in a state where the side surface has bite into the lead frame 1. In FIG. 6, the insulating resin 8 is embedded over the entire thickness of the lead frame 1, but it may be embedded at a depth of at least about 1/3 of the thickness from the surface side.
[0024]
The opening provided in the laminated portion of the insulating resin 8 on the main surface side is formed by a photolithography method. Specifically, openings are patterned in the insulating resin 8 at predetermined positions of the leads 5 and the die pad 3 by exposure through a predetermined mask and subsequent development. Then, plating necessary for bonding such as silver, gold, and Pd is performed on the lower metal portion exposed through the opening.
[0025]
A procedure for manufacturing a semiconductor package using the lead frame 1 is as follows. First, a semiconductor element is mounted on the die pad 3 with silver paste, wire bonding is performed between the plating 9 applied to the lead 5 and the electrode on the upper surface of the semiconductor element, and then set in a mold and individually. After being molded, each semiconductor package is punched out by a mold. Since the insulating resin 8 is embedded between the leads 5 at the time of molding, the sealing resin does not wrap around to the back side without attaching a tape to the back surface of the lead frame as in the prior art.
[0026]
A cross-sectional view of the semiconductor package manufactured in this way is shown in FIG. In this semiconductor package, as shown in the figure, the electrode of the semiconductor element 4 mounted on the die pad 3 of the lead frame 1 and the place of the plating 9 applied to the lead 5 of the lead frame are electrically joined by a thin metal wire 6. Insulating resin 8 is embedded between leads 5 of lead frame 1, and sealing resin 7 is provided in a state where insulating resin 8 is sandwiched between lead frame 1. Since the insulating resin 8 has good adhesion to the sealing resin 7 and has a lower elastic modulus than the sealing resin 7, stress due to the difference in thermal expansion coefficient from the lead frame 1 is relieved. , No problems such as peeling.
[0027]
When flip chip type wireless bonding is used instead of wire bonding for electrical bonding between the electrode of the semiconductor element mounted on the die pad and the lead of the lead frame, an opening formed near the tip of the lead 5 is used. However, the bumps of the semiconductor element are aligned and bonded and connected by solder reflow by heat. At this time, since the insulating resin 8 around the opening serves as a weir, solder flow is prevented.
[0028]
In the above description, the individual mold type is described, but the same applies to a batch mold type semiconductor package.
[0029]
【The invention's effect】
The present invention has a die pad, a lead, and a frame part for connecting and fixing the die pad and the lead, and an insulating resin laminate on at least the main surface side of the main surface side on which the semiconductor element is mounted and the opposite back surface side. a method of manufacturing a lead frame parts ing by disposing a, (a) a step of a base material having a predetermined shape lined pattern of the lead frame fabricating a laminar-like metal material, (b) groups of the lead frame A step of forming an insulating resin laminated portion having a plurality of predetermined openings on at least a main surface side of the material, and (c) a step of embedding an insulating resin in a gap between the side surfaces of the leads, After the step of forming the insulating resin laminated portion and the step of embedding the insulating resin in (c) are provided on the back side of the base material of the lead frame, a leakage preventing member is installed on the back side of the base material of the lead frame. Apply liquid insulating resin to the entire surface Thus, the insulating resin laminate portion on the main surface side is formed and embedded in the gap between the side surfaces of the lead at the same time. After drying the insulating resin and removing the peelable member, the insulating resin laminate portion has a predetermined The step of providing the opening is performed, or the step (b) of forming the insulating resin laminated portion and the step (c) of embedding the insulating resin are performed using a film-shaped resin having a predetermined thickness as a lead. After aligning with the main surface side of the base material of the frame, heat insulation and press-fitting into the gap between the main surface side of the lead frame base material and each side surface of the lead frame to embed the insulating resin laminate It is characterized in that it is performed by the procedure of forming a part at the same time and then providing a predetermined opening in the insulating resin laminated part, so that it is possible to omit the sticking of an expensive tape on the back surface when molding the sealing resin. Reduce costs It is possible.
[0030]
Insulating resin in contact with the base material of the lead frame has a low modulus of elasticity, and stress due to the difference in thermal expansion coefficient is relieved. A highly reliable semiconductor package that does not occur can be provided.
[0031]
Further, by forming an opening in the insulating resin laminated portion, it is possible to perform flip chip bonding by batch reflow using solder, and a package corresponding to a high-frequency type semiconductor element can be supplied in the form of an inexpensive QFN.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of a conventional semiconductor package.
2 is a plan view showing the semiconductor package shown in FIG. 1 with its sealing resin seen through. FIG.
FIG. 3 is an explanatory view showing an individual mold type semiconductor package;
FIG. 4 is an explanatory view showing a batch mold type semiconductor package;
FIG. 5 is a plan view showing an example of a lead frame manufactured by the method of the present invention.
6 is a partially enlarged view of the AA cross section and the BB cross section of the lead frame shown in FIG. 5;
7 is a cross-sectional view showing a semiconductor package manufactured using the lead frame shown in FIG. 5;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Lead frame 2 Hanging lead 3 Die pad 4 Semiconductor element 5 Lead 6 Metal fine wire 7 Sealing resin 8 Insulating resin 9 Plating 10 Plating C Mold cavity F Frame L Grid lead S Semiconductor package

Claims (2)

ダイパッドと、リードと、ダイパッドとリードを接続固定する枠部とを有し、半導体素子を搭載する主面側とその反対の裏面側のうちの少なくとも主面側に絶縁性樹脂積層部を配設してなるリードフレームを製造する方法であって、（ａ）リードフレームのパターンが並んだ所定形状の基材を薄板状金属材料より製作する工程と、（ｂ）リードフレームの基材の少なくとも主面側に、所定の開口部を複数有する絶縁性樹脂積層部を形成する工程と、（ｃ）リード側面間の間隙部に絶縁性樹脂を埋め込む工程とを含み、（ｂ）の絶縁性樹脂積層部を形成する工程、及び（ｃ）の絶縁性樹脂を埋め込む工程を、リードフレームの基材の裏面側に漏れ防止用の剥離性部材を設置した後に、リードフレームの基材の全面に液状絶縁性樹脂を塗布することにより、主面側の絶縁性樹脂積層部の形成とリード側面間の間隙部への埋め込みを同時に行い、絶縁性樹脂の乾燥及び剥離性部材の取外し後に、絶縁性樹脂積層部に所定の開口部を設ける手順で行うことを特徴とするリードフレームの製造方法。 It has a die pad, a lead, and a frame part for connecting and fixing the die pad and the lead, and an insulating resin laminated portion is disposed on at least the main surface side of the main surface side on which the semiconductor element is mounted and the opposite back surface side. met method of manufacturing a lead frame formed by, (a) a step of a base material having a predetermined shape lined pattern of the lead frame fabricating a laminar-like metal material, (b) at least predominantly of a substrate of the lead frame A step of forming an insulating resin laminated portion having a plurality of predetermined openings on the surface side, and (c) a step of embedding an insulating resin in a gap portion between the lead side surfaces, step of forming part, and a step of embed an insulating resin (c), after installing the release member for preventing leakage on the back side of the base material of the lead frame, the whole surface of the base material of the lead frame Apply liquid insulating resin Then, the insulating resin laminate portion on the main surface side is simultaneously formed and embedded in the gap between the side surfaces of the leads, and after the insulating resin is dried and the peelable member is removed, a predetermined opening is formed in the insulating resin laminate portion. A method of manufacturing a lead frame, characterized in that the method is performed according to a procedure for providing a portion. ダイパッドと、リードと、ダイパッドとリードを接続固定する枠部とを有し、半導体素子を搭載する主面側とその反対の裏面側のうちの少なくとも主面側に絶縁性樹脂積層部を配設してなるリードフレームを製造する方法であって、（ａ）リードフレームのパターンが並んだ所定形状の基材を薄板状金属材料より製作する工程と、（ｂ）リードフレームの基材の少なくとも主面側に、所定の開口部を複数有する絶縁性樹脂積層部を形成する工程と、（ｃ）リード側面間の間隙部に絶縁性樹脂を埋め込む工程とを含み、（ｂ）の絶縁性樹脂積層部を形成する工程、及び（ｃ）の絶縁性樹脂を埋め込む工程を、所定厚さのフィルム状樹脂をリードフレームの基材の主面側に位置合わせした後、リードフレームの基材の主面側及び各リード側面間の間隙部に、熱圧接及び加圧圧入することにより、絶縁性樹脂積層部と埋め込み部を同時形成し、その後に絶縁性樹脂積層部に所定の開口部を設ける手順で行うことを特徴とするリードフレームの製造方法。 It has a die pad, a lead, and a frame part for connecting and fixing the die pad and the lead, and an insulating resin laminated portion is disposed on at least the main surface side of the main surface side on which the semiconductor element is mounted and the opposite back surface side. met method of manufacturing a lead frame formed by, (a) a step of a base material having a predetermined shape lined pattern of the lead frame fabricating a laminar-like metal material, (b) at least predominantly of a substrate of the lead frame A step of forming an insulating resin laminated portion having a plurality of predetermined openings on the surface side, and (c) a step of embedding an insulating resin in a gap portion between the lead side surfaces, step of forming part, and a step embed an insulating resin (c), after aligning the main surface side of the predetermined thickness film-like resin substrate of the lead frame, the lead frame substrate Between the main surface side and each lead side surface The lead is characterized in that the insulating resin laminated portion and the embedded portion are simultaneously formed by hot-pressing and press-fitting into the gap portion, and thereafter a predetermined opening is provided in the insulating resin laminated portion. Manufacturing method of the frame.
JP2002150063A 2002-05-24 2002-05-24 Lead frame manufacturing method Expired - Fee Related JP3976311B2 (en)

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