JPH09162238A - Terminal electrode on circuit board, formation thereof, circuit board, and semiconductor module - Google Patents

Terminal electrode on circuit board, formation thereof, circuit board, and semiconductor module

Info

Publication number
JPH09162238A
JPH09162238A JP7320258A JP32025895A JPH09162238A JP H09162238 A JPH09162238 A JP H09162238A JP 7320258 A JP7320258 A JP 7320258A JP 32025895 A JP32025895 A JP 32025895A JP H09162238 A JPH09162238 A JP H09162238A
Authority
JP
Japan
Prior art keywords
circuit board
terminal electrode
electrode
semiconductor device
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7320258A
Other languages
Japanese (ja)
Other versions
JP3405628B2 (en
Inventor
Yoshihiro Tomura
善広 戸村
Yoshihiro Bessho
芳宏 別所
Tsukasa Shiraishi
司 白石
Masahiro Ono
正浩 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP32025895A priority Critical patent/JP3405628B2/en
Publication of JPH09162238A publication Critical patent/JPH09162238A/en
Application granted granted Critical
Publication of JP3405628B2 publication Critical patent/JP3405628B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To make smooth flows of sealing resin in facedown bonding of a semiconductor device by using a circuit board that has stepped terminal electrodes with steps. SOLUTION: A circuit board 2 for facedown bonding of a semiconductor device 4 has stepped terminal electrodes 1. For example, the terminal electrode 1 has two or more steps 2a and 2b against the flow of molding resin 7. The height of the step 2a is less than half the average particle size of the filler in the molding resin, whereas that of the step 2b is greater than half the average particle size of the filler. Bump electrodes 5 on pads of the semiconductor device 4 are electrically connected with terminal electrodes 1 on the circuit board 2 through junctions 6 of conductive adhesive or solder. Since the terminal electrodes 1 on the circuit board 2 do not form a vertical barrier against the resin flow, the filler is well distributed in the molding resin 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、フェースダウン
(表面実装)で半導体装置を実装する際の回路基板上の
端子電極とその形成方法および回路基板、ならびにそれ
らを用いた半導体装置の実装体に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal electrode on a circuit board for mounting a semiconductor device face down (surface mounting), a method for forming the terminal electrode, the circuit board, and a semiconductor device mounting body using the same. It is a thing.

【0002】[0002]

【従来の技術】近年の電子機器の小型化や薄型化などに
伴い、LSIチップの高速化、高集積化、多ピン化と同
時に、LSIチップを高密度に回路基板に実装するため
の高密度実装技術が進んできている。そのため、LSI
チップのパッケージもさまざまな形状や構造が提案され
ている(日経エレクトロニクス1993年8−2号n
o.587掲載『LSIパッケージ最前線高密度実装を
後押し』P93〜99)。フェ−スダウン(表面実装の
一種)による実装方法もそのうちの一つである。
2. Description of the Related Art As electronic devices have become smaller and thinner in recent years, the speed of LSI chips, the degree of integration, and the number of pins have been increased. Packaging technology has advanced. Therefore, LSI
Various shapes and structures have also been proposed for chip packages (Nikkei Electronics 1993 No. 8-2 n
o. 587, “Pushing the Leading Edge in High Density Packaging of LSI Packages”, pp. 93-99). A mounting method using face down (a type of surface mounting) is one of them.

【0003】以下、従来のフェ−スダウン実装方法およ
び半導体装置の実装体の具体例について説明する。従来
のフェ−スダウン実装方法に用いられる回路基板として
は、たとえば図17に示すようなものが考えられる。こ
の回路基板上に、半導体装置の突起電極を下向きに実装
するのが、フェ−スダウン実装方法であり、実際に回路
基板上に半導体装置を実装している実装体を示している
のが、図20である。
Specific examples of conventional face-down mounting methods and semiconductor device mounting bodies will be described below. As a circuit board used in the conventional face-down mounting method, for example, the one shown in FIG. 17 can be considered. It is a face-down mounting method that the protruding electrodes of the semiconductor device are mounted downward on this circuit board, and a mounting body in which the semiconductor device is actually mounted on the circuit board is shown in FIG. Twenty.

【0004】次に、フェ−スダウン実装方法において用
いられる回路基板の作成方法について説明する。通常、
プリント基板の端子電極の場合は、積層されたガラス・
エポキシ基板上に銅箔を貼り付け、その上に回路のパタ
ーンを抜いたレジスト膜を形成し、銅箔の露出部分をエ
ッチング液で溶かし、最後にレジストを剥離する。こう
することにより、銅の回路パターンのみがガラス・エポ
キシ基板上に形成される。このときの銅配線膜厚、つま
り銅箔の厚さは、通常18μmである。また、必要に応
じて、銅配線の上にニッケルメッキを行った後に金メッ
キを行うことにより、配線表面の酸化・腐食を抑え、安
定な配線を形成することができる。
Next, a method of making a circuit board used in the face-down mounting method will be described. Normal,
In the case of printed circuit board terminal electrodes, laminated glass
A copper foil is attached on an epoxy substrate, a resist film with a circuit pattern removed is formed thereon, the exposed portion of the copper foil is dissolved with an etching solution, and finally the resist is peeled off. In this way, only copper circuit patterns are formed on the glass epoxy substrate. The copper wiring film thickness at this time, that is, the thickness of the copper foil is usually 18 μm. Further, if necessary, by plating nickel on the copper wiring and then gold plating, oxidation and corrosion of the wiring surface can be suppressed, and stable wiring can be formed.

【0005】セラミック基板の端子電極の場合は、グリ
ーンシート積層後、またはその焼成後にスクリーン印刷
によって配線導体を印刷し、その配線導体を600〜1
000℃で焼成することによって、配線を形成する。こ
のときの配線膜厚は銅で約15μm、金で約5μmであ
る。これはスクリーン版と印刷機の設定と導体ペースト
の粘度で決まる値である。ここでもさらにニッケルメッ
キを行った後に、金メッキを行うことができる。また、
配線ペーストの材料としてはAu、Cu、Ag、AgP
dなどがある。
In the case of a terminal electrode of a ceramic substrate, a wiring conductor is printed by screen printing after stacking the green sheets or after firing the green sheet, and the wiring conductor is set to 600-1.
The wiring is formed by firing at 000 ° C. The wiring film thickness at this time is about 15 μm for copper and about 5 μm for gold. This is a value determined by the settings of the screen plate, the printing machine, and the viscosity of the conductor paste. Here as well, after further nickel plating, gold plating can be performed. Also,
The material of the wiring paste is Au, Cu, Ag, AgP
d etc.

【0006】セラミック基板においても、プリント基板
と類似した配線形成方法がある。それは、セラミック基
板に無電解銅メッキを行った後、その上に回路のパター
ンを抜いたレジスト膜を形成し、銅メッキの露出部分を
エッチング液で溶かし、最後にレジストを剥離させる方
法である。この方法によれば、銅の回路パターンのみが
セラミック基板上に形成される。この場合も銅配線上に
ニッケルメッキした後に金メッキすることができる。
There is also a wiring forming method similar to that of a printed circuit board for a ceramic substrate. This is a method in which after electroless copper plating is performed on a ceramic substrate, a resist film having a circuit pattern is formed thereon, the exposed portion of the copper plating is dissolved by an etching solution, and finally the resist is peeled off. According to this method, only the copper circuit pattern is formed on the ceramic substrate. Also in this case, the copper wiring can be plated with nickel and then plated with gold.

【0007】[0007]

【発明が解決しようとする課題】上記のような従来の回
路基板の端子電極は、図16の断面図に示すような構造
であり、以下のような問題を有している。通常、フェー
スダウンで半導体装置を回路基板の端子電極に実装する
場合、半導体装置の突起電極と回路基板の端子電極との
接続信頼性を高めるために、封止樹脂を半導体装置と回
路基板との間隙に封入する。この封入の際、上記従来例
においては、回路基板の端子電極が、封止樹脂の封入方
向に対して垂直な壁になっているため、封止樹脂中の液
体成分のみが濡れ伝わりやすい。つまり固形分(充填
剤)は、はじめのうちは封止樹脂封入時の勢いで、端子
電極の垂直部分の高さを液体成分とともに濡れ伝わり運
ばれて乗り越えていくことができるが、半導体装置の封
止方向の長さが長くなるにつれて、封止樹脂の封入スピ
ードは低下し、封止樹脂の固形分(充填剤)は、回路基
板上の端子電極の垂直部分の手前に堆積してしまう。以
上のようなことが、各端子電極で発生していた。この状
況を具体的に示しているのが、図18および図19であ
る。各図面において、回路基板上の端子電極が封止樹脂
の封入方向に対して垂直な壁になっているため、充填材
は、その壁を乗り越えていくことができず、回路基板上
の端子電極手前で堆積している。
The above-mentioned conventional terminal electrode of the circuit board has a structure as shown in the sectional view of FIG. 16 and has the following problems. Usually, when mounting a semiconductor device face down on a terminal electrode of a circuit board, in order to enhance the connection reliability between the protruding electrode of the semiconductor device and the terminal electrode of the circuit board, a sealing resin is used between the semiconductor device and the circuit board. Enclose in the gap. At the time of this encapsulation, in the above-mentioned conventional example, the terminal electrode of the circuit board is a wall perpendicular to the encapsulation direction of the encapsulating resin, so that only the liquid component in the encapsulating resin is easily transmitted. In other words, the solid content (filler) can be carried over the height of the vertical portion of the terminal electrode along with the liquid component while being carried by the momentum of the encapsulating resin at the beginning. As the length in the sealing direction becomes longer, the sealing speed of the sealing resin decreases, and the solid content (filler) of the sealing resin accumulates before the vertical portion of the terminal electrode on the circuit board. The above has occurred in each terminal electrode. 18 and 19 specifically show this situation. In each drawing, the terminal electrode on the circuit board is a wall perpendicular to the encapsulation direction of the encapsulating resin, so the filler cannot get over the wall and the terminal electrode on the circuit board It has accumulated in the foreground.

【0008】本発明はこのような問題を解決するために
なされたもので、封止樹脂の封入性を良くする回路基板
上の端子電極とその形成方法、および封止樹脂の封入性
を良くする回路基板、ならびにそれらを用いた半導体装
置の実装体を提供することを目的とする。
The present invention has been made to solve such a problem, and improves a terminal electrode on a circuit board for improving encapsulation of sealing resin, a method of forming the terminal electrode, and encapsulation of sealing resin. An object of the present invention is to provide a circuit board and a semiconductor device mounting body using them.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
の本発明による回路基板上の端子電極は、階段状の段差
を備えていることを特徴とする。この段差は、封止樹脂
中の充填剤の平均粒径の半分以下の厚さであることが好
ましい。このような構成により、封止樹脂中の固形分
(充填剤)が、端子電極面上を液体分とともに乗り越え
ていくことが容易となる。
To achieve the above object, the terminal electrode on the circuit board according to the present invention is characterized in that it has a step-like step. It is preferable that the step has a thickness that is half or less of the average particle diameter of the filler in the sealing resin. With such a configuration, the solid content (filler) in the sealing resin can easily get over the surface of the terminal electrode together with the liquid content.

【0010】さらに、回路基板上の端子電極の階段状の
段幅は、封止樹脂中の充填剤の平均粒径の半分以上の寸
法であることが好ましい。この構成にすることにより、
端子電極の段差に固形分(充填剤)が乗り上げた場合、
端子電極面上の固形分(充填剤)を樹脂分が回路基板に
対して水平方向に運ぶので、封入スピ−ドを低下させる
ことがない。
Furthermore, it is preferable that the stepwise width of the terminal electrodes on the circuit board is at least half the average particle size of the filler in the sealing resin. With this configuration,
If solid content (filler) gets on the step of the terminal electrode,
Since the resin content carries the solid content (filler) on the terminal electrode surface in the horizontal direction with respect to the circuit board, the enclosed speed is not lowered.

【0011】また、フェ−スダウンで半導体装置を実装
する回路基板において、半導体装置と回路基板との間に
封入する封止樹脂の封入性を向上させるための流動補助
電極を備えていることを特徴とする。この構成にするこ
とにより、半導体装置と回路基板との間隙界面に封止樹
脂をより確実に濡れ伝えることが容易となる。さらに好
ましくは、流動補助電極を封止樹脂の封入方向に対し
て、平行にまたは傾斜方向に沿うように配置する。そう
することにより、封止樹脂の封入性をさらに向上させる
ことができる。また、流動補助電極を、回路基板の他の
端子電極と切り離して電気的導通とは無関係な位置に配
置することも好ましい。
Further, in a circuit board on which a semiconductor device is mounted by face-down, a flow auxiliary electrode is provided for improving the encapsulation property of a sealing resin which is sealed between the semiconductor device and the circuit board. And With this configuration, it becomes easy to more surely transfer the sealing resin to the gap interface between the semiconductor device and the circuit board. More preferably, the flow auxiliary electrode is arranged in parallel with or along the inclined direction with respect to the sealing resin enclosing direction. By doing so, the sealing property of the sealing resin can be further improved. It is also preferable to separate the flow assisting electrode from the other terminal electrodes of the circuit board and arrange it at a position irrelevant to electrical conduction.

【0012】さらに、上述した端子電極の本発明による
形成方法には、メッキ法によるものとエッチング法によ
るものとがある。メッキ法によれば、まずはじめに回路
基板上に端子電極を形成すべき領域を除いてレジスト層
Aを形成し、前記端子電極を形成すべき領域にメッキ法
により封止樹脂の充填剤の平均粒径の半分以下の厚さの
端子電極を析出させる。次に、形成された端子電極上に
その端子電極の外縁から封止樹脂の充填剤の平均粒径の
半分以上の寸法だけ内側に小さい領域を除いてレジスト
層Bを形成し、再びメッキ法により、前記端子電極上に
封止樹脂の充填剤の平均粒径の半分以下の厚さの端子電
極を析出させる。そして最後に、すべてのレジスト膜を
溶解または剥離することにより、2段階の階段状の段差
を有する端子電極を形成することができる。また、上記
工程を繰り返すことにより、3段階以上の階段状の段差
を有する端子電極も形成できる。
Further, the method of forming the above-mentioned terminal electrode according to the present invention includes a method by a plating method and a method by an etching method. According to the plating method, first, the resist layer A is formed on the circuit board except the region where the terminal electrode is to be formed, and the average particle of the filler of the sealing resin is formed in the region where the terminal electrode is to be formed by the plating method. A terminal electrode having a thickness not more than half the diameter is deposited. Next, a resist layer B is formed on the formed terminal electrode by removing a small region inward from the outer edge of the terminal electrode by a dimension equal to or more than half the average particle diameter of the filler of the sealing resin, and again by plating. A terminal electrode having a thickness not more than half the average particle diameter of the filler of the sealing resin is deposited on the terminal electrode. Finally, by dissolving or peeling off all the resist films, a terminal electrode having a two-step stepped step can be formed. In addition, by repeating the above steps, a terminal electrode having three or more steps in steps can be formed.

【0013】エッチング法によれば、まずはじめに回路
基板上の全面に導電体層を形成し、端子電極を形成すべ
き領域にレジスト層Aを形成し、そのレジスト層Aに覆
われていない領域の導電体層を除くようにエッチングを
行う。次に、レジスト層Aを溶解または剥離して端子電
極を露出させ、その端子電極上に、電極の外縁から封止
樹脂の充填剤の平均粒径の半分以上の寸法だけ内側に小
さい領域にレジスト層Bを形成し、そのレジスト層Bが
形成されていない領域を所定の厚さの導電体層が残るよ
うにエッチングを行う。そして、レジスト層Bを溶解ま
たは剥離することにより、2段階の階段状の段差を有す
る端子電極を形成することができる。また、上記工程で
露出した電極上段面の外縁から封止樹脂の充填剤の平均
粒径の半分以上の寸法だけ内側に小さい領域および電極
下段面を含む領域にレジスト層Cを形成し、レジスト層
Cが形成されていない領域を所定の厚さの導電体層が残
るようにエッチングし、レジスト層Cを溶解または剥離
することにより、3段階の階段状の段差を有する端子電
極を形成することができる。この工程を繰り返すと、4
段階以上の階段状の段差を有する端子電極も形成でき
る。
According to the etching method, first, a conductor layer is formed on the entire surface of a circuit board, a resist layer A is formed in a region where a terminal electrode is to be formed, and a region not covered with the resist layer A is formed. Etching is performed so as to remove the conductor layer. Next, the resist layer A is dissolved or peeled off to expose the terminal electrode, and the resist is formed on the terminal electrode in a small area inward from the outer edge of the electrode by a dimension of at least half the average particle diameter of the filler of the sealing resin. The layer B is formed, and the region where the resist layer B is not formed is etched so that a conductor layer having a predetermined thickness remains. Then, by melting or peeling the resist layer B, a terminal electrode having a two-step stepped step can be formed. In addition, a resist layer C is formed in a region including a small region and an electrode lower stage face inward from the outer edge of the electrode upper stage face exposed in the above step by a dimension of half or more of the average particle size of the filler of the sealing resin, A region where C is not formed is etched so that a conductor layer having a predetermined thickness remains, and the resist layer C is melted or peeled off to form a terminal electrode having a three-step staircase-like step. it can. Repeat this process to 4
It is also possible to form a terminal electrode having a step-like step having more than one step.

【0014】これらの方法により、本発明に適した端子
電極を形成することができる。また、上述した回路基板
上の端子電極と半導体装置とをフェ−スダウン実装法に
より実装し、それらの間に封止樹脂を封入すれば、信頼
性の高い接続部を有する半導体装置の実装体を得ること
ができる。
By these methods, a terminal electrode suitable for the present invention can be formed. Further, by mounting the terminal electrode on the circuit board and the semiconductor device by a face-down mounting method and encapsulating a sealing resin between them, a semiconductor device mounting body having a highly reliable connection portion can be obtained. Obtainable.

【0015】[0015]

【発明の実施の形態】以下、この発明の具体的な実施形
態を図面に基づいて説明する。まず、図8を用いて、本
実施形態における半導体装置の実装体を説明する。図8
(a)は、多層回路基板2上に半導体装置4が複数個実
装されているもの(マルチチップモジュール)の断面図
であり、図8(b)は、回路基板上に半導体装置4が単
体で実装されているもの(チップサイズパッケージ)の
断面図である。図8(a)は、フェ−スダウンで複数の
半導体装置4が多層回路基板2上に実装されている。半
導体装置4と多層回路基板2との間隙部は、封止樹脂7
によって充填封止されている。図8(b)は、フェ−ス
ダウンで単体の半導体装置4が回路基板2上に実装され
ている。半導体装置4と回路基板2との間隙部は、封止
樹脂7によって充填封止されている。なお、後述する他
の実施形態においても、半導体装置の実装体の全体構造
は、図8と同様である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. First, the semiconductor device mounting body according to the present embodiment will be described with reference to FIG. FIG.
FIG. 8A is a cross-sectional view of one in which a plurality of semiconductor devices 4 are mounted on the multilayer circuit board 2 (multichip module), and FIG. 8B is a single semiconductor device 4 on the circuit board. It is sectional drawing of what is mounted (chip size package). In FIG. 8A, a plurality of semiconductor devices 4 are mounted on the multilayer circuit board 2 in a face-down manner. The gap between the semiconductor device 4 and the multilayer circuit board 2 is covered with the sealing resin 7
It is filled and sealed by. In FIG. 8B, a single semiconductor device 4 is mounted on the circuit board 2 by face-down. The gap between the semiconductor device 4 and the circuit board 2 is filled and sealed with the sealing resin 7. In addition, also in other embodiments described later, the entire structure of the mounted body of the semiconductor device is the same as that in FIG.

【0016】図1は、この発明の第1の実施形態を示し
ている。図1の断面図に示すように、この第1の実施形
態の端子電極1は、回路基板2上に、階段状の段差を備
えている。この端子電極1の階段状の段差は、封止樹脂
の封入方向に対して備えられており、この段差を備えた
ことで、端子電極が垂直な壁とはならず、封止樹脂の封
入後の分散状態が良好となる。
FIG. 1 shows a first embodiment of the present invention. As shown in the cross-sectional view of FIG. 1, the terminal electrode 1 of the first embodiment has a step-like step on a circuit board 2. This step-like step of the terminal electrode 1 is provided in the encapsulation direction of the encapsulating resin, and by providing this step, the terminal electrode does not become a vertical wall, and after encapsulating the encapsulating resin. The dispersion state of is good.

【0017】次に、この第1の実施形態である端子電極
の形成方法を、図4に基づいて説明する。まず、図4
(a)に示すように、回路基板2上の端子電極を形成す
べき領域を除いた部分に、レジスト層Aを形成させる。
次に、図4(b)に示すように、回路基板2上の端子電
極を形成すべき領域に、メッキ法により封止樹脂の充填
剤の平均粒径の半分以下の厚さの端子電極を析出させ
る。これが端子電極1の1段目となる。次に、図4
(c)に示すように、図4(b)で形成された端子電極
1の1段目の上に、その端子電極の外縁から封止樹脂の
充填剤の平均粒径の半分以上の寸法だけ内側に小さい領
域を除いてレジスト層Bを形成させる。次に、図4
(d)に示すように、端子電極1の1段目の上に、再び
メッキ法により、封止樹脂の充填剤の平均粒径の半分以
下の厚さの端子電極を析出させる。そして最後に、図4
(e)に示すように、すべてのレジスト膜を溶解、また
は剥離して、回路基板2上に階段状の段差を有する端子
電極1を露出させ、必要な場合には回路基板2および端
子電極1を洗浄する。以上の方法により、2段階の階段
状の段差を有する端子電極を形成することができる。ま
た、上記方法において、図4(c)および図4(d)に
示される工程を繰り返し行うことにより、3段階以上の
階段状の段差を有する端子電極1を形成することができ
る。
Next, the method of forming the terminal electrode according to the first embodiment will be described with reference to FIG. First, FIG.
As shown in (a), a resist layer A is formed on a portion of the circuit board 2 excluding a region where a terminal electrode is to be formed.
Next, as shown in FIG. 4B, a terminal electrode having a thickness not more than half the average particle diameter of the filler of the sealing resin is formed by plating on the area where the terminal electrode is to be formed on the circuit board 2. Precipitate. This is the first stage of the terminal electrode 1. Next, FIG.
As shown in (c), on the first stage of the terminal electrode 1 formed in FIG. 4 (b), from the outer edge of the terminal electrode, only a size equal to or more than half the average particle size of the filler of the sealing resin is provided. A resist layer B is formed on the inside except for a small region. Next, FIG.
As shown in (d), a terminal electrode having a thickness equal to or smaller than half the average particle diameter of the filler of the sealing resin is deposited on the first stage of the terminal electrode 1 by plating again. And finally, Figure 4
As shown in (e), all the resist films are dissolved or peeled off to expose the terminal electrodes 1 having step-like steps on the circuit board 2 and, if necessary, the circuit board 2 and the terminal electrodes 1 To wash. By the above method, a terminal electrode having a two-step stepped step can be formed. Further, in the above method, by repeating the steps shown in FIGS. 4C and 4D, it is possible to form the terminal electrode 1 having a step difference of three steps or more.

【0018】この第1の実施形態である端子電極1へ、
突起電極5が二段突起形状である半導体装置4を実装し
た実装体の構造を示しているのが、図9である。これ
は、フェ−スダウンにより、半導体装置4の電極パッド
部11上に形成された突起電極5と、回路基板2上の階
段状の段差を備えた端子電極1とが、接合層6を介して
電気的に接続されている。半導体装置4と回路基板2と
の間隙部は、封止樹脂7によって充填封止されている。
半導体装置4の突起電極5は、端子電極1との接続を安
定に行うために、ワイヤ−ボンディング法により二段突
起状に形成されている。図9において、7は封止樹脂、
8は充填剤の平均粒径、9は充填剤の最大粒径、10は
充填剤の最小粒径である。また、矢印は封止樹脂の封入
方向を示している。
To the terminal electrode 1 according to the first embodiment,
FIG. 9 shows the structure of a mounting body on which the semiconductor device 4 in which the protruding electrodes 5 have a two-step protruding shape is mounted. This is because the protruding electrode 5 formed on the electrode pad portion 11 of the semiconductor device 4 and the terminal electrode 1 having a step-like step on the circuit board 2 by the face-down via the bonding layer 6. It is electrically connected. The gap between the semiconductor device 4 and the circuit board 2 is filled and sealed with the sealing resin 7.
The protruding electrode 5 of the semiconductor device 4 is formed in a two-step protruding shape by a wire-bonding method in order to stably connect with the terminal electrode 1. In FIG. 9, 7 is a sealing resin,
8 is the average particle size of the filler, 9 is the maximum particle size of the filler, and 10 is the minimum particle size of the filler. The arrow indicates the direction of encapsulation of the sealing resin.

【0019】図2は、この発明の第2の実施形態を示し
ている。図2の断面図に示すように、この第2の実施形
態の端子電極1は、回路基板2上に階段状の段差を有
し、その段差は封止樹脂中の充填剤の平均粒径の半分以
下の厚さで構成されている。この端子電極1の階段状の
段差は、封止樹脂の封入方向に対して備えられており、
その厚さは、充填剤の平均粒径の半分以下であるので、
端子電極が垂直な壁とはならず、封止樹脂の封入後の分
散状態が良好となる。
FIG. 2 shows a second embodiment of the present invention. As shown in the cross-sectional view of FIG. 2, the terminal electrode 1 of the second embodiment has a step-like step on the circuit board 2, and the step is the average particle size of the filler in the sealing resin. The thickness is less than half. The step-like step of the terminal electrode 1 is provided in the sealing resin sealing direction,
Since its thickness is less than half the average particle size of the filler,
The terminal electrode does not form a vertical wall, and the dispersion state after encapsulation of the sealing resin is good.

【0020】この第2の実施形態である端子電極1へ、
突起電極5が二段突起形状である半導体装置4を実装し
た実装体の構造を示しているのが、図10である。これ
は、フェ−スダウンにより、半導体装置4の電極パッド
部11上に形成された突起電極5と、回路基板2上の階
段状の段差を備えた端子電極1とが、接合層6を介して
電気的に接続されている。半導体装置4と回路基板2と
の間隙部は、封止樹脂7によって充填封止されている。
半導体装置4の突起電極5は、端子電極1との接続を安
定に行うために、ワイヤ−ボンディング法により二段突
起状に形成されている。
To the terminal electrode 1 according to the second embodiment,
FIG. 10 shows the structure of a mounting body on which the semiconductor device 4 in which the protruding electrodes 5 have a two-step protruding shape is mounted. This is because the protruding electrode 5 formed on the electrode pad portion 11 of the semiconductor device 4 and the terminal electrode 1 having a step-like step on the circuit board 2 by the face-down via the bonding layer 6. It is electrically connected. The gap between the semiconductor device 4 and the circuit board 2 is filled and sealed with the sealing resin 7.
The protruding electrode 5 of the semiconductor device 4 is formed in a two-step protruding shape by a wire-bonding method in order to stably connect with the terminal electrode 1.

【0021】図3は、この発明の第3の実施形態を示し
ている。図3の断面図に示すように、この第3の実施形
態の端子電極1は、回路基板2上に階段状の段差を有
し、その段差2aは封止樹脂中の充填剤の平均粒径の半
分以下の厚さであり、その段幅2bは封止樹脂中の充填
剤の平均粒径の半分以上の寸法で構成されている。この
端子電極1の階段状の段差は、封止樹脂の封入方向に対
して上記の寸法で構成されているので、端子電極が垂直
な壁とはならず、封止樹脂の封入後の分散状態が良好と
なる。
FIG. 3 shows a third embodiment of the present invention. As shown in the cross-sectional view of FIG. 3, the terminal electrode 1 of the third embodiment has a step-like step on the circuit board 2, and the step 2a is the average particle size of the filler in the sealing resin. Is less than half the thickness, and the step width 2b is configured to have a dimension not less than half the average particle diameter of the filler in the sealing resin. Since the step-like step of the terminal electrode 1 is formed in the above-mentioned dimension with respect to the encapsulation direction of the sealing resin, the terminal electrode does not become a vertical wall, and the dispersed state after encapsulation of the sealing resin Will be good.

【0022】次に、この第3の実施形態である端子電極
1の形成方法を、図5に基づいて説明する。まず、図5
(a)に示すように、回路基板2の全面に導電体層3を
形成する。次に、図5(b)に示すように、端子電極を
形成すべき領域にレジスト層Aを形成する。次に、図5
(c)に示すように、レジスト層Aに覆われていない領
域の導電体層3を除くようにエッチングを行う。次に、
図5(d)に示すように、レジスト層Aを溶解または剥
離して導電体層3を露出させる。次に、図5(e)に示
すように、図5(d)で形成された導電体層3の上に、
その電極の外縁から封止樹脂の充填剤の平均粒径の半分
以上の寸法だけ内側に小さい領域を形成するようにレジ
スト層Bを形成する。次に、図5(f)に示すように、
導電体層3上のレジスト層Bが形成されていない領域に
おいて、封止樹脂の充填剤の平均粒径の半分以下の厚さ
の導電体層3が残るようにエッチングを行う。次に、図
5(g)に示すように、レジスト層Bを溶解または剥離
する。ここまでの工程で2段階の階段状の段差を有する
端子電極を形成することができる。次に、図5(h)に
示すように、図5(g)で形成された端子電極上に、そ
の端子電極の外縁から封止樹脂の充填剤の平均粒径の半
分以上の寸法だけ内側に小さい領域および図5(f)で
形成された端子電極にレジスト層Cを形成する。次に、
図5(i)に示すように、端子電極上のレジスト層Cが
形成されていない領域において、図5(f)で形成され
た端子電極の厚さに封止樹脂の充填剤の平均粒径の半分
以下の厚さを加えた寸法の厚さの端子電極が残るように
エッチングを行う。次に、図5(j)に示すように、レ
ジスト層Cを溶解または剥離して回路基板2上に階段状
の段差を有する端子電極1を露出させる。以上の方法に
より、3段階の階段状の段差を備えた端子電極1を形成
することができる。さらに、前記方法の図5(h)〜図
5(j)に示される工程を繰り返し行うことにより、4
段階以上の階段状の段差を有する端子電極1を形成する
こともできる。また、必要な場合には回路基板2および
端子電極1を洗浄する。なお、はじめに回路基板2の全
面に形成する導電体層は、銅箔を貼り付ける物でも、無
電解銅メッキでもよく、あるいはその他の導体でもよ
い。
Next, a method of forming the terminal electrode 1 according to the third embodiment will be described with reference to FIG. First, FIG.
As shown in (a), the conductor layer 3 is formed on the entire surface of the circuit board 2. Next, as shown in FIG. 5B, a resist layer A is formed in the region where the terminal electrode is to be formed. Next, FIG.
As shown in (c), etching is performed so as to remove the conductor layer 3 in the region not covered with the resist layer A. next,
As shown in FIG. 5D, the resist layer A is dissolved or peeled off to expose the conductor layer 3. Next, as shown in FIG. 5E, on the conductor layer 3 formed in FIG.
The resist layer B is formed so as to form a small region inward from the outer edge of the electrode by a dimension that is at least half the average particle diameter of the filler of the sealing resin. Next, as shown in FIG.
Etching is performed so that the conductor layer 3 having a thickness equal to or less than half the average particle diameter of the filler of the sealing resin remains in a region where the resist layer B is not formed on the conductor layer 3. Next, as shown in FIG. 5G, the resist layer B is dissolved or peeled off. Through the steps up to this point, a terminal electrode having a two-step step difference can be formed. Next, as shown in FIG. 5H, on the terminal electrode formed in FIG. A resist layer C is formed on the small area and on the terminal electrode formed in FIG. next,
As shown in FIG. 5 (i), in the region where the resist layer C on the terminal electrode is not formed, the average particle diameter of the filler of the sealing resin is set to the thickness of the terminal electrode formed in FIG. 5 (f). Etching is performed so that a terminal electrode having a thickness equal to or less than half of the above remains. Next, as shown in FIG. 5J, the resist layer C is dissolved or peeled off to expose the terminal electrode 1 having a step-like step on the circuit board 2. By the method described above, the terminal electrode 1 having a three-step stepped step can be formed. Further, by repeating the steps shown in FIGS. 5 (h) to 5 (j) of the above method, 4
It is also possible to form the terminal electrode 1 having a step-like step having more than one step. If necessary, the circuit board 2 and the terminal electrode 1 are washed. The conductor layer formed on the entire surface of the circuit board 2 may be a copper foil adhered material, electroless copper plating, or another conductor.

【0023】この第3の実施形態である端子電極1へ、
突起電極5が二段突起形状である半導体装置4を実装し
た実装体の構造を示しているのが、図12である。これ
は、フェ−スダウンにより、半導体装置4の電極パッド
部11上に形成された突起電極5と、回路基板2上の階
段状の段差を備えた端子電極1とが、接合層6を介して
電気的に接続されている。半導体装置4と回路基板2と
の間隙部は、封止樹脂7によって充填封止されている。
半導体装置4の突起電極5は、端子電極1との接続を安
定に行うために、ワイヤ−ボンディング法により二段突
起状に形成されている。
To the terminal electrode 1 according to the third embodiment,
FIG. 12 shows the structure of a mounting body on which the semiconductor device 4 in which the protruding electrodes 5 have a two-step protruding shape is mounted. This is because the protruding electrode 5 formed on the electrode pad portion 11 of the semiconductor device 4 and the terminal electrode 1 having a step-like step on the circuit board 2 by the face-down via the bonding layer 6. It is electrically connected. The gap between the semiconductor device 4 and the circuit board 2 is filled and sealed with the sealing resin 7.
The protruding electrode 5 of the semiconductor device 4 is formed in a two-step protruding shape by a wire-bonding method in order to stably connect with the terminal electrode 1.

【0024】図6は、この発明の第4の実施形態を示し
ている。図6の平面図に示すように、この第4の実施形
態においては、回路基板2を真上から見て、流動補助電
極1aが、回路基板2上に封入される封止樹脂7の封入
方向に対して、平行にまたは傾斜方向に沿って備えられ
ている。加えていうならば、流動補助電極1aは、その
長手方向が、封止樹脂7の封入方向に対して平行にまた
は傾斜方向に沿うような形で配置されている。端子電極
1は、通常、回路基板2上に最適化されたものだけが構
成されるが、この第4の実施形態では、上述したとおり
封止樹脂の封入方向に対して平行または傾斜した形で、
流動補助電極1aが加えられている。以上の構成にした
ことにより、封止樹脂が流動補助電極1aに沿って流れ
るので、封止樹脂の封入後の分散状態が良好となる。こ
の流動補助電極1aのライン幅と長さは、極端に太くし
ないか、または隣接間とショ−トの危険性がなければ、
特に制限しない。
FIG. 6 shows a fourth embodiment of the present invention. As shown in the plan view of FIG. 6, in the fourth embodiment, when the circuit board 2 is viewed from directly above, the flow auxiliary electrode 1a is sealed in the sealing resin 7 on the circuit board 2 in the sealing direction. , Parallel to or along the tilt direction. In addition, the flow assisting electrode 1a is arranged such that the longitudinal direction thereof is parallel to the sealing direction of the sealing resin 7 or along the inclined direction. Normally, only the optimized terminal electrode 1 is formed on the circuit board 2. However, in the fourth embodiment, as described above, the terminal electrode 1 is parallel or inclined with respect to the encapsulation direction of the sealing resin. ,
The flow auxiliary electrode 1a is added. With the above configuration, the sealing resin flows along the auxiliary flow electrodes 1a, so that the dispersed state of the sealing resin after encapsulation becomes good. The line width and length of the flow assisting electrode 1a should not be made extremely thick, or if there is no risk of shorting between adjacent parts,
There is no particular limitation.

【0025】この第4の実施形態である流動補助電極1
aを備えた回路基板2に、半導体装置4を実装した場合
の実装体の構造を示す平面図が、図14である。これ
は、フェ−スダウンにより、半導体装置4の電極パッド
部11上に形成された突起電極5と、回路基板2上の端
子電極1とが、接合層6を介して電気的に接続されてい
る。上述したように、端子電極1には、封止樹脂の封入
方向に対して平行または傾斜した流動補助電極1aが、
さらに加えられており、半導体装置4と回路基板2との
間隙部は、封止樹脂7によって充填封止されている。
The flow assisting electrode 1 according to the fourth embodiment
FIG. 14 is a plan view showing the structure of the mounting body when the semiconductor device 4 is mounted on the circuit board 2 provided with a. This is because the protruding electrode 5 formed on the electrode pad portion 11 of the semiconductor device 4 and the terminal electrode 1 on the circuit board 2 are electrically connected via the bonding layer 6 by face down. . As described above, the terminal electrode 1 is provided with the flow auxiliary electrode 1a that is parallel or inclined with respect to the sealing resin sealing direction.
In addition, the gap between the semiconductor device 4 and the circuit board 2 is filled and sealed with the sealing resin 7.

【0026】図7は、この発明の第5の実施形態を示し
ている。図7の平面図に示すように、この第5の実施形
態においては、回路基板を真上から見て、流動補助電極
1bが、通常の最適化された電気的導通に関係のある端
子電極1とは別に、電気的導通には全く無関係な箇所
に、封止樹脂の封入方向に対して平行にまたは傾斜方向
に沿って備えられている。以上の構成にしたことによ
り、封止樹脂が、流動補助電極1bに沿って流れるの
で、封止樹脂の封入性が良好となる。流動補助電極1b
のライン幅と長さは、極端に太くしないか、または周辺
の電気的導通のある端子電極とのショ−トの危険性がな
ければ、特に制限しない。
FIG. 7 shows a fifth embodiment of the present invention. As shown in the plan view of FIG. 7, in the fifth embodiment, when the circuit board is viewed from directly above, the flow auxiliary electrode 1b is connected to the terminal electrode 1 which is related to normal optimized electrical conduction. Separately from the above, it is provided at a position that is completely unrelated to electrical conduction, either parallel to the sealing resin enclosing direction or along the inclined direction. With the above configuration, the sealing resin flows along the flow assisting electrode 1b, so that the encapsulating property of the sealing resin becomes good. Flow auxiliary electrode 1b
The line width and length are not particularly limited as long as they are not extremely thick or there is no risk of short-circuiting with the surrounding terminal electrodes having electrical conduction.

【0027】この第5の実施形態である流動補助電極1
bを備えた回路基板2に、半導体装置4を実装した場合
の実装体の構造を示す平面図が、図15である。これ
は、フェ−スダウンにより、半導体装置4の電極パッド
部11上に形成された突起電極5と、回路基板2上の端
子電極1とが、接合層6を介して電気的に接続されてい
る。上述したように、回路基板2上には、電気的導通に
は全く無関係な箇所に、封止樹脂の封入方向に対して平
行または傾斜して流動補助電極1bが加えられており、
半導体装置4と回路基板2との間隙部は、封止樹脂7に
よって充填封止されている。
The flow assisting electrode 1 according to the fifth embodiment
FIG. 15 is a plan view showing the structure of the mounting body when the semiconductor device 4 is mounted on the circuit board 2 provided with b. This is because the protruding electrode 5 formed on the electrode pad portion 11 of the semiconductor device 4 and the terminal electrode 1 on the circuit board 2 are electrically connected via the bonding layer 6 by face down. . As described above, the flow assisting electrode 1b is added to the circuit board 2 at a position that is completely unrelated to electrical conduction, in parallel or at an inclination with respect to the encapsulation direction of the sealing resin.
The gap between the semiconductor device 4 and the circuit board 2 is filled and sealed with the sealing resin 7.

【0028】図11は、この発明の第6の実施形態を示
している。図11の断面図に示すように、これは、フェ
−スダウンにより、半導体装置4の電極パッド部11上
に形成された突起電極5と、回路基板2上の階段状の段
差を備えた端子電極1とが、接合層6を介して電気的に
接続されている。また、半導体装置4と回路基板2との
間隙部は、封止樹脂7によって充填封止されている。さ
らに、半導体装置4の突起電極5は、メッキ法により形
成されている。
FIG. 11 shows a sixth embodiment of the present invention. As shown in the cross-sectional view of FIG. 11, this is a terminal electrode provided with a bump electrode 5 formed on the electrode pad portion 11 of the semiconductor device 4 by face down and a step-like step on the circuit board 2. 1 are electrically connected to each other through the bonding layer 6. The gap between the semiconductor device 4 and the circuit board 2 is filled and sealed with the sealing resin 7. Furthermore, the protruding electrode 5 of the semiconductor device 4 is formed by a plating method.

【0029】図13は、この発明の第7の実施形態を示
している。図13の断面図に示すように、この第7の実
施形態の端子電極1は、回路基板2上の封止樹脂の封入
方向に向かってのみ階段状の段差を有し、その段差2a
は封止樹脂中の充填剤の平均粒径の半分以下の厚さであ
り、その段幅2bは封止樹脂中の充填剤の平均粒径の半
分以上の寸法で構成されている。この端子電極1の階段
状の段差は、封止樹脂の封入方向に対してのみ以上のよ
うに構成されているので、端子電極が垂直な壁とはなら
ず、封止樹脂の封入後の分散状態が良好となる。半導体
装置4と回路基板2との間隙部は、封止樹脂7によって
充填封止されており、半導体装置4の突起電極5は、端
子電極との接続を安定に行うために、ワイヤ−ボンディ
ング法により二段突起状に形成されている。
FIG. 13 shows a seventh embodiment of the present invention. As shown in the cross-sectional view of FIG. 13, the terminal electrode 1 of the seventh embodiment has a step-like step only toward the sealing resin sealing direction on the circuit board 2, and the step 2a
Is a thickness not more than half the average particle diameter of the filler in the sealing resin, and the step width 2b is configured to have a dimension not less than half the average particle diameter of the filler in the sealing resin. Since the step-like step of the terminal electrode 1 is configured as described above only in the encapsulation direction of the encapsulating resin, the terminal electrode does not form a vertical wall, and dispersion after encapsulating the encapsulating resin is not achieved. The condition is good. The gap between the semiconductor device 4 and the circuit board 2 is filled and sealed with a sealing resin 7, and the protruding electrodes 5 of the semiconductor device 4 are wire-bonded by a wire bonding method in order to stably connect with the terminal electrodes. Is formed in a two-step projection shape.

【0030】また、以上の各実施形態における端子電極
1の材質については特に限定はなく、たとえば、Cuま
たはNi等が考えられ、その形成方法としては、Cuメ
ッキ、NiメッキおよびAuメッキ等が考えられる。
Further, the material of the terminal electrode 1 in each of the above embodiments is not particularly limited, and Cu or Ni, for example, can be considered, and as the forming method, Cu plating, Ni plating, Au plating, etc. can be considered. To be

【0031】さらに、半導体装置4の電極パッド部11
上に形成された突起電極については、その形状として二
段突起形状等、その材質としてはAu等が考えられる。
また、各実施形態においては、半導体装置4の電極パッ
ド部11上に形成された突起電極と、回路基板2の端子
電極1とがフェ−スダウン(ワイヤレスボンディング)
により接合される方法について説明したが、本発明は、
これに限定されるものではなく、たとえばワイヤボンデ
ィング装置により形成する方法等も好ましい。
Further, the electrode pad portion 11 of the semiconductor device 4
The shape of the protruding electrode formed above may be a two-step protruding shape, and the material may be Au or the like.
Further, in each embodiment, the protruding electrode formed on the electrode pad portion 11 of the semiconductor device 4 and the terminal electrode 1 of the circuit board 2 are face down (wireless bonding).
Although the method of joining by
The method is not limited to this, and a method of forming with a wire bonding device is also preferable.

【0032】さらに、回路基板2上の端子電極1と、半
導体装置4の電極パッド部11上に形成された突起電極
5とを接合する接合層については、導電性接着剤および
半田等が考えられる。
Further, as the bonding layer for bonding the terminal electrode 1 on the circuit board 2 and the protruding electrode 5 formed on the electrode pad portion 11 of the semiconductor device 4, a conductive adhesive, solder or the like is considered. .

【0033】[0033]

【発明の効果】本発明によれば、回路基板の端子電極に
階段状の段差を備えることにより、回路基板上の端子電
極が、封止樹脂の封入方向に対して垂直な壁とはなら
ず、封止樹脂の封入後の分散状態が良好となる。また、
回路基板に流動補助電極を備えることにより、封止樹脂
を、半導体装置と回路基板との間隙に封入スピードを低
下させることなく、また、固形分(充填剤)を沈降、堆
積するのを防ぎながら良好に封入することができる。さ
らに、以上に示した構成の端子電極や回路基板に半導体
装置を実装することにより、封止樹脂封入後の半導体装
置の実装部および端子電極周辺については、封止樹脂中
の液体分と固形分の分散が良くなり、信頼性の高い接続
が得られる。
According to the present invention, since the terminal electrode of the circuit board is provided with the step-like step, the terminal electrode on the circuit board does not become a wall perpendicular to the sealing resin enclosing direction. The dispersion state after encapsulation of the sealing resin becomes good. Also,
By providing a flow auxiliary electrode on the circuit board, the sealing resin is not sealed in the gap between the semiconductor device and the circuit board, and the solid content (filler) is prevented from settling and depositing. It can be sealed well. Further, by mounting the semiconductor device on the terminal electrode or the circuit board having the above-described configuration, the mounting portion of the semiconductor device after encapsulating the sealing resin and the periphery of the terminal electrode have a liquid content and a solid content in the sealing resin. Distribution is better and a reliable connection is obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態に係る回路基板上の端
子電極を示す概略断面図
FIG. 1 is a schematic cross-sectional view showing a terminal electrode on a circuit board according to a first embodiment of the present invention.

【図2】本発明の第2の実施形態に係る回路基板上の端
子電極を示す概略断面図
FIG. 2 is a schematic sectional view showing a terminal electrode on a circuit board according to a second embodiment of the present invention.

【図3】本発明の第3の実施形態に係る回路基板上の端
子電極を示す概略断面図
FIG. 3 is a schematic sectional view showing a terminal electrode on a circuit board according to a third embodiment of the present invention.

【図4】図1の端子電極の形成方法を説明するための工
程図
4A to 4C are process diagrams for explaining a method of forming the terminal electrode of FIG.

【図5】図3の端子電極の形成方法を説明するための工
程図
5A to 5C are process diagrams for explaining a method of forming the terminal electrode of FIG.

【図6】本発明の第4の実施形態に係る回路基板を示す
概略平面図
FIG. 6 is a schematic plan view showing a circuit board according to a fourth embodiment of the present invention.

【図7】本発明の第5の実施形態に係る回路基板を示す
概略平面図
FIG. 7 is a schematic plan view showing a circuit board according to a fifth embodiment of the present invention.

【図8】本発明の各実施形態に係る実装体の全体構造を
示す断面図
FIG. 8 is a cross-sectional view showing the overall structure of a mounting body according to each embodiment of the present invention

【図9】図1の端子電極を有する回路基板に突起電極が
二段突起形状である半導体装置を実装した実装体の電極
接続部の構造を示す拡大断面図
9 is an enlarged cross-sectional view showing the structure of an electrode connection portion of a mounting body in which a semiconductor device having projecting electrodes having a two-step projecting shape is mounted on the circuit board having the terminal electrodes of FIG. 1;

【図10】図2の端子電極を有する回路基板に突起電極
が二段突起形状である半導体装置を実装した実装体の電
極接続部の構造を示す拡大断面図
10 is an enlarged cross-sectional view showing a structure of an electrode connection portion of a mounting body in which a semiconductor device having projecting electrodes in a two-step projecting shape is mounted on a circuit board having the terminal electrodes of FIG.

【図11】本発明の第6の実施形態に係る実装体の電極
接続部の構造を示す拡大断面図
FIG. 11 is an enlarged cross-sectional view showing a structure of an electrode connecting portion of a mounting body according to a sixth embodiment of the present invention.

【図12】図3の端子電極を有する回路基板に突起電極
が二段突起形状である半導体装置を実装した実装体の電
極接続部の構造を示す拡大断面図
12 is an enlarged cross-sectional view showing a structure of an electrode connecting portion of a mounting body in which a semiconductor device having projecting electrodes in a two-step projecting shape is mounted on a circuit board having the terminal electrodes of FIG.

【図13】本発明の第7の実施形態に係る実装体の電極
接続部の構造を示す拡大断面図
FIG. 13 is an enlarged cross-sectional view showing a structure of an electrode connecting portion of a mounting body according to a seventh embodiment of the present invention.

【図14】図6の回路基板に半導体装置を実装した実装
体の概略平面図
14 is a schematic plan view of a mounting body in which a semiconductor device is mounted on the circuit board of FIG.

【図15】図7の回路基板に半導体装置を実装した実装
体の概略平面図
15 is a schematic plan view of a mounting body in which a semiconductor device is mounted on the circuit board of FIG.

【図16】従来例に係る回路基板上の端子電極を示す概
略断面図
FIG. 16 is a schematic cross-sectional view showing a terminal electrode on a circuit board according to a conventional example.

【図17】従来例に係る回路基板を示す概略平面図FIG. 17 is a schematic plan view showing a circuit board according to a conventional example.

【図18】従来例の端子電極を有する回路基板に突起電
極が二段突起形状である半導体装置を実装した実装体の
電極接続部の構造を示す拡大断面図
FIG. 18 is an enlarged cross-sectional view showing a structure of an electrode connecting portion of a mounting body in which a semiconductor device having protruding electrodes in a two-step protruding shape is mounted on a circuit board having terminal electrodes of a conventional example.

【図19】従来例の端子電極を有する回路基板に半導体
装置を実装した実装体の電極接続部の構造を示す拡大断
面図
FIG. 19 is an enlarged cross-sectional view showing a structure of an electrode connecting portion of a mounting body in which a semiconductor device is mounted on a circuit board having a terminal electrode of a conventional example.

【図20】従来例の回路基板に半導体装置を実装した実
装体の概略平面図
FIG. 20 is a schematic plan view of a mounting body in which a semiconductor device is mounted on a conventional circuit board.

【符号の説明】[Explanation of symbols]

1 端子電極 1a 流動補助電極 1b 電気的導通に無関係な流動補助電極 2 回路基板 2a 端子電極段差 2b 端子電極段幅 3 導電体層 4 半導体装置 5 突起電極 6 接合層 7 封止樹脂 8 充填剤(平均粒径) 9 最大粒径 10 最小粒径 11 電極パッド部 1 Terminal Electrode 1a Flow Auxiliary Electrode 1b Flow Auxiliary Electrode Irrelevant to Electrical Conduction 2 Circuit Board 2a Terminal Electrode Step 2b Terminal Electrode Step Width 3 Conductor Layer 4 Semiconductor Device 5 Projection Electrode 6 Bonding Layer 7 Sealing Resin 8 Filler ( Average particle size 9 Maximum particle size 10 Minimum particle size 11 Electrode pad

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小野 正浩 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Ono 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (23)

【特許請求の範囲】[Claims] 【請求項1】 フェースダウンで半導体装置を実装する
回路基板上の端子電極であって、階段状の段差を備えて
いることを特徴とする回路基板上の端子電極。
1. A terminal electrode on a circuit board on which a semiconductor device is mounted face down, the terminal electrode on the circuit board having a step-like step.
【請求項2】 回路基板上の端子電極が、封止樹脂の注
入方向に向かって少なくとも2段以上の階段状の段差を
備えていることを特徴とする請求項1記載の回路基板上
の端子電極。
2. The terminal on the circuit board according to claim 1, wherein the terminal electrode on the circuit board has a step-like step having at least two steps in the injection direction of the sealing resin. electrode.
【請求項3】 回路基板上の端子電極の階段状の段差
が、封止樹脂中の充填剤の平均粒径の半分以下の厚さで
あることを特徴とする請求項1または2記載の回路基板
上の端子電極。
3. The circuit according to claim 1, wherein the step-like step difference of the terminal electrode on the circuit board has a thickness not more than half the average particle diameter of the filler in the sealing resin. Terminal electrodes on the substrate.
【請求項4】 回路基板上の端子電極の階段状の段幅
が、封止樹脂中の充填剤の平均粒径の半分以上の寸法で
あることを特徴とする請求項1、2または3記載の回路
基板上の端子電極。
4. The step-shaped step width of the terminal electrode on the circuit board is equal to or more than half the average particle diameter of the filler in the sealing resin. Terminal electrodes on the circuit board.
【請求項5】 フェ−スダウンで半導体装置を実装する
回路基板において、半導体装置と回路基板との間に封入
する封止樹脂の封入性を向上させるための流動補助電極
を備えていることを特徴とする回路基板。
5. A circuit board on which a semiconductor device is mounted by face-down is provided with a flow auxiliary electrode for improving encapsulation of a sealing resin sealed between the semiconductor device and the circuit board. And a circuit board.
【請求項6】 流動補助電極が、封止樹脂の封入方向に
対して平行にまたは傾斜方向に沿うように配置されてい
ることを特徴とする請求項5記載の回路基板。
6. The circuit board according to claim 5, wherein the flow assisting electrode is disposed in parallel with or along the inclined direction with respect to the encapsulation direction of the sealing resin.
【請求項7】 半導体装置の突起電極との接続用の端子
電極とは切り離して、電気的導通とは無関係な位置に、
前記流動補助電極が備えられていることを特徴とする請
求項5または6記載の回路基板。
7. A semiconductor device, which is separated from a terminal electrode for connection with a protruding electrode and is located at a position unrelated to electrical conduction,
7. The circuit board according to claim 5, wherein the flow auxiliary electrode is provided.
【請求項8】 端子電極の材質がCuまたはNiである
請求項1から4のいずれか1項記載の回路基板上の端子
電極。
8. The terminal electrode on the circuit board according to claim 1, wherein the material of the terminal electrode is Cu or Ni.
【請求項9】 回路基板上の端子電極および流動補助電
極の材質が、CuまたはNiである請求項5、6または
7記載の回路基板。
9. The circuit board according to claim 5, 6 or 7, wherein the material of the terminal electrode and the flow auxiliary electrode on the circuit board is Cu or Ni.
【請求項10】 端子電極がCuメッキ、Niメッキま
たはAuメッキによって形成されている請求項1から4
のいずれか1項記載の回路基板上の端子電極。
10. The terminal electrode is formed by Cu plating, Ni plating or Au plating.
The terminal electrode on the circuit board according to claim 1.
【請求項11】 回路基板上の端子電極および流動補助
電極が、Cuメッキ、NiメッキまたはAuメッキによ
って形成されている請求項5、6または7記載の回路基
板。
11. The circuit board according to claim 5, 6 or 7, wherein the terminal electrode and the flow auxiliary electrode on the circuit board are formed by Cu plating, Ni plating or Au plating.
【請求項12】 フェースダウンで半導体装置を実装す
る回路基板上の端子電極の形成方法であって、前記回路
基板上に端子電極を形成すべき領域を除いてレジスト層
Aを形成する工程aと、前記端子電極を形成すべき領域
にメッキ法により封止樹脂の充填剤の平均粒径の半分以
下の厚さの端子電極を析出させる工程bと、その工程b
で形成された端子電極上にその端子電極の外縁から封止
樹脂の充填剤の平均粒径の半分以上の寸法だけ内側に小
さい領域を除いてレジスト層Bを形成する工程cと、再
びメッキ法により、前記端子電極上に封止樹脂の充填剤
の平均粒径の半分以下の厚さの端子電極を析出させる工
程dと、すべてのレジスト膜を溶解または剥離する工程
eとからなる、2段階の階段状の段差を有する端子電極
を形成する回路基板上の端子電極の形成方法。
12. A method of forming a terminal electrode on a circuit board for mounting a semiconductor device face down, comprising the step a of forming a resist layer A on the circuit board except a region where the terminal electrode is to be formed. A step b in which a terminal electrode having a thickness not more than half the average particle diameter of the filler of the sealing resin is deposited in a region where the terminal electrode is to be formed by a plating method, and the step b
A step c of forming a resist layer B on the terminal electrode formed by removing a small area inward from the outer edge of the terminal electrode by a dimension equal to or more than half the average particle diameter of the filler of the sealing resin, and plating again. The step d of depositing a terminal electrode having a thickness not more than half the average particle size of the filler of the sealing resin on the terminal electrode, and the step e of dissolving or peeling all the resist films. A method of forming a terminal electrode on a circuit board, the terminal electrode having a stepped step.
【請求項13】 請求項12記載の回路基板上の端子電
極の形成方法において、工程cおよび工程dを繰り返し
行い、最後に工程eを行うことからなる、3段階以上の
階段状の段差であって各段の厚さが封止樹脂の充填剤の
平均粒径の半分以下である段差を有する端子電極を形成
する回路基板上の端子電極の形成方法。
13. The method of forming a terminal electrode on a circuit board according to claim 12, wherein the step c and the step d are repeated, and finally the step e is performed. A method of forming a terminal electrode on a circuit board, wherein a terminal electrode having a step in which the thickness of each step is less than or equal to half the average particle diameter of the filler of the sealing resin is formed.
【請求項14】 フェ−スダウンで半導体装置を実装す
る回路基板上の端子電極の形成方法であって、前記回路
基板上の全面に導電体層を形成する工程aと前記端子電
極を形成すべき領域にレジスト層Aを形成する工程b
と、前記レジスト層Aに覆われていない領域の導電体層
を除くようにエッチングする工程cと、前記レジスト層
Aを溶解または剥離して端子電極を露出させる工程d
と、前記端子電極上に、その電極の外縁から封止樹脂の
充填剤の平均粒径の半分以上の寸法だけ内側に小さい領
域にレジスト層Bを形成する工程eと、前記レジスト層
Bが形成されていない領域を所定の厚さの導電体層が残
るようにエッチングする工程fと、前記レジスト層Bを
溶解または剥離する工程gとからなる、2段階の階段状
の段差であって各段の厚さが封止樹脂の充填剤の平均粒
径の半分以下である段差を有する端子電極を形成する回
路基板上の端子電極の形成方法。
14. A method of forming a terminal electrode on a circuit board for mounting a semiconductor device by face-down, comprising: forming a conductor layer on the entire surface of the circuit board; and forming the terminal electrode. Step b of forming resist layer A in the region
A step c of etching so as to remove the conductor layer in a region not covered by the resist layer A, and a step d of dissolving or peeling the resist layer A to expose the terminal electrode.
And a step e of forming a resist layer B on the terminal electrode in a small area inward from the outer edge of the electrode by a dimension equal to or more than half the average particle diameter of the filler of the sealing resin, and forming the resist layer B. The step is a step-like step of two steps, which includes a step f of etching an unetched region so that a conductor layer having a predetermined thickness remains, and a step g of dissolving or peeling the resist layer B. A method of forming a terminal electrode on a circuit board, wherein a terminal electrode having a step whose thickness is less than or equal to half the average particle size of the filler of the sealing resin is formed.
【請求項15】 請求項14記載の回路基板上の端子電
極の形成方法において、工程gで露出した電極上段面の
外縁から封止樹脂の充填剤の平均粒径の半分以上の寸法
だけ内側に小さい領域および電極下段面を含む領域にレ
ジスト層Cを形成する工程hと、前記レジスト層Cが形
成されていない領域を所定の厚さの導電体層が残るよう
にエッチングする工程iと、前記レジスト層Cを溶解ま
たは剥離する工程jとからなる、3段階の階段状の段差
であって各段の厚さが封止樹脂の充填剤の平均粒径の半
分以下である段差を有する端子電極を形成する回路基板
上の端子電極の形成方法。
15. The method of forming a terminal electrode on a circuit board according to claim 14, wherein the outer edge of the upper electrode surface exposed in step g is inward by a dimension not less than half the average particle diameter of the filler of the sealing resin. A step h of forming a resist layer C in an area including a small area and an electrode lower surface, and a step i of etching an area in which the resist layer C is not formed so that a conductor layer having a predetermined thickness remains. A terminal electrode having a three-step step-like step consisting of a step j of dissolving or peeling the resist layer C, in which the thickness of each step is not more than half the average particle size of the filler of the sealing resin. Forming a terminal electrode on a circuit board.
【請求項16】 請求項15記載の回路基板上の端子電
極の形成方法において、工程h〜jを繰り返すことから
なる、4段階以上の階段状の段差であって各段の厚さが
封止樹脂の充填剤の平均粒径の半分以下である段差を有
する端子電極を形成する回路基板上の端子電極の形成方
法。
16. The method for forming a terminal electrode on a circuit board according to claim 15, wherein steps h to j are repeated to form a step-like step having four or more steps and each step has a thickness. A method for forming a terminal electrode on a circuit board, the method comprising forming a terminal electrode having a step that is equal to or less than half the average particle diameter of a resin filler.
【請求項17】 半導体装置の電極パッド部上に形成さ
れた突起電極と、回路基板上の端子電極とが、接合層を
介して電気的に接続される半導体装置の実装体であっ
て、前記端子電極が請求項1から4のいずれか1項記載
の構造であることを特徴とする半導体装置の実装体。
17. A semiconductor device mounting body, wherein a protruding electrode formed on an electrode pad portion of a semiconductor device and a terminal electrode on a circuit board are electrically connected via a bonding layer, A package of a semiconductor device, wherein the terminal electrode has the structure according to any one of claims 1 to 4.
【請求項18】 半導体装置の電極パッド部上に形成さ
れた突起電極と、回路基板上の端子電極とが、接合層を
介して電気的に接続される半導体装置の実装体であっ
て、前記回路基板上の端子電極が請求項5、6または7
記載の構造であることを特徴とする半導体装置の実装
体。
18. A package of a semiconductor device, wherein a protruding electrode formed on an electrode pad portion of the semiconductor device and a terminal electrode on a circuit board are electrically connected via a bonding layer, The terminal electrode on the circuit board is defined by claim 5, 6 or 7.
A semiconductor device mounting body having the structure described.
【請求項19】 半導体装置の電極パッド部上に形成さ
れた突起電極が2段突起形状である請求項17または1
8記載の半導体装置の実装体。
19. The projection electrode formed on the electrode pad portion of the semiconductor device has a two-step projection shape.
8. A semiconductor device package according to item 8.
【請求項20】 半導体装置の電極パッド部上に形成さ
れた突起電極の材質がAuである請求項17または18
記載の半導体装置の実装体。
20. The material of the protruding electrode formed on the electrode pad portion of the semiconductor device is Au.
A packaged semiconductor device as described above.
【請求項21】 半導体装置の電極パッド部上に形成さ
れた突起電極がワイヤボンディング装置により形成され
る請求項17または18記載の半導体装置の実装体。
21. The semiconductor device mounting body according to claim 17, wherein the protruding electrode formed on the electrode pad portion of the semiconductor device is formed by a wire bonding device.
【請求項22】 半導体装置の電極パッド部上に形成さ
れた突起電極がメッキ法により形成される請求項17ま
たは18記載の半導体装置の実装体。
22. The semiconductor device mounting body according to claim 17, wherein the protruding electrode formed on the electrode pad portion of the semiconductor device is formed by a plating method.
【請求項23】 接合層が導電性接着剤または半田から
なる請求項17または18記載の半導体装置の実装体。
23. The semiconductor device package according to claim 17, wherein the bonding layer is made of a conductive adhesive or solder.
JP32025895A 1995-12-08 1995-12-08 Terminal electrode on circuit board, method for forming the same, and package of semiconductor device Expired - Fee Related JP3405628B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123310A (en) * 2005-10-25 2007-05-17 Aoi Electronics Co Ltd Semiconductor device
JP2008205057A (en) * 2007-02-19 2008-09-04 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP2010103187A (en) * 2008-10-21 2010-05-06 Internatl Business Mach Corp <Ibm> Printed wiring board and method of manufacturing the same
JP2011109152A (en) * 2011-03-09 2011-06-02 Internatl Business Mach Corp <Ibm> Printed wiring board and method of manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123310A (en) * 2005-10-25 2007-05-17 Aoi Electronics Co Ltd Semiconductor device
JP4627480B2 (en) * 2005-10-25 2011-02-09 アオイ電子株式会社 Semiconductor device
JP2008205057A (en) * 2007-02-19 2008-09-04 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP2010103187A (en) * 2008-10-21 2010-05-06 Internatl Business Mach Corp <Ibm> Printed wiring board and method of manufacturing the same
US8209856B2 (en) 2008-10-21 2012-07-03 International Business Machines Corporation Printed wiring board and method for manufacturing the same
JP2011109152A (en) * 2011-03-09 2011-06-02 Internatl Business Mach Corp <Ibm> Printed wiring board and method of manufacturing the same

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