JP2023142146A - Package substrate and semiconductor device - Google Patents

Abstract

To achieve both GND potential stability and prevention of delamination.SOLUTION: A package substrate 1 that fixes a semiconductor chip 11 with a back surface 11b at a predetermined potential to a surface 1a facing the back surface includes: a wiring layer 3a having a predetermined potential: an insulating layer 4 laminated on an upper surface 3a1 of the wiring layer and having a plurality of openings 41 in which a part of the wiring layer is exposed formed at a position facing the back surface of the semiconductor chip; and a plurality of conductive bumps 6 provided on the upper surface of the wiring layer exposed through the openings, and each having a top portion 6a that is closer to the back surface of the semiconductor chip than a front surface 4a of the insulating layer.SELECTED DRAWING: Figure 3

Description

The present invention relates to a package substrate and a semiconductor device.

In a BGA (ball grid array) package as a semiconductor device, a semiconductor chip is mounted on a BGA substrate (package substrate) with the back surface of the semiconductor chip facing the front surface of the BGA substrate (package substrate). Here, as a method for stabilizing the GND (ground) voltage of the semiconductor chip, there is a method of conducting electricity from the back surface of the semiconductor chip to the wiring in the BGA substrate through silver paste. When using this method, there is a known technique in which a part of the solder resist (SR) on the surface of the BGA substrate is opened to ensure conductivity, and the copper pattern of the top layer wiring facing the back surface of the semiconductor chip is exposed through this opening. (Patent Document 1).

Here, when operating a device or the like that responds quickly at high voltage, it is required to ensure a stable GND voltage. If this cannot be ensured, there is a risk that defects in electrical characteristics will occur in device operation.
In order to improve the stability of the GND level, it is effective to increase the opening area of the solder resist on the surface of the BGA substrate. Moreover, the silver paste has adhesiveness to the solder resist.

Japanese Patent Application Publication No. 2000-133742

However, silver paste has a limited adhesion with copper and surface plating compared to its adhesion with solder resist. Therefore, if the opening area of the solder resist is increased too much, the adhesion between the BGA substrate and the silver paste will decrease, and peeling may occur starting from the contact point between the copper and the silver paste.

In other words, when the opening area of the solder resist is increased in order to improve the stability of the GND level of the semiconductor chip, the adhesion between the silver paste and the solder resist decreases, resulting in peeling when a load is applied. There is a possibility that problems such as delamination may occur during reflow. Therefore, there is a demand for simultaneously improving the stability of the GND level of the semiconductor chip and suppressing the occurrence of delamination between the semiconductor chip and the BGA substrate.

The present invention has been made in view of the above circumstances, and aims to provide a package substrate and a semiconductor device that can simultaneously improve the stability of the GND level of a semiconductor chip and improve the operational stability by preventing the occurrence of delamination. It is an attempt to achieve a goal.

A package substrate according to one embodiment of the present invention includes:
A package substrate on which a semiconductor chip with a back surface at a predetermined potential is fixed to a surface opposite to the back surface,
a wiring layer having the predetermined potential;
an insulating layer that is laminated on the upper surface of the wiring layer and has a plurality of openings that expose parts of the wiring layer at positions facing the back surface of the semiconductor chip;
a plurality of conductive bumps provided on the upper surface of the wiring layer each exposed from the opening and having a top portion closer to the back surface of the semiconductor chip than the front surface of the insulating layer;
has,
This solved the above problem.

A semiconductor device according to another aspect of the present invention includes:
The above package board,
the semiconductor chip;
a conductive adhesive that fixes the back surface of the semiconductor chip, the top of the conductive bump and the surface of the insulating layer;
has,
be able to.

According to the present invention, it is possible to provide a package substrate and a semiconductor device that can simultaneously improve GND level stability and improve operational stability due to the occurrence of delamination. .

1 is a cross-sectional view showing a first embodiment of a package substrate according to the present invention. FIG. 1 is a top view showing a first embodiment of a package substrate according to the present invention. 1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. FIG. 3 is a cross-sectional view showing a second embodiment of the semiconductor device according to the present invention.

Hereinafter, a first embodiment of a package substrate and a semiconductor device according to the present invention will be described based on the drawings.
FIG. 1 is a top view showing a package substrate in this embodiment. FIG. 2 is a cross-sectional view showing the package substrate in this embodiment. In the figure, numeral 1 is a package substrate.

The package substrate 1 according to this embodiment is a BGA substrate, as shown in FIGS. 1 and 2. Solder balls 2 as external terminals are arranged on the back surface 1b of a rectangular package substrate 1. The package substrate 1 has a plurality of wiring layers 3 such as signal wiring or connection wiring, vertical wiring 3c such as through holes, etc. installed inside and near the front and back surfaces.

A semiconductor chip 11, which will be described later, is placed on a surface 1a of the package substrate 1 opposite to the solder balls 2 and connected thereto. In the package substrate 1, a semiconductor chip 11 is connected to an upper connection wiring layer (wiring layer) 3a closest to the surface 1a. A solder resist (insulating layer) 4 is laminated on the upper connection wiring layer (wiring layer) 3a. An opening 41 is formed in the solder resist (insulating layer) 4. The upper connection wiring layer (wiring layer) 3a exposed from this opening 41 serves as a terminal connected to the semiconductor chip 11.

Similarly, in the package substrate 1, the semiconductor chip 11 is connected to the lower connection wiring layer (wiring layer) 3b closest to the back surface 1b. An insulating layer 5 is laminated on the lower connection wiring layer (wiring layer) 3b. An opening 5a is formed in the insulating layer 5. The lower connection wiring layer (wiring layer) 3b exposed from the opening 5a serves as a terminal connected to the solder ball 2.
In the package substrate 1, the wiring layer 3 may be formed other than the above-mentioned upper connection wiring layer (wiring layer) 3a, lower connection wiring layer (wiring layer) 3b, and vertical wiring 3c, and the structure thereof is not particularly limited. , other wiring is not illustrated in this embodiment. The upper connection wiring layer (wiring layer) 3a is set to the GND voltage of the semiconductor chip 11.

On the surface 1a of the package substrate 1, as shown in FIG. 2, a plurality of openings 41 are formed within a chip area 1C that overlaps the semiconductor chip 11 in plan view. The chip area (chip area) 1C is set corresponding to the contour shape of the semiconductor chip 11, which will be described later, as shown by the broken line in FIG. A bonding area (bonding area) 1D is formed near the outer periphery of the chip area (chip area) 1C to which a bonding wire for connecting to an electrode of the semiconductor chip 11 is connected.

The opening 41 opens on the surface 4a of the solder resist (insulating layer) 4. A plurality of openings 41 are formed spaced apart from each other in the chip area (chip area) 1C. Although not shown, an opening is formed in the solder resist (insulating layer) 4 also in the bonding area 1D.

In this embodiment, the plurality of openings 41 all have the same circular outline, but are not limited to this outline. Further, although the plurality of openings 41 all have the same diameter, the diameter does not have to be the same. Further, although the plurality of openings 41 are all arranged with the same distance, the distance relationship is not limited to this.

The opening 41 penetrates the solder resist (insulating layer) 4 in the thickness direction. In the opening 41, the upper surface three a1 of the upper connection wiring layer (wiring layer) 3a is exposed. The opening 41 has the same contour shape over the entire length of the solder resist (insulating layer) 4 in the thickness direction.
The openings 41 all have the same depth dimension D1 in the chip area (chip area) 1C. The depth dimension D1 of the opening 41 is equal to the thickness dimension D1 of the solder resist (insulating layer) 4 in the chip region (chip area) 1C.

That is, the solder resist (insulating layer) 4 is formed to have a uniform thickness D1 over at least the entire chip region (chip area) 1C. In this configuration, it is sufficient that the openings 41 formed in the chip area 1C have the same depth D1, and the depths of the openings formed in other areas are not limited. Various aspects can be adopted for the components in the package substrate 1 and their forms.

Conductive bumps 6 are provided on the upper connection wiring layer (wiring layer) 3a exposed in the opening 41, respectively.
The conductive bumps 6 can be formed in all the openings 41 in the chip area (chip area) 1C. In the chip region (chip area) 1C, there may be an opening 41 in which the conductive bump 6 is not provided. In the chip area (chip area) 1C, the conductive bumps 6 are preferably formed in at least half of the openings 41. In the chip region (chip area) 1C, it is more preferable that the conductive bumps 6 are formed in two-thirds or more of the openings 41.

Furthermore, it is preferable that the conductive bumps 6 are formed in the openings 41 arranged along the periphery of the chip area (chip area) 1C. The conductive bump 6 is preferably formed in an opening 41 located near the center of the chip area (chip area) 1C.

The lower end 6b of the conductive bump 6 contacts the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a exposed in the opening 41.
The conductive bump 6 protrudes from the opening 41 in the thickness direction. That is, the top portion 6a of the conductive bump 6 is formed at a position protruding from the opening 41 in the thickness direction. The top portion 6a of the conductive bump 6 is formed at a position protruding from the surface 4a of the solder resist (insulating layer) 4 at a predetermined protrusion height (height) D2 in the thickness direction. The top portion 6a of the conductive bump 6 is closer to the back surface 10b of the semiconductor chip 11, which will be described later, than the front surface 4a of the solder resist (insulating layer) 4.

In the thickness direction of the package substrate 1, a protrusion height D2 at which the top portion 6a of the conductive bump 6 protrudes from the front surface 4a of the solder resist (insulating layer) 4 toward the back surface 11b of the semiconductor chip 11, which will be described later, is the opening. 41 is smaller than the depth D1. In other words,
D2 ≦ D1
It is preferable that

Note that the protrusion heights D2 of the plurality of conductive bumps 6 can all be made equal. Alternatively, the protrusion height D2 of the plurality of conductive bumps 6 can be formed as an average value of at least the conductive bumps 6 protruding from the surface 4a of the solder resist (insulating layer) 4.

When viewed in the thickness direction of the package substrate 1, the outline of the conductive bump 6 is smaller than or the same as the outline of the opening 41 formed in the solder resist (insulating layer) 4. Here, the outline of the conductive bump 6 is the external outline when the package substrate 1 is viewed from above, and when the shape of the conductive bump 6 changes in the height direction of the conductive bump 6, means the maximum external contour.
When the outline of the conductive bump 6 is smaller than the outline of the opening 41, there may be a portion within the opening 41 where the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a is exposed.

For example, when the conductive bump 6 is a copper pillar, the outline of the conductive bump 6 is the same circular as the outline of the opening 41, and the shape of the conductive bump 6 changes in the height direction of the conductive bump 6. do not. Therefore, in this case, the conductive bump 6 of the copper pillar is formed into a substantially cylindrical shape having substantially the same cross-sectional shape as the opening 41. The substantially cylindrical conductive bump 6 is erected from the upper surface 3 a 1 of the upper connection wiring layer (wiring layer) 3 a exposed in the opening 41 .
Further, in this case, the top portion 6a of the conductive bump 6 can be formed in a plane that is substantially inclined to the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a.

When the conductive bump 6 is a copper pillar, in order to manufacture it, the surface of the solder resist (insulating layer) 4 is applied to the substrate on which the upper connection wiring layer (wiring layer) 3a is formed by a predetermined manufacturing process. Form 4a. Furthermore, a photoresist is formed by a photolithography process or the like and exposed and developed to form a solder resist (insulating layer) 4 having a pattern corresponding to the opening 41 and a predetermined pattern.

After that, a predetermined pattern such as an opening 41 is formed in the solder resist (insulating layer) 4, and the upper surface 3a1 corresponding to the opening 41 is exposed. Further, after forming a predetermined mask covering areas other than the opening 41, conductive bumps 6 in the form of copper pillars are grown on the upper surface 3a1 exposed from the opening 41 by plating or the like. At this time, the conductive bumps 6 are formed to a protruding height D2 protruding from the surface 4a of the solder resist (insulating layer) 4 by growing the film to a predetermined thickness by, for example, electrolytic plating or electroless plating. As a result, a cylindrical conductive bump 6 having a contour corresponding to the contour of the opening 41 is formed.

Alternatively, when the conductive bump 6 is a gold ball, the outline of the conductive bump 6 is smaller than or the same circular shape as the outline of the opening 41, and the conductive bump 6 The shape decreases in diameter toward the top 6a. In this case, the conductive bump 6 of the gold ball can be formed in the shape of a water droplet having a cross-sectional shape substantially the same as the opening 41 and decreasing in diameter from the lower end 6b toward the top 6a. This columnar conductive bump 6 is erected from the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a exposed in the opening 41.
Further, in this case, the top portion 6a of the conductive bump 6 can be formed into a sharp shape in a direction away from the upper surface three a1 of the upper connection wiring layer (wiring layer) 3a.
In this case, the top portion 6a of the formed conductive bump 6 may be made of cut gold wire, or may be subjected to processing such as pounding or other shaping.

When the conductive bump 6 is a gold ball, in order to manufacture it, a solder resist (insulating layer) 4 having a pattern corresponding to the opening 41 and a predetermined pattern is prepared in the same way as when the conductive bump 6 is a copper pillar. Form.

Thereafter, conductive bumps 6 are formed using a conventionally known technique such as a wire bonder. That is, a gold ball is formed using a wire bonder so as to be in contact with the upper surface 3a1 exposed from the opening 41, a gold wire is formed into a predetermined shape, and then the solder resist (insulating layer) 4 is cut. The conductive bumps 6 are formed to protrude from the surface 4a to a protruding height D2. As a result, a ball-shaped conductive bump 6 having a contour corresponding to the contour of the opening 41 and deformed so that the top portion 6a protrudes is formed.

Note that the top portion 6a of the conductive bump 6 can have a predetermined surface condition. Specifically, in order to improve contact and adhesion with the silver paste 12 described later, it is preferable to form predetermined irregularities on the surface of the top portion 6a. This is the same whether the conductive bumps 6 are copper pillars or gold balls.

In the package substrate 1 according to the present embodiment, the conductive bumps 6 with the tops 6a protruding from the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a exposed in the opening 41 are provided in the opening 41. The surface area of the conductive bump 6 becomes larger than the area of the exposed upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a. Thereby, when connecting from the upper connection wiring layer (wiring layer) 3a to the semiconductor chip 11, the area that comes into contact with the silver paste (conductive adhesive) 12 can be increased as described later. The bonding surface area between the silver paste 12 and the upper connection wiring layer (wiring layer) 3a increases.

Thereby, it is possible to achieve low resistance. Therefore, the conductivity between the upper connection wiring layer (wiring layer) 3a and the semiconductor chip 11 is improved, for example, the conductivity between the upper connection wiring layer (wiring layer) 3a which is the GND voltage is improved, and the semiconductor chip It is possible to ensure stability of the GND voltage at 11. At the same time, it is possible to reduce resistance and improve heat dissipation characteristics.
Moreover, since the area of the opening 41 does not change, the adhesion between the silver paste 12 and the surface 4a of the solder resist (insulating layer) 4 does not deteriorate.

Since the protruding height D2 of the top portion 6a of the conductive bump 6 protruding from the surface 4a of the solder resist (insulating layer) 4 is smaller than the depth D1 of the opening 41, the back surface 11b of the semiconductor chip 11 is coated with the silver paste 12. When the conductive bumps 6 and the back surface 11b of the semiconductor chip 11 are connected to each other, the conductive bumps 6 and the back surface 11b of the semiconductor chip 11 are not separated more than necessary, the conductivity is improved, and it is possible to realize a stable GND voltage on the semiconductor chip 11. .

FIG. 3 is a cross-sectional view showing the semiconductor device in this embodiment.
As shown in FIG. 3, the semiconductor device 10 according to this embodiment includes a package substrate 1, a semiconductor chip 11, and a silver paste (conductive adhesive) 12.
The semiconductor device 10 is set with the semiconductor chip 11 fixed (attached) to the front surface 1a of the package substrate 1, and the back surface 11b of the semiconductor chip 11 and the front surface 1a of the package substrate 1 are bonded with silver paste (conductive adhesive). adhesive) 12. The conductive bumps 6, which are electrodes on the package substrate 1, and the back surface 11b of the semiconductor chip 11 are electrically connected by a silver paste (conductive adhesive) 12.

Furthermore, in the semiconductor device 10, the front surface 11a of the semiconductor chip 11 and the front surface 1a of the package substrate 1 are electrically connected by bonding wires 13. The bonding wire 13 is connected to an electrode formed in a bonding area 1D on the front surface 1a of the package substrate 1. Note that electrodes in this bonding region (bonding area) 1D are not shown.
On the surface 1 a of the package substrate 1 of the semiconductor device 10 , a semiconductor chip 11 , bonding wires 13 , and silver paste (conductive adhesive) 12 are sealed with a transfer mold 14 .

Here, the back surface 11b of the semiconductor chip 11, the top 6a of the conductive bump 6, the surface 4a of the solder resist (insulating layer) 4, and the silver paste (conductive adhesive) 12 are formed as follows. .
In the thickness direction of the package substrate 1, the distance D3 between the back surface 11b of the semiconductor chip 11 and the front surface 4a of the solder resist (insulating layer) 4 is greater than or equal to the thickness D1 of the solder resist (insulating layer) 4. It is preferable that

That is, the protrusion height D2 of the top 6a of the conductive bump 6, the depth D1 of the opening 41, that is, the thickness D1 of the solder resist (insulating layer) 4, and the surface 4a of the solder resist (insulating layer) 4. The thickness D3 of the silver paste (conductive adhesive) 12 up to the back surface 11b of the semiconductor chip 11 is
D2 ≦ D1 ≦ D3
It is preferable that

By setting the dimensional relationship in this way, the protrusion heights D2 of the plurality of conductive bumps 6 can be made as close as possible to each other, and thereby the height of the semiconductor chip 11 can be increased from the surface 4a of the solder resist (insulating layer) 4. The separation distance D3 to the back surface 11b is too close to each other, and when the silver paste (conductive adhesive) 12 is applied between the top 6a of the conductive bump 6 and the back surface 11b of the semiconductor chip 11, the granular material Problems such as being pushed out can be avoided. Further, the top portion 6a of the conductive bump 6 and the back surface 11b of the semiconductor chip 11 are not too far apart, and the conductive performance, that is, the stability of the GND voltage at the semiconductor chip 11 is not impaired.

In the method for manufacturing the semiconductor device 10 according to this embodiment, a silver paste (conductive adhesive) 12 is applied to the surface 1a of the package substrate 1. Thereafter, after mounting the semiconductor chip 11 on the package substrate 1, heat treatment is performed to bond the back surface 1b of the semiconductor chip 11 and the front surface 1a of the package substrate 1 with a silver paste (conductive adhesive) 12. As a result, the semiconductor chip 11 is set in a fixed (attached) state on the surface of the package substrate 1, and the conductive bumps 6, which are electrodes on the package substrate 1 and which apply a bias to the back surface 11b of the semiconductor chip 11, are set. The back surface 1b of the semiconductor chip 11 is electrically connected using a silver paste (conductive adhesive) 12.

Thereafter, using a wire bonding device, bonding pads other than the surface 11a and external electrode pads in the bonding area 1D of the package substrate 1 are connected as external electrodes on the semiconductor chip 11 using gold wire, aluminum wire, etc. Electrical connection is made using bonding wires 13. Further, the semiconductor chip 11 and bonding wires 13 are sealed with a transfer mold 14.

According to the semiconductor device 10 according to the present embodiment, since the conductive bumps 6 are formed to protrude from the surface 4a of the solder resist (insulating layer) 4, the conductive bumps 6 and the silver paste (conductive adhesive) 12 The area of the electrically conductive connection between the opening 41 and the upper surface 3a1 is larger than the area of the upper surface 3a1 exposed inside the opening 41. This ensures the necessary contact area between the conductive bumps 6 and the silver paste (conductive adhesive) 12, and ensures stability of the GND voltage in the operation of the semiconductor chip 11, which is a device that responds at high voltage and high speed. As a result, it is possible to reduce the occurrence of defects in electrical characteristics during device operation.

This makes it possible to improve the stability of the GND level without increasing the area of the opening 41, that is, the area of the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a exposed in the opening 41.

At the same time, since the area of the opening 41, that is, the area of the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a exposed in the opening 41 does not change, the solder resist (insulating layer) 4 in the chip area (chip area) 1C does not change. The area of the surface 4a also does not change. Therefore, the adhesion with the solder resist (insulating layer) 4 is not reduced. This can prevent peeling from occurring due to stress such as application of a load.

That is, in the semiconductor device 10 according to the present embodiment, it is possible to simultaneously improve GND level stability and improve operational stability due to the occurrence of delamination.

Hereinafter, a second embodiment of a package substrate and a semiconductor device according to the present invention will be described based on the drawings.
FIG. 4 is a cross-sectional view showing a semiconductor device according to this embodiment. This embodiment differs from the above-described first embodiment in that it relates to a backside metal layer, and is different from the above-mentioned first embodiment. Components corresponding to the configurations are given the same reference numerals and their explanations will be omitted.

In the semiconductor device 10 according to this embodiment, as shown in FIG. 4, a backside metal layer 15 is formed on the back surface 11b of the semiconductor chip 11. The backside metal layer 15 is made of a predetermined metal and covers the entire back surface 11b of the semiconductor chip 11.
In the semiconductor device 10 according to this embodiment, by forming the backside metal layer 15, conductivity between the semiconductor chip 11 and the package substrate 1 can be improved.

Note that when forming the backside metal layer 15, it is also possible to reduce the thickness D3 of the silver paste (conductive adhesive) 12 in accordance with the thickness of the backside metal layer 15. Alternatively, when forming the backside metal layer 15, the thickness D3 of the silver paste (conductive adhesive) 12 may be set to the above-mentioned relationship without taking the thickness of the backside metal layer 15 into consideration. is also possible.

In this embodiment, effects equivalent to those of the above-described embodiment can be achieved.

An example of implementation according to the present invention will be described below.

In the semiconductor device of the present invention, its dimensions can be set as follows.
Opening 41 diameter dimension; φ0.25mm
Number of openings 41 in chip area (chip area) 1C: Approximately 130 Area of chip area (chip area) 1C excluding openings 41: 160 mm ²
Thickness D1 of solder resist (insulating layer) 4: 30 μm
Opening 41 depth D1; 30 μm
Thickness D3 of silver paste (conductive adhesive) 12: 40 μm
Projection height D2 of the top portion 6a of the conductive bump 6 from the surface 4a of the solder resist (insulating layer) 4: 20 μm
Conductive bump 6; gold ball

The GND level stability and the occurrence of delamination were compared between the semiconductor device of the present invention as described above and a semiconductor device having the same configuration except that the conductive bumps 6 were not formed. As a result, it was found that in the semiconductor device of the present invention in which the conductive bumps 6 were formed, the GND level stability was improved and the occurrence of delamination was significantly suppressed.
Note that the height (D1+D2) from the top surface 3a1 of the upper connection wiring layer (wiring layer) 3a to the top 6a of the conductive bump 6 is the height (D1+D2) from the top surface 3a1 of the upper connection wiring layer (wiring layer) 3a to the back surface of the semiconductor chip 11. It has been found that it is preferable to set the distance to 11b to about 2/3 or 5/7 of the distance (D1+D3).

1...Package substrate 1a...Front surface 1b...Back surface 1C...Chip area (chip area)
1D...Bonding area (bonding area)
2...Solder ball (ball)
2... Solder ball 3... Wiring layer 3a... Upper connection wiring layer (wiring layer)
3a1...Top surface 3b...Lower connection wiring layer (wiring layer)
4...Solder resist (insulating layer)
4a...Front surface 41...Opening 5...Insulating layer 5a...Opening 6...Conductive bump 6a...Top 6b...Lower end 10...Semiconductor device 10b...Back surface 11...Semiconductor chip 11b...Back surface 12...Silver paste (conductive adhesive)
13... Bonding wire 14... Transfer mold 15... Back side metal layer

Claims (7)

A package substrate on which a semiconductor chip with a back surface at a predetermined potential is fixed to a surface opposite to the back surface,
a wiring layer having the predetermined potential;
an insulating layer that is laminated on the upper surface of the wiring layer and has a plurality of openings that expose parts of the wiring layer at positions facing the back surface of the semiconductor chip;
a plurality of conductive bumps provided on the upper surface of the wiring layer each exposed from the opening and having a top portion closer to the back surface of the semiconductor chip than the front surface of the insulating layer;
has,
A package substrate characterized by: In the thickness direction, a height at which the top of the conductive bump protrudes from the front surface of the insulating layer toward the back surface of the semiconductor chip is smaller than the depth of the opening.
The package substrate according to claim 1, characterized in that: The outline of the conductive bump in plan view is smaller than or the same as the outline of the opening formed in the insulating layer.
The package substrate according to claim 1, characterized in that: The package substrate of claim 1, wherein the conductive bumps are selected from gold balls, solder balls, and copper pillars. A package substrate according to any one of claims 1 to 4,
the semiconductor chip;
a conductive adhesive that fixes the back surface of the semiconductor chip, the top of the conductive bump and the surface of the insulating layer;
has,
A semiconductor device characterized by: In the thickness direction, the distance between the back surface of the semiconductor chip and the front surface of the insulating layer is greater than or equal to the thickness of the insulating layer;
6. The semiconductor device according to claim 5. a backside metal layer is formed on the backside of the semiconductor chip;
7. The semiconductor device according to claim 6.

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