JPH11163197A - Semiconductor mounting board - Google Patents

Semiconductor mounting board

Info

Publication number
JPH11163197A
JPH11163197A JP32507397A JP32507397A JPH11163197A JP H11163197 A JPH11163197 A JP H11163197A JP 32507397 A JP32507397 A JP 32507397A JP 32507397 A JP32507397 A JP 32507397A JP H11163197 A JPH11163197 A JP H11163197A
Authority
JP
Japan
Prior art keywords
substrate
electrode
edge
semiconductor
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32507397A
Other languages
Japanese (ja)
Inventor
Isao Hirata
勲夫 平田
Takeshi Kano
武司 加納
Hideo Nakanishi
秀雄 中西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP32507397A priority Critical patent/JPH11163197A/en
Publication of JPH11163197A publication Critical patent/JPH11163197A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0284Details of three-dimensional rigid printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3442Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor mounting board which can be mounted on a motherboard, improved in electrical reliability, and improved in connection reliability when it is mounted on the motherboard. SOLUTION: A recess 11 is provided to the rear center of an insulating board 10. An edge electrode 13 is provided to each edge face of the insulating board 10 spreading in the thickness direction of the board 10, surface circuits 14 each connected to the edge electrodes 13 are provided to the surface of the board 10 extending from the edges toward center of the board 10, and back electrodes 15 each of which connected to the edge electrodes 13 are formed on the rear of the board 10. A resist 5 is provided to the surface of the insulating board 10 for covering the surface of the surface circuits 14 with the center and edges of the board 10 left exposed. The length A of an exposed part between the end of the resist 5 and the edge of the board 10 is set larger than a length B of the back electrode 15, which extends from the edge of the board to its other edge.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ICチップなどの
半導体素子を搭載するのに使用される半導体実装用基板
に関し、詳しくは、半導体素子を実装した状態でマザー
ボード上に複数積載して実装することができる半導体実
装用基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting substrate used for mounting a semiconductor element such as an IC chip, and more particularly, to mounting a plurality of semiconductor elements mounted on a motherboard in a state where the semiconductor elements are mounted. The present invention relates to a semiconductor mounting substrate that can be used.

【0002】[0002]

【従来の技術】従来から、ICチップなどの半導体素子
を搭載し、さらに樹脂封止した後、マザーボード上に実
装して使用するための半導体実装用基板として、各種タ
イプのパッケージが広く用いられている。その一種とし
て、基板の周端面に外部に露出する端面電極を有し、こ
の端面電極を介してマザーボード上の回路と導通が図ら
れる構成を有するLCC(leadless chip
carrier)(他にQFN(quad flat
non−leaded package)とも呼ばれ
る)などのパッケージが知られている。
2. Description of the Related Art Conventionally, various types of packages have been widely used as a semiconductor mounting substrate for mounting a semiconductor element such as an IC chip, sealing it with a resin, and mounting it on a motherboard for use. I have. As one type, an LCC (leadless chip) having a configuration in which an end surface electrode exposed to the outside is provided on the peripheral end surface of the substrate, and conduction with a circuit on a motherboard is achieved through the end surface electrode.
carrier) (QFN (quad flat)
Packages (also referred to as non-leaded packages) are known.

【0003】[0003]

【発明が解決しようとする課題】ところで近年、マザー
ボード上に実装される電子部品の高密度化にともない、
半導体の高集積化に対する需要が高まってきている。
In recent years, with the increase in the density of electronic components mounted on a motherboard,
Demand for high integration of semiconductors is increasing.

【0004】本願出願人は、このような需要に応えるべ
く、パッケージ自体の取り扱いが比較的容易であり且つ
実装信頼性が高いLCCに注目し、1997年6月13
日に出願された特願平9−157189号に記載の発明
(以下、先行発明とする)おいて、高集積化が可能な半
導体実装用基板(LCC)を提案しており、本発明はこ
の先行発明を契機としてなされたものである。
[0004] In order to meet such demands, the applicant of the present application has paid attention to an LCC whose package itself is relatively easy to handle and has high mounting reliability.
In the invention described in Japanese Patent Application No. Hei 9-157189 (hereinafter referred to as the prior invention) filed on Nov. 5, the present invention proposes a semiconductor mounting substrate (LCC) capable of high integration. It was made with the prior invention as an opportunity.

【0005】本発明の大きな目的は、上記先行発明と同
様に、半導体素子を搭載するためのパッケージであっ
て、マザーボード上に積載して実装できる半導体実装用
基板を提供することにある。さらに本発明は、上記の目
的に加え、電気信頼性の向上を図ると共にマザーボード
上に積載して実装する際の接続信頼性を向上させた半導
体実装用基板を提供することにある。
It is a major object of the present invention to provide a package for mounting a semiconductor element, which is a package for mounting a semiconductor element, which can be mounted on a motherboard and mounted thereon, similarly to the above-mentioned prior invention. It is still another object of the present invention to provide a semiconductor mounting substrate which has improved electrical reliability and improved connection reliability when mounted and mounted on a motherboard in addition to the above objects.

【0006】[0006]

【課題を解決するための手段】本発明に係る半導体実装
用基板は、上記目的を達するために以下の必須構成を有
する。即ち、相対向する表裏面を有する絶縁基板を備え
ており、この絶縁基板の裏面中央部には凹部が形成され
ている。この絶縁基板において、その周端面には外部に
露出する端面電極が基板厚み方向に跨るように形成さ
れ、その表面には上記端面電極に導通して基板縁部から
中央部に向かって延びる表面回路が形成され、一方、そ
の裏面には上記端面回路と通じる裏面電極が形成されて
いる。さらに、上記絶縁基板の表面にはレジストが設け
られていて、上記表面回路における基板中央側および基
板端部側の部分を露出部分として残して上記レジストに
より表面回路の表面が被覆されている。そして該表面回
路の上記露出部分のうち、基板中央側の露出部分は半導
体素子と接続するための半導体接続用電極とされ、基板
表面の端部側は当該半導体実装用基板を積載して実装す
るときに上位に載置された半導体実装用基板の裏面電極
と接続するための上部積載用電極とされる。そして上記
上部積載用電極における上記レジストの端から基板端縁
までの寸法は、上記裏面電極における基板端縁から基板
中央側の端までの寸法よりも大きくなっている。
A semiconductor mounting substrate according to the present invention has the following essential components to achieve the above object. That is, an insulating substrate having opposite front and back surfaces is provided, and a concave portion is formed at the center of the back surface of the insulating substrate. In this insulating substrate, an end surface electrode exposed to the outside is formed on the peripheral end surface so as to straddle in the thickness direction of the substrate, and a surface circuit extending on the surface from the edge portion of the substrate toward the center portion in conduction with the end surface electrode. On the other hand, on the back surface, a back surface electrode communicating with the end surface circuit is formed. Further, a resist is provided on the surface of the insulating substrate, and the surface of the surface circuit is covered with the resist except for portions of the surface circuit on the substrate center side and the substrate end side as exposed portions. Of the exposed portions of the surface circuit, the exposed portion on the center side of the substrate is used as a semiconductor connection electrode for connecting to a semiconductor element, and the end portion of the substrate surface is mounted with the semiconductor mounting substrate mounted thereon. It is sometimes used as an upper mounting electrode for connecting to a back surface electrode of a semiconductor mounting substrate mounted on an upper layer. The dimension of the upper stacking electrode from the edge of the resist to the edge of the substrate is larger than the dimension of the back electrode from the edge of the substrate to the edge of the center of the substrate.

【0007】当該半導体実装用基板において、半導体素
子を搭載する手法としては次に示すように上記凹部内ま
たは基板表面中央部に搭載する二通りがある。上記凹部
内に半導体素子を搭載する場合、上記絶縁基板において
上記凹部底面と基板表面中央部とに開口する貫通孔を形
成するとよく、搭載すべき半導体素子の一主表面を上記
凹部底面に固定して、上記貫通孔を通じて上記半導体素
子と基板表面の上記半導体接続用電極とを結線し接続す
るとよい。一方、上記絶縁基板の表面中央部に半導体素
子を搭載する場合、上記絶縁基板表面の中央部に半導体
素子を搭載するための部位を設けて、その部位の周囲近
傍に上記表面回路の中央側端部を配置するとよく、この
とき上記絶縁基板表面の中央部に半導体素子を載置する
とともに該半導体素子と基板表面の上記半導体接続用電
極とを結線し接続するとよい。
In the semiconductor mounting substrate, there are two methods for mounting a semiconductor element, as described below, by mounting the semiconductor element in the recess or in the center of the substrate surface. When a semiconductor element is mounted in the recess, it is preferable to form a through hole that opens in the insulating substrate at the bottom of the recess and at the center of the surface of the substrate. One main surface of the semiconductor element to be mounted is fixed to the bottom of the recess. Preferably, the semiconductor element and the semiconductor connection electrode on the substrate surface are connected and connected through the through hole. On the other hand, when the semiconductor element is mounted at the center of the surface of the insulating substrate, a portion for mounting the semiconductor element is provided at the center of the surface of the insulating substrate, and the center of the surface circuit is provided near the periphery of the portion. In this case, it is preferable to place a semiconductor element in the center of the surface of the insulating substrate and to connect and connect the semiconductor element and the electrode for semiconductor connection on the surface of the substrate.

【0008】上記のように半導体素子が搭載された当該
半導体実装用基板は、マザーボード上の所定位置に載置
し、上記端面電極をマザーボード上に形成された回路と
一致させて半田接合することによりマザーボード上に実
装されるものであり、さらに次のようにして複数積載す
ることができる。すなわち、マザーボード上に実装され
た下位の半導体実装用基板の上に上位の半導体実装用基
板を載せて、下位の半導体実装用基板の上記上部積載用
電極上に上位の半導体実装用基板の裏面電極を一致さ
せ、これらを半田接合することで上下の導通を図るとと
もに上位の半導体実装用基板が固定される。このとき本
発明の半導体実装用基板においては、上記凹部が該半導
体実装用基板に搭載された半導体素子を収容する役割を
果たすため、当該半導体実装用基板の上下積載が容易に
行えるものとなる。例えば上述した2通りの半導体素子
の搭載方法において、例えば半導体素子が該半導体実装
用基板の凹部内に搭載される場合には当該半導体素子が
該半導体実装用基板から突き出ることがないため該半導
体実装用基板を上下積載でき、一方、半導体素子が半導
体実装用基板の表面中央部に搭載される場合には、下位
の半導体実装用基板に搭載された半導体素子は上位の半
導体実装用基板の凹部内に収容されるため、該半導体実
装用基板を上下積載できる。
The semiconductor mounting board on which the semiconductor elements are mounted as described above is placed at a predetermined position on the motherboard, and the end face electrodes are soldered in accordance with the circuit formed on the motherboard. It is mounted on a motherboard, and can be stacked in a plurality as follows. That is, the upper semiconductor mounting substrate is mounted on the lower semiconductor mounting substrate mounted on the motherboard, and the lower electrode of the upper semiconductor mounting substrate is placed on the upper mounting electrode of the lower semiconductor mounting substrate. By connecting them by soldering, vertical conduction is achieved and the upper semiconductor mounting substrate is fixed. At this time, in the semiconductor mounting substrate of the present invention, since the concave portion plays a role of accommodating the semiconductor element mounted on the semiconductor mounting substrate, the semiconductor mounting substrate can be easily stacked vertically. For example, in the above two mounting methods of the semiconductor element, for example, when the semiconductor element is mounted in the concave portion of the semiconductor mounting substrate, the semiconductor element does not protrude from the semiconductor mounting substrate. When the semiconductor element is mounted on the center of the surface of the semiconductor mounting board, the semiconductor element mounted on the lower semiconductor mounting board is placed in the recess of the upper semiconductor mounting board. The semiconductor mounting substrate can be vertically stacked.

【0009】本発明の半導体実装用基板においては、上
記絶縁基板の表面に設けられた上記レジストが表面回路
を保護する役割を果たして高い電気信頼性が得られるも
のであり、また搭載された半導体素子との結線接続時に
おける半田ブリッジ等による表面回路のショートも防止
できる。さらに本発明においては、該半導体実装用基板
の上下積載時に良好な上下導通を行えるようにするため
に、このレジストにより被覆されない上記表面回路の基
板端部側の露出部分、すなわち上記上部搭載用電極にお
いて、上記レジストの端から基板端縁までの寸法が上記
裏面電極における基板端縁から基板中央側の端までの寸
法よりも大きくされている。これにより、当該半導体実
装用基板の上下積載時に、下位の半導体実装用基板の上
記上部積載用電極と上位の半導体実装用基板の上記裏面
電極との間に上記レジストの層が介在することなくこれ
らを半田接合できるため、比較的少ない量の半田で良好
な半田接合が行える。つまり、半田接合される上記裏面
電極と上記上部積載用電極との間に上記レジストの層が
介在する場合、該レジストの厚みの分、上下電極間に隙
間を生じるため、接合に使用する半田の量が少ないと上
記隙間を充填できず接続不良や接合不良を来す恐れがあ
り、逆に半田の量を増やして上記隙間よりも半田接合層
を厚くすると上下電極の接合および接続は行えるもの
の、半田が不要な場所に流れて隣り合う上記表面回路間
や上記端面電極間で半田ブリッジによりショートする恐
れがあるが、本発明の半導体実装用基板ではそのような
懸念がないものとなる。
In the semiconductor mounting substrate according to the present invention, the resist provided on the surface of the insulating substrate serves to protect a surface circuit, and high electrical reliability is obtained. The short circuit of the surface circuit due to the solder bridge or the like at the time of the connection connection with the above can be prevented. Further, in the present invention, in order to enable good vertical conduction during vertical mounting of the semiconductor mounting substrate, an exposed portion of the surface circuit on the side of the substrate end which is not covered with the resist, that is, the upper mounting electrode Wherein the dimension from the edge of the resist to the edge of the substrate is larger than the dimension of the back electrode from the edge of the substrate to the edge of the substrate on the center side. Thus, when the semiconductor mounting substrate is vertically stacked, the resist layer is not interposed between the upper mounting electrode of the lower semiconductor mounting substrate and the back surface electrode of the upper semiconductor mounting substrate. Therefore, good soldering can be performed with a relatively small amount of solder. That is, when the resist layer is interposed between the back electrode and the upper stacking electrode to be solder-bonded, a gap is generated between the upper and lower electrodes by the thickness of the resist. If the amount is small, the gap cannot be filled and connection failure or bonding failure may occur.On the contrary, if the amount of solder is increased and the solder bonding layer is made thicker than the gap, bonding and connection of the upper and lower electrodes can be performed, Although there is a possibility that the solder flows to an unnecessary place to cause a short circuit between the adjacent surface circuits or the end face electrodes due to a solder bridge, the semiconductor mounting substrate of the present invention does not have such a concern.

【0010】本発明において、上記上部積載用電極にお
ける上記レジストの端から基板端縁までの露出寸法と、
上記裏面電極における基板端縁から基板中央側の端まで
の寸法との差は100〜200μmの範囲にするとよ
い。上記上部積載用電極と上記裏面電極の寸法差をこの
ような範囲とすることで、上記レジストのパターン形成
時における露光等の位置合わせの誤差を考慮しても、上
記レジストより露出した上記上部搭載用電極の長さが上
記裏面電極の長さよりも大きくなることはなく、また上
記上部搭載用電極の大きさを最小限にして上記表面回路
上を十分多く被覆できるため、高い電気信頼性を確保で
きる。
In the present invention, an exposure dimension from an end of the resist to an edge of the substrate in the upper stacking electrode;
The difference between the dimension of the back electrode from the edge of the substrate to the edge of the center of the substrate is preferably in the range of 100 to 200 μm. By setting the dimensional difference between the upper mounting electrode and the back electrode in such a range, the upper mounting exposed from the resist can be taken into account even when a positioning error such as exposure during pattern formation of the resist is considered. Since the length of the electrode for use does not become longer than the length of the back electrode, the size of the upper mounting electrode can be minimized, and the surface circuit can be sufficiently covered to ensure high electrical reliability. it can.

【0011】[0011]

【発明の実施の形態】以下、本発明の実施形態について
説明する。
Embodiments of the present invention will be described below.

【0012】図1は、本発明の一実施形態に係る半導体
実装用基板1を示す断面図である。半導体実装用基板1
は、相対向する表裏面を有する矩形の絶縁基板10を備
えており、この絶縁基板10の裏面中央部には矩形の凹
部11が形成されている。この凹部10の開口の大きさ
は実装すべき半導体素子2(後述する)の外寸よりも大
きく、且つ該凹部11の深さは半導体素子2の厚みより
も大きく形成されている。
FIG. 1 is a sectional view showing a semiconductor mounting substrate 1 according to one embodiment of the present invention. Semiconductor mounting board 1
Is provided with a rectangular insulating substrate 10 having front and rear surfaces facing each other, and a rectangular concave portion 11 is formed at the center of the rear surface of the insulating substrate 10. The size of the opening of the recess 10 is larger than the outer dimension of the semiconductor element 2 (to be described later) to be mounted, and the depth of the recess 11 is larger than the thickness of the semiconductor element 2.

【0013】また、絶縁基板10において、凹部11の
底面中央部と基板表面の中央部に開口する、凹部11の
開口部よりも開口面積が小さい矩形の貫通孔12が形成
されている。この貫通孔12の大きさは実装すべき半導
体素子2の大きさよりも小さく形成されている。
In the insulating substrate 10, a rectangular through hole 12 having a smaller opening area than the opening of the recess 11 is formed at the center of the bottom surface of the recess 11 and at the center of the substrate surface. The size of the through hole 12 is smaller than the size of the semiconductor element 2 to be mounted.

【0014】図2に示すように、絶縁基板10の周端面
には基板厚み方向に跨る窪みが周方向に複数形成されて
いて、それら窪みの内面には外部に露出する端面電極1
3が基板厚み方向に跨るように形成されている。絶縁基
板10の表面には端面電極13に導通して基板縁縁にて
導通し、そこから貫通孔12の開口部近傍に向かって延
びる表面回路14が各端面電極13に対応して複数放射
状に形成されている。一方、絶縁基板10の裏面には端
面回路13と通じる裏面電極15が各端面電極13に対
応して凹部11の開口部の周囲を囲むように複数形成さ
れている。これら電極や回路は通常、銅により形成され
ており、所望によりその上にニッケル皮膜および金皮膜
などをめっき法などにより適宜形成することもできる。
As shown in FIG. 2, a plurality of depressions extending in the thickness direction of the substrate are formed on the peripheral end surface of the insulating substrate 10, and the end surface electrodes 1 exposed to the outside are formed on the inner surfaces of the depressions.
3 is formed so as to straddle in the thickness direction of the substrate. The surface of the insulating substrate 10 is electrically connected to the end face electrode 13 and is electrically connected to the edge of the substrate. Is formed. On the other hand, on the back surface of the insulating substrate 10, a plurality of back surface electrodes 15 communicating with the end surface circuits 13 are formed so as to surround the periphery of the opening of the concave portion 11 corresponding to each end surface electrode 13. These electrodes and circuits are usually formed of copper, and if desired, a nickel film, a gold film, and the like can be appropriately formed thereon by a plating method or the like.

【0015】絶縁基板13の表面にはメッキレジストな
いしはソルダーレジストとしての目的でレジスト5が設
けられている。このレジスト5としては、フォトレジス
トや熱硬化型レジストなどが使用できる。このレジスト
5は、表面回路14における基板中央側および基板端部
側の部分を露出部分として残すようにして表面回路14
の中間部分を被覆している。ここで、表面回路14の上
記露出部分のうち、基板中央側の露出部分は図3に示す
如く当該半導体実装用基板1に半導体素子2を実装する
ときに該半導体素子2と接続するための半導体接続用電
極14bとなり、基板表面の端部側は当該半導体実装用
基板1を図4の如く積載実装するときに上位に載置され
た半導体実装用基板1の裏面電極と接続するための上部
積載用電極14aとなる。この上部積載用電極14aに
おけるレジスト5の端から基板端縁までの寸法Aは、裏
面電極15における基板端縁から基板中央側の端までの
寸法Bよりも大きくなっている。このとき、レジスト5
を形成するにあたっては、露光などによるレジスト5の
パターン形成時の位置合わせの誤差を考慮しても上記寸
法関係が確保できるようにするために、寸法Aの大きさ
が寸法Bの大きさより100〜200μm長くなるよう
にするのが好ましい。
A resist 5 is provided on the surface of the insulating substrate 13 to serve as a plating resist or a solder resist. As the resist 5, a photoresist, a thermosetting resist, or the like can be used. The resist 5 is formed by leaving the portions of the surface circuit 14 on the substrate center side and the substrate end side as exposed portions.
Is covered. Here, of the exposed portions of the surface circuit 14, the exposed portion on the center side of the substrate is a semiconductor for connecting to the semiconductor element 2 when the semiconductor element 2 is mounted on the semiconductor mounting substrate 1 as shown in FIG. The connection electrode 14b serves as an upper mounting portion for connecting to the back surface electrode of the semiconductor mounting substrate 1 placed on the upper side when the semiconductor mounting substrate 1 is mounted and mounted as shown in FIG. Electrode 14a. The dimension A of the upper stacking electrode 14a from the edge of the resist 5 to the substrate edge is larger than the dimension B of the back electrode 15 from the substrate edge to the substrate center end. At this time, resist 5
In order to ensure the above dimensional relationship even when considering the alignment error when forming the pattern of the resist 5 by exposure or the like, the size of the dimension A is 100 to 100 times larger than the size of the dimension B. It is preferable to make the length longer by 200 μm.

【0016】当該半導体実装用基板1の製造は例えば次
のような方法で行うことができる。まず、少なくとも絶
縁基板13よりも大きな母基板を準備し、この母基板に
おいて絶縁基板13の外周端辺に相当する位置にスルー
ホールを複数穿孔する。次に無電解メッキや電解メッキ
等の手法により上記スルホールの内周面にメッキを施す
とともに、母基板の表裏両面にメッキを施して表面回路
14および裏面電極15を形成する。そして母基板の表
面にレジスト5を塗布し、表面回路14のうち半導体接
続用電極14bおよび上部搭載用電極14aが露出する
ようにパターニングしてレジスト5を硬化させる。この
とき、このレジスト5の形成は、初めからパターニング
した形でレジスト5を塗布し、そのまま硬化させてもよ
く、あるいはレジスト5を全面塗布し、これを所定のパ
ターンに硬化させた後、未硬化部分を除去するようにし
てもよい。次に上記母基板は、絶縁基板10となる位置
の裏面側中央部に凹部11を座ぐり加工等により形成す
るとともに、該凹部11の底面から基板表面側に貫通孔
を形成する。そして、上記母基板を、絶縁基板10の外
周端辺に相当する位置にて上記スルホールが略半分に裁
断されるように金型打ち抜き等の手法により切断して絶
縁基板10を切り出すことにより、当該半導体実装用基
板1が得られる。なお、以上の製造方法は半導体実装用
基板1を製造する一例であって、本発明では上記工程の
実施手順を適宜入れ替えることも可能であり、また、全
く異なる工程から成る製法を採用することも可能であ
る。
The manufacture of the semiconductor mounting substrate 1 can be performed, for example, by the following method. First, a mother substrate larger than at least the insulating substrate 13 is prepared, and a plurality of through holes are formed in the mother substrate at positions corresponding to the outer peripheral edges of the insulating substrate 13. Next, plating is applied to the inner peripheral surface of the through hole by a method such as electroless plating or electrolytic plating, and plating is applied to both the front and back surfaces of the mother substrate to form the front surface circuit 14 and the back surface electrode 15. Then, a resist 5 is applied to the surface of the mother substrate, and the resist 5 is cured by patterning so that the semiconductor connection electrode 14b and the upper mounting electrode 14a of the surface circuit 14 are exposed. At this time, the resist 5 may be formed by applying the resist 5 in a patterned form from the beginning and curing the resist 5 as it is, or after applying the resist 5 on the entire surface and curing it to a predetermined pattern, You may make it remove a part. Next, in the mother substrate, a concave portion 11 is formed at the center of the rear surface side at a position to be the insulating substrate 10 by spot facing or the like, and a through hole is formed from the bottom surface of the concave portion 11 to the substrate surface side. Then, the mother substrate is cut by a method such as die punching so that the through hole is cut into approximately half at a position corresponding to the outer peripheral edge of the insulating substrate 10, and the insulating substrate 10 is cut out. The semiconductor mounting substrate 1 is obtained. Note that the above-described manufacturing method is an example of manufacturing the semiconductor mounting substrate 1, and in the present invention, it is possible to appropriately change the execution procedure of the above steps, or to adopt a manufacturing method including completely different steps. It is possible.

【0017】図3は半導体実装用基板1に対する半導体
素子2の実装例を示している。該実施形態において、半
導体実装用基板1に対し半導体素子2は図3に示す如く
実装される。まず半導体素子2としては、凹部11の開
口寸法よりも小さく且つ貫通孔12よりも大きい外寸お
よび凹部11の深さよりも小さい厚みを有し、一主表面
の中央部に電極パッド21を備えたものが使用される。
この半導体素子2は、その一主表面を、電極パッド21
の位置が貫通孔12に一致するようにして、凹部11の
底面に接着層3を介して固定し、さらに貫通孔12を通
じてボンディングワイヤー4により電極パッド21と半
導体接続用電極14bとを接続することで、半導体実装
用基板1の凹部11内に搭載される。このとき、ボンデ
ィングワイヤー4は半導体接続用電極14bに半田接合
されるが、このとき絶縁基板10の表面にはレジスト5
が設けられているので、隣りあう半導体接続用電極14
b、14b同士が半田ブリッジによるショートを起こす
のが防止される。さらに、上記のように半導体素子2を
搭載した半導体実装用基板1には、少なくともボンディ
ングワイヤー4による絶続部分を封止するために、貫通
孔12内と外貫通孔12の表面側開口部の周辺部が封止
材6により樹脂封止される。
FIG. 3 shows an example of mounting the semiconductor element 2 on the semiconductor mounting substrate 1. In this embodiment, the semiconductor element 2 is mounted on the semiconductor mounting substrate 1 as shown in FIG. First, the semiconductor element 2 has an outer dimension smaller than the opening dimension of the concave portion 11 and larger than the through hole 12 and a thickness smaller than the depth of the concave portion 11, and has an electrode pad 21 in a central portion of one main surface. Things are used.
The semiconductor element 2 has one main surface formed by an electrode pad 21.
Is fixed to the bottom surface of the concave portion 11 via the adhesive layer 3 so that the position of the electrode pad 21 coincides with the through hole 12, and the electrode pad 21 and the semiconductor connection electrode 14 b are connected by the bonding wire 4 through the through hole 12. Then, it is mounted in the recess 11 of the semiconductor mounting substrate 1. At this time, the bonding wire 4 is solder-bonded to the semiconductor connection electrode 14b.
Are provided, so that the adjacent semiconductor connection electrodes 14
Short circuit between b and 14b due to the solder bridge is prevented. Further, the semiconductor mounting substrate 1 on which the semiconductor element 2 is mounted as described above has at least a surface opening of the through hole 12 and the outer through hole 12 in order to seal at least a continuous portion by the bonding wire 4. The peripheral portion is resin-sealed by the sealing material 6.

【0018】図4はマザーボード9上への半導体実装用
基板1の実装例であり、図5はさらにその上に半導体実
装用基板1を積載し実装した例を示している。
FIG. 4 shows an example of mounting the semiconductor mounting substrate 1 on the motherboard 9, and FIG. 5 shows an example in which the semiconductor mounting substrate 1 is further mounted thereon and mounted.

【0019】上記のように半導体素子2が実装された半
導体実装用基板1は、図4に示す如く、マザーボード9
上の所定位置に載置し、端面電極13をマザーボード9
上に設けられた電極(図示せず)と一致させて半田7に
て接合することによりマザーボード9上に実装される。
さらに、図5のように、マザーボード9上に実装された
半導体実装用基板1の上には、もう1つの半導体実装用
基板1を載置して積み重ねることができ、この場合、半
田8により上位の半導体装置の裏面電極15と下位の半
導体装置の表面電極14とを接合することで上位の半導
体実装用基板1の固定および上下の接続がなされ、ま
た、下位の半導体実装用基板1表面上において硬化して
基板表面よりも上に盛り上がった封止材6の部分は、上
位の半導体実装用基板1の凹部11における半導体素子
2の下側の空間に収まるので、このような積載構造が可
能となっている。
As shown in FIG. 4, the semiconductor mounting substrate 1 on which the semiconductor element 2 is mounted is a motherboard 9 as shown in FIG.
On the motherboard 9.
It is mounted on the motherboard 9 by bonding with an electrode (not shown) provided thereon and using a solder 7.
Further, as shown in FIG. 5, another semiconductor mounting substrate 1 can be placed and stacked on the semiconductor mounting substrate 1 mounted on the motherboard 9. By bonding the back electrode 15 of the lower semiconductor device to the front electrode 14 of the lower semiconductor device, the upper semiconductor mounting substrate 1 is fixed and connected up and down. The portion of the sealing material 6 which has hardened and rises above the surface of the substrate is accommodated in the space below the semiconductor element 2 in the concave portion 11 of the upper semiconductor mounting substrate 1, so that such a stacked structure is possible. Has become.

【0020】また、該実施形態の半導体実装用基板1で
は、上部搭載用電極14aの寸法Aと裏面電極15の寸
法Bとの関係が、A>Bとなっていることにより、上記
積載構造において、上部搭載用電極14aと裏面電極1
5との良好な接続ないし接合が行えるようになってい
る。これについて、図6に示される、上記電極14a,
15の寸法関係をA<Bとした場合の半導体実装用基板
1の積載構造の例(比較例)との比較において説明す
る。まず、この比較例の積載構造では、上下に積載され
た半導体実装用基板1、1において、上部搭載用電極1
4aと裏面電極15との間にレジスト5の層が介在する
ことになる。この場合、レジスト5の厚みの分、上下の
電極14a,15間に隙間を生じる。これら電極14
a,15を半田接合する際、使用される半田8の量が少
ないと上記隙間を充填できず接続不良や接合不良を来す
恐れがあるため、上記隙間よりも半田8の層が厚くなる
ようにその量を増やす必要があるが、この場合、半田8
が不要な場所に流れて隣り合う表面回路14、14間や
端面電極13、13間で半田ブリッジによるショートす
る恐れを生じる。これに対し、A>Bとした該実施形態
に係る半導体実装用基板1では、半導体実装用基板1、
1の上下積載構造において、下位の半導体実装用基板1
の上部積載用電極14aと上位の半導体実装用基板1の
裏面電極15との間にレジスト5の層が介在することな
くこれらを半田接合できるため、比較的少ない量の半田
8で良好な半田接合が行える。従って、上記比較例のよ
うな不具合が該実施形態の半導体実装用基板1では防止
される。
In the semiconductor mounting substrate 1 of this embodiment, the relationship between the dimension A of the upper mounting electrode 14a and the dimension B of the back electrode 15 is A> B. , Upper mounting electrode 14a and back electrode 1
5 can be connected or joined well. In this regard, the electrodes 14a, 14a, shown in FIG.
A description will be given in comparison with an example (comparative example) of the mounting structure of the semiconductor mounting substrate 1 when the dimensional relationship of 15 is A <B. First, in the mounting structure of this comparative example, the upper mounting electrode 1 is mounted on the semiconductor mounting substrates 1 and 1 stacked vertically.
A layer of resist 5 is interposed between 4a and back electrode 15. In this case, a gap is generated between the upper and lower electrodes 14a and 15 by the thickness of the resist 5. These electrodes 14
When the solders a and 15 are solder-bonded, if the amount of the solder 8 used is small, the gap cannot be filled and a connection failure or a bonding failure may occur, so that the layer of the solder 8 is thicker than the gap. However, in this case, the solder 8
May flow to unnecessary places and cause a short circuit between the adjacent surface circuits 14 and 14 and between the end face electrodes 13 and 13 due to a solder bridge. On the other hand, in the semiconductor mounting substrate 1 according to the embodiment in which A> B, the semiconductor mounting substrate 1,
In the vertical stacking structure 1, the lower semiconductor mounting substrate 1
Can be soldered between the upper mounting electrode 14a and the back electrode 15 of the upper semiconductor mounting substrate 1 without the interposition of the resist 5 layer. Can be performed. Therefore, the disadvantages as in the comparative example are prevented in the semiconductor mounting substrate 1 of the embodiment.

【0021】[0021]

【発明の効果】以上説明したように、本発明に係る半導
体実装用基板は、当該半導体実装用基板に搭載された半
導体素子を凹部内に収めた状態で上下に積載した構造と
することが可能である。また、本発明の半導体実装用基
板は、上記絶縁基板の表面に設けられた上記レジストが
表面回路を保護する役割を果たすので高い電気信頼性が
得られるものであり、また搭載された半導体素子との結
線接続時における半田ブリッジ等による表面回路のショ
ートも防止できる。さらに本発明においては、レジスト
により被覆されない上記表面回路の基板端部側の露出部
分、すなわち上記上部搭載用電極において、上記レジス
トの端から基板端縁までの寸法が上記裏面電極における
基板端縁から基板中央側の端までの寸法よりも大きくさ
れているので、当該半導体実装用基板の上記積載構造に
おいて、下位の半導体実装用基板の上記上部積載用電極
と上位の半導体実装用基板の上記裏面電極との間に上記
レジストの層が介在することなくこれらを半田接合でき
るため、比較的少ない量の半田で良好な半田接合が行
え、その結果、接続不良や接合不良を来すのが防止さ
れ、また上記表面回路間や上記端面電極間で半田ブリッ
ジによるショートも防止される。
As described above, the substrate for mounting a semiconductor device according to the present invention can have a structure in which semiconductor elements mounted on the substrate for mounting a semiconductor device are stacked vertically while being accommodated in a recess. It is. In addition, the semiconductor mounting substrate of the present invention has high electrical reliability because the resist provided on the surface of the insulating substrate plays a role of protecting a surface circuit. The short circuit of the surface circuit due to the solder bridge or the like at the time of the connection connection can be prevented. Further, in the present invention, in the exposed portion on the substrate end side of the surface circuit that is not covered by the resist, that is, in the upper mounting electrode, the dimension from the edge of the resist to the substrate edge is from the substrate edge in the back electrode. Since the size is larger than the dimension up to the edge on the center side of the substrate, in the loading structure of the semiconductor mounting substrate, the upper loading electrode of the lower semiconductor mounting substrate and the lower electrode of the upper semiconductor mounting substrate Since these can be solder-bonded without interposing the above-mentioned resist layer between them, good solder bonding can be performed with a relatively small amount of solder, and as a result, poor connection or poor bonding is prevented, In addition, a short circuit due to a solder bridge between the surface circuits and between the end surface electrodes is prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第一実施形態に係る半導体実装用基板
を示す断面図である。
FIG. 1 is a sectional view showing a semiconductor mounting substrate according to a first embodiment of the present invention.

【図2】同上実施形態の半導体実装用基板において、レ
ジストを除いた状態の基板を示す部分斜視図である
FIG. 2 is a partial perspective view showing the substrate in a state where a resist is removed in the semiconductor mounting substrate of the embodiment.

【図3】同上実施形態の半導体実装用基板に半導体素子
を実装した状態を示す断面図である。
FIG. 3 is a cross-sectional view showing a state where a semiconductor element is mounted on the semiconductor mounting substrate of the embodiment.

【図4】図3に示す半導体実装用基板をマザーボード上
に実装した状態を示す断面図である。
4 is a cross-sectional view showing a state where the semiconductor mounting substrate shown in FIG. 3 is mounted on a motherboard.

【図5】図4に示す状態の半導体実装用基板の上にさら
に半導体実装用基板を積載して実装した状態を示す断面
図である。
FIG. 5 is a cross-sectional view showing a state in which the semiconductor mounting substrate is further stacked and mounted on the semiconductor mounting substrate in the state shown in FIG. 4;

【図6】図5に示す状態と比較するための比較例に係る
半導体実装用基板の積載状態を示す断面図である。
FIG. 6 is a cross-sectional view showing a stacked state of a semiconductor mounting substrate according to a comparative example for comparison with the state shown in FIG. 5;

【符号の説明】[Explanation of symbols]

1 半導体実装用基板 10 絶縁基板 11 凹部 12 貫通孔 13 端面電極 14 表面回路 14a 上部積載用電極 14b 半導体接続用電極 15 裏面電極 2 半導体素子 5 レジスト 8 半田 A 上部積載用電極の寸法 B 裏面電極の寸法 Reference Signs List 1 semiconductor mounting substrate 10 insulating substrate 11 concave portion 12 through hole 13 end surface electrode 14 surface circuit 14a upper mounting electrode 14b semiconductor connection electrode 15 back electrode 2 semiconductor element 5 resist 8 solder A size of upper mounting electrode B back electrode Size

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 相対向する表裏面を有する絶縁基板にお
いて、その裏面中央部に凹部を形成し、さらにこの絶縁
基板の周端面に外部に露出する端面電極を基板厚み方向
に跨るように形成するとともに、上記絶縁基板の表面に
上記端面電極に導通して基板縁部から中央部に向かって
延びる表面回路と、上記絶縁基板の裏面に上記端面回路
と通じる裏面電極とを形成し、さらに、上記絶縁基板の
表面にレジストを設けて上記表面回路の表面を被覆する
一方、該表面回路における基板中央側および基板端部側
に上記レジストにより被覆されない露出部分を設けて半
導体接続用電極および上部積載用電極を形成した構成を
有し、上記上部積載用電極における上記レジストの端か
ら基板端縁までの寸法を、上記裏面電極における基板端
縁から基板中央側の端までの寸法よりも大きくしたこと
を特徴とする半導体実装用基板。
1. An insulating substrate having opposite front and back surfaces, a concave portion is formed at the center of the rear surface, and an end surface electrode exposed to the outside is formed on a peripheral end surface of the insulating substrate so as to straddle in the thickness direction of the substrate. Along with the front surface circuit of the insulating substrate, a front surface circuit extending from the edge portion of the substrate toward the center portion and a back surface electrode communicating with the end surface circuit are formed on the back surface of the insulating substrate. A resist is provided on the surface of the insulating substrate to cover the surface of the surface circuit, and exposed portions not covered by the resist are provided on the center and side edges of the substrate in the surface circuit to provide a semiconductor connection electrode and an upper stacking portion. An electrode is formed, and the dimension from the edge of the resist to the edge of the substrate in the upper stacking electrode is set at the center of the substrate from the edge of the substrate in the back electrode. A substrate for mounting a semiconductor, characterized in that it has a size larger than an end.
【請求項2】 上記上部積載用電極における上記レジス
トの端から基板端縁までの露出寸法と、上記裏面電極に
おける基板端縁から基板中央側の端までの寸法との差
が、100〜200μmであることを特徴とする請求項
1記載の半導体実装用基板。
2. A difference between an exposed dimension of the upper stacking electrode from the edge of the resist to the edge of the substrate and a dimension of the back electrode from the edge of the substrate to the edge of the center of the substrate is 100 to 200 μm. The substrate for mounting a semiconductor according to claim 1, wherein:
JP32507397A 1997-11-26 1997-11-26 Semiconductor mounting board Pending JPH11163197A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32507397A JPH11163197A (en) 1997-11-26 1997-11-26 Semiconductor mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32507397A JPH11163197A (en) 1997-11-26 1997-11-26 Semiconductor mounting board

Publications (1)

Publication Number Publication Date
JPH11163197A true JPH11163197A (en) 1999-06-18

Family

ID=18172859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32507397A Pending JPH11163197A (en) 1997-11-26 1997-11-26 Semiconductor mounting board

Country Status (1)

Country Link
JP (1) JPH11163197A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7613010B2 (en) 2004-02-02 2009-11-03 Panasonic Corporation Stereoscopic electronic circuit device, and relay board and relay frame used therein
JP2010278480A (en) * 2010-09-14 2010-12-09 Rohm Co Ltd Semiconductor device
US8754535B2 (en) 2004-09-28 2014-06-17 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
EP3096592A4 (en) * 2014-01-14 2018-01-17 Taiyo Ink Mfg. Co., Ltd. Three-dimensional circuit board and solder resist composition used for same
US11842972B2 (en) 2004-09-28 2023-12-12 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7613010B2 (en) 2004-02-02 2009-11-03 Panasonic Corporation Stereoscopic electronic circuit device, and relay board and relay frame used therein
US8754535B2 (en) 2004-09-28 2014-06-17 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US9117774B2 (en) 2004-09-28 2015-08-25 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US9721865B2 (en) 2004-09-28 2017-08-01 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US9831204B2 (en) 2004-09-28 2017-11-28 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US10522494B2 (en) 2004-09-28 2019-12-31 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US10818628B2 (en) 2004-09-28 2020-10-27 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US11355462B2 (en) 2004-09-28 2022-06-07 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US11842972B2 (en) 2004-09-28 2023-12-12 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
JP2010278480A (en) * 2010-09-14 2010-12-09 Rohm Co Ltd Semiconductor device
EP3096592A4 (en) * 2014-01-14 2018-01-17 Taiyo Ink Mfg. Co., Ltd. Three-dimensional circuit board and solder resist composition used for same

Similar Documents

Publication Publication Date Title
US8222747B2 (en) Multilayer wiring substrate mounted with electronic component and method for manufacturing the same
US7993967B2 (en) Semiconductor package fabrication method
US6049125A (en) Semiconductor package with heat sink and method of fabrication
JP3189703B2 (en) Semiconductor device and manufacturing method thereof
US7923835B2 (en) Package, electronic device, substrate having a separation region and a wiring layers, and method for manufacturing
US6501160B1 (en) Semiconductor device and a method of manufacturing the same and a mount structure
US6716675B2 (en) Semiconductor device, method of manufacturing semiconductor device, lead frame, method of manufacturing lead frame, and method of manufacturing semiconductor device with lead frame
JPH11163197A (en) Semiconductor mounting board
JPH11163024A (en) Semiconductor device and lead frame for assembling the same, and manufacture of the device
JP2020129637A (en) Electronic device and manufacturing method thereof
JP2005109088A (en) Semiconductor device and its manufacturing method, circuit substrate, and electronic equipment
JP2936540B2 (en) Circuit board, method of manufacturing the same, and method of manufacturing semiconductor package using the same
JP3101043B2 (en) Plastic IC chip carrier and method of manufacturing the same
JP2000286378A (en) Resin sealed semiconductor device
JP3684517B2 (en) Semiconductor device
JP2669286B2 (en) Composite lead frame
JPH09246416A (en) Semiconductor device
JP3670636B2 (en) Electronic device with electronic components mounted
JP3196758B2 (en) Lead frame, method of manufacturing lead frame, semiconductor device, and method of manufacturing semiconductor device
KR100320447B1 (en) Method for Manufacturing Semiconductor Package
JPH06291246A (en) Multi-chip semiconductor device
JP3506788B2 (en) Semiconductor package
JPH1116947A (en) Semiconductor package and manufacture thereof
JPH07122701A (en) Semiconductor device, its manufacture, and lead frame for pga
JP2861984B2 (en) Semiconductor device and method of manufacturing the semiconductor device