JPH06291246A - Multi-chip semiconductor device - Google Patents
Multi-chip semiconductor deviceInfo
- Publication number
- JPH06291246A JPH06291246A JP5073230A JP7323093A JPH06291246A JP H06291246 A JPH06291246 A JP H06291246A JP 5073230 A JP5073230 A JP 5073230A JP 7323093 A JP7323093 A JP 7323093A JP H06291246 A JPH06291246 A JP H06291246A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- wiring board
- chip
- semiconductor device
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子部品搭載器に用い
られる半導体装置に係り、特に多層プリント配線板に集
積回路チップを高密度に実装することを目的とする。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used in an electronic component mounter, and more particularly to mounting an integrated circuit chip on a multilayer printed wiring board at a high density.
【０００２】[0002]
【従来の技術】従来、半導体装置は、電子機器の多機能
化、小型化により電子機器の中の組み込まれる電子部品
とそれを実装するための基板からなる半導体装置におい
て、基板の配線密度を高くしたり、あるいは、図７に示
すように、配線基板（１１）に凹部を設け、その凹部に
集積回路チップ（１７）を埋没した状態で搭載し、ワイ
ヤーボンディング（１２）することなより、部品実装後
のプリント配線板の全体の厚さを薄くする工夫をした半
導体装置がある。また、この半導体装置はチップの電極
とプリント配線板側の電極が略同一平面上にあるため、
ワイヤーの距離を短くできる利点がある。更に、上記方
法は、ベアチップを使用することにより、集積回路チッ
プを樹脂モールドしたパッケージと比較して実装するの
に必要な占有面積を小さくすることができるとう効果も
ある。2. Description of the Related Art Conventionally, a semiconductor device has a high wiring density of a substrate in a semiconductor device including an electronic component incorporated in the electronic device and a substrate for mounting the electronic component due to multifunctionalization and miniaturization of the electronic device. Alternatively, as shown in FIG. 7, the wiring board (11) is provided with a recessed portion, and the integrated circuit chip (17) is mounted in the recessed state in a buried state, and the wire bonding (12) is carried out. There is a semiconductor device that is devised to reduce the overall thickness of the printed wiring board after mounting. Further, in this semiconductor device, since the chip electrode and the electrode on the printed wiring board side are substantially on the same plane,
There is an advantage that the wire distance can be shortened. Further, the above method has an effect that the occupied area required for mounting the integrated circuit chip as compared with the resin-molded package can be reduced by using the bare chip.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記の半導体
装置では限られた実装面積を有効に使うには限界であ
り、本発明は、集積回路チップの実装密度を上げるため
に、基板表面の限られた面積上により多くの集積回路チ
ップを搭載可能にした半導体装置を提供するものであ
る。また、使用時には集積回路チップが熱を発生し、し
かも集積回路チップが複数搭載される場合、その発熱量
は相当になり、放熱されずにいると、チップ自体に良い
影響を与えないばかりか、集積回路チップの配線基板か
ら剥離、及びクラックの発生が起こる等の問題がある。However, in the above semiconductor device, there is a limit to effectively using a limited mounting area, and the present invention limits the surface area of the substrate in order to increase the mounting density of integrated circuit chips. The present invention provides a semiconductor device capable of mounting a larger number of integrated circuit chips on a given area. In addition, when the integrated circuit chip generates heat during use, and when a plurality of integrated circuit chips are mounted, the amount of heat generated by the integrated circuit chip becomes considerable, and if not dissipated, not only does the chip itself not be adversely affected. There are problems such as separation from the wiring board of the integrated circuit chip and occurrence of cracks.
【０００４】よって、本発明は、配線基板への集積回路
チップの実装密度をあげ、更に集積回路チップから発生
する熱の放熱効果が高い半導体装置を提供するものであ
る。Therefore, the present invention provides a semiconductor device which increases the mounting density of integrated circuit chips on a wiring board and has a high heat dissipation effect of heat generated from the integrated circuit chips.
【０００５】[0005]
【課題を解決するための手段】請求項１に記載の発明
は、複数の導体回路を有する多層プリント配線板に複数
の集積回路チップを実装して構成されるマルチチップ半
導体装置において、前記多層プリント配線板に、前記導
体回路のうち、内層の導体回路の一部を外部へ露出させ
る段付き凹部が形成され、その段付き凹部内に集積回路
チップが複数搭載され、前記集積回路チップの少なくと
も１つが、前記内層の導体回路と電気的に接続されてい
ることを特徴とするマルチチップ半導体装置であり、請
求項２に記載の発明は、前記複数の集積回路チップの少
なくとも１つが、リードフレーム上に搭載し樹脂モール
ドされた集積回路部品であることを特徴とする請求項１
に記載のマルチチップ半導体装置であり、請求項３に記
載の発明は、前記多層プリント配線板の少なくとも１層
が金属板であり、その金属板に少なくとも１つの集積回
路チップが直接実装されることを特徴とする請求項１及
び請求項２に記載のマルチチップ半導体装置である。According to a first aspect of the present invention, there is provided a multi-chip semiconductor device configured by mounting a plurality of integrated circuit chips on a multilayer printed wiring board having a plurality of conductor circuits. A stepped recess is formed on the wiring board to expose a part of the conductor circuit of the inner layer to the outside of the conductor circuit, and a plurality of integrated circuit chips are mounted in the stepped recess, and at least one of the integrated circuit chips is mounted. 3 is a multi-chip semiconductor device electrically connected to the conductor circuit of the inner layer, and the invention according to claim 2, wherein at least one of the plurality of integrated circuit chips is on a lead frame. 2. An integrated circuit component mounted on a substrate and molded with a resin.
The multi-chip semiconductor device according to claim 3, wherein the at least one layer of the multilayer printed wiring board is a metal plate, and at least one integrated circuit chip is directly mounted on the metal plate. The multi-chip semiconductor device according to claim 1 or 2.
【０００６】[0006]
【作用】このように、基板に凹部を設けて、集積回路チ
ップを基板表面に対して厚さ方向に２つ以上重ねるよう
に実装するので、基板表面の集積回路チップ実装に必要
な占有面積を狭くすることができるので、実装密度があ
がり、更に配線基板の金属層にチップを搭載することに
より放熱効果も向上する。As described above, since the recess is formed in the substrate and the integrated circuit chips are mounted so that two or more of them are stacked in the thickness direction with respect to the surface of the substrate, the occupied area required for mounting the integrated circuit chip on the surface of the substrate is reduced. Since it can be narrowed, the packaging density is increased, and the heat dissipation effect is also improved by mounting the chip on the metal layer of the wiring board.
【０００７】[0007]
【実施例】図１から図３は本発明の実施例を示すもので
あり、図４から図６は他の実施例を示すものである。図
１には本発明にかかる半導体装置の断面図が示されてお
り、この多層プリント配線板（５）は、多層配線板
（１）、金属板（２）、多層配線板（３）からなってい
るものである。金属板（２）は、厚さ１ｍｍのアルミニ
ウム板を陽極酸化処理をし、絶縁層を設けている。そし
て、上記各基板は、絶縁性の接着剤プリプレグ（ガラス
布にエポキシ樹脂を含浸させて半硬化させたもの）を介
して積層され、加熱加圧して多層プリント配線板（５）
を形成している。1 to 3 show an embodiment of the present invention, and FIGS. 4 to 6 show another embodiment. FIG. 1 shows a sectional view of a semiconductor device according to the present invention. This multilayer printed wiring board (5) comprises a multilayer wiring board (1), a metal plate (2) and a multilayer wiring board (3). It is what The metal plate (2) is formed by anodizing an aluminum plate having a thickness of 1 mm to provide an insulating layer. Then, the above-mentioned substrates are laminated via an insulating adhesive prepreg (glass cloth impregnated with epoxy resin and semi-cured), and heated and pressed to form a multilayer printed wiring board (5).
Is formed.
【０００８】本発明に係る実施例を図面に従って説明す
る。まず、図２（ａ）に示すように、銅箔により構成さ
れた配線層を有する２枚の内層用回路板（１Ａ）を外層
用銅箔（ａ）と共にプリプレグ（４）を介して積層して
図２（ｂ）のように一体化する。この時、内層の配線層
（ｂ）には、後に集積回路チップを実装するための凹部
を形成した際に、集積回路チップの電極と内層の配線層
（ｂ）とを電気的に接続するための接続用パッド（２
ｂ）を形成しておく。そして、多層配線板（１）に適宜
穿設手段により図２（ｃ）に示すようなスルーホール
（２）を穿設（ドリリング）した後、このスルーホール
（２）の内壁面を銅めっきにて覆うためスルーホールの
化学銅めっき処理を施してめっき層を積層体表面とスル
ーホール（２）内壁面にそれぞれ形成し上部配線層と下
部配線層の電気的な導通を行えるようにする。An embodiment according to the present invention will be described with reference to the drawings. First, as shown in FIG. 2 (a), two inner layer circuit boards (1A) having a wiring layer composed of a copper foil are laminated together with an outer layer copper foil (a) via a prepreg (4). Integrated as shown in FIG. At this time, when a recess for mounting an integrated circuit chip later is formed in the inner wiring layer (b), the electrode of the integrated circuit chip and the inner wiring layer (b) are electrically connected to each other. Connection pad (2
b) is formed. Then, after the through hole (2) as shown in FIG. 2 (c) is drilled (drilled) in the multilayer wiring board (1) by appropriate drilling means, the inner wall surface of this through hole (2) is plated with copper. In order to cover the through hole, a chemical copper plating process is applied to the through hole to form a plated layer on the surface of the laminated body and on the inner wall surface of the through hole (2) so that the upper wiring layer and the lower wiring layer can be electrically connected.
【０００９】次いで、この化学銅めっき層の面上にスル
ーホール（２）周辺の一部と配線層形成部位を除きフォ
トレジスト層をパターン状に形成するとともに、このフ
ォトレジスト層から露出する部位に順次銅の電解めっき
層とはんだめっき層を形成し、その後、上記フォトレジ
スト層を除去する。そして、この銅の電解めっき層とは
んだめっき層をマスクにして化学銅めっき層等をエッチ
ングにより除去し、図２（Ｃ）に示すような多層配線板
（１）を製造する。上記方法と同様にして多層配線板
（３）を製造する。Then, a photoresist layer is formed in a pattern on the surface of the chemical copper plating layer except for a part around the through hole (2) and a wiring layer forming portion, and a portion exposed from the photoresist layer is formed. An electrolytic plating layer of copper and a solder plating layer are sequentially formed, and then the photoresist layer is removed. Then, the electrolytic copper plating layer and the solder plating layer of copper are used as a mask to remove the chemical copper plating layer and the like by etching to manufacture a multilayer wiring board (1) as shown in FIG. 2 (C). A multilayer wiring board (3) is manufactured in the same manner as the above method.
【００１０】次に、厚さ１ｍｍのアルミニウム板を１５
％の硫酸水溶液で温度２０℃、直流電流密度１．０〜
１．２Ａ／ｄｍ2 １０分間の条件で陽極酸化し、酸化皮
膜の膜厚を約３μｍに形成し、表面絶縁層を形成した金
属板（２）を製造する。Next, an aluminum plate with a thickness of 1 mm is attached to 15
% Sulfuric acid aqueous solution at a temperature of 20 ° C. and a direct current density of 1.0 to
Anodization is performed under the conditions of 1.2 A / dm 2 for 10 minutes to form an oxide film having a thickness of about 3 μm, and a metal plate (2) having a surface insulating layer is manufactured.
【００１１】そして、多層配線板（１）、プリプレグ
（４）、金属板（２）、プリプレグ（４）、多層配線板
（３）、の順に重ねあわせ加熱加圧して図３のように金
属板を内層とした多層配線板（５）を得ることができ
る。その多層配線板（５）に集積回路チップを実装する
ために、多層配線板（５）を金属板（２）に達する深さ
で、且つ接続用パッド（２ｂ）を露出するように段付き
凹部（６）をザグリ加工で形成する。集積回路チップと
してベアチップ（７ａ）を凹部（６）の底部に接着剤
（８）で接着し、ベアチップ（７ａ）の電極と多層配線
板（１）の接続用パッド（２ｂ）をワイヤーボンディン
グにより接続する。次に、ベアチップ（７ａ）を搭載し
た凹部（６）にベアチップ（７ａ）及びワイヤーが充分
埋まる程度にエポキシ樹脂（９）を充填し、表面を平滑
にして第２の搭載面を形成する。この時、充填物質は、
エポキシ樹脂に限らず絶縁性のあるものであればよい。Then, the multi-layer wiring board (1), the prepreg (4), the metal plate (2), the prepreg (4), and the multi-layer wiring board (3) are superposed in this order and heated and pressed to form a metal plate as shown in FIG. It is possible to obtain a multilayer wiring board (5) having an inner layer of. In order to mount the integrated circuit chip on the multilayer wiring board (5), the multilayer wiring board (5) has a stepped recess at a depth reaching the metal plate (2) and exposing the connection pads (2b). (6) is formed by counterboring. A bare chip (7a) as an integrated circuit chip is bonded to the bottom of the recess (6) with an adhesive (8), and the electrode of the bare chip (7a) and the connection pad (2b) of the multilayer wiring board (1) are connected by wire bonding. To do. Next, an epoxy resin (9) is filled into the recess (6) on which the bare chip (7a) is mounted so that the bare chip (7a) and the wire are sufficiently filled, and the surface is smoothed to form a second mounting surface. At this time, the filling substance is
It is not limited to the epoxy resin, and any insulating resin may be used.
【００１２】２つめの集積回路チップとしてリードフレ
ームに搭載し樹脂モールドされたＩＣパッケージ（７
ｂ）をベアチップ（７ａ）上に実装する前に多層配線板
（１）の最外層の接続用パッド（３ｂ）にクリーム半田
を印刷し、ＩＣパッケージ（７ｂ）のアウターリード
（７ｃ）と、接続用パッド（３ｂ）との位置あわせを行
いながら、第２の搭載面に集積回路チップ（７ｂ）を搭
載し、リフローして、クリーム半田を溶融し、アウター
リード（７ｃ）と接続用パッド（３ｂ）を接続し、マル
チチップ半導体装置（１０）を形成する。A second integrated circuit chip mounted on a lead frame and resin-molded IC package (7
Before mounting b) on the bare chip (7a), cream solder is printed on the connection pads (3b) of the outermost layer of the multilayer wiring board (1) to connect with the outer leads (7c) of the IC package (7b). The integrated circuit chip (7b) is mounted on the second mounting surface while aligning with the pad (3b) for soldering, reflowed to melt the cream solder, and the outer lead (7c) and the connection pad (3b). ) Are connected to form a multi-chip semiconductor device (10).
【００１３】ベアチップ（７ａ）は、多層配線板（１）
の凹部（６）に実装され、更にその上に２つめの集積回
路チップ（７ｂ）を実装することになるので、半導体装
置使用時に発熱量がおおく発熱しても、ベアチップ（７
ａ）は金属板（２）に直接接続するので金属板（２）を
つたって放熱される。尚、放熱性を向上させるために、
２つめの集積回路チップ（７ｂ）上に放熱用のフィンを
設けることも可能である。The bare chip (7a) is a multilayer wiring board (1).
Since the second integrated circuit chip (7b) is mounted on the concave portion (6) of the bare chip (7) even if the amount of heat generated during use of the semiconductor device is large, the bare chip (7
Since a) is directly connected to the metal plate (2), heat is radiated through the metal plate (2). In order to improve heat dissipation,
It is also possible to provide fins for heat dissipation on the second integrated circuit chip (7b).
【００１４】上記実施例は、放熱性を考えて、金属板を
内層した多層配線板の例であるが、通常の多層配線板を
ざぐったもの、あるいは、基材のうえに配線層を設け、
感光性ポリイミドで絶縁層を設けて更にその上に配線層
と導電層を形成し、かつ、上下の配線層を接続させなが
ら配線層を形成していくいわゆるビルトアップ法による
多層配線板でもよい。そして、集積回路チップを図４の
ように２つ以上搭載することも可能である。また、集積
回路チップと多層配線板の接続用パッドとのワイヤーボ
ンディングによる接続の方法として、上記実施例の他に
図５に示すようなバリエーションも可能であり、更に集
積回路チップと多層配線板の接続用パッドとの接続も、
ワイヤーボンディングに限らず、図６のようにＴＡＢ
（７ｄ）を使用することも可能である。The above embodiment is an example of a multi-layer wiring board having a metal plate as an inner layer in consideration of heat dissipation. However, a normal multi-layer wiring board is scooped out, or a wiring layer is provided on a base material,
It may be a multilayer wiring board by a so-called built-up method in which an insulating layer is provided with a photosensitive polyimide, a wiring layer and a conductive layer are further formed on the insulating layer, and the wiring layers are formed while connecting the upper and lower wiring layers. It is also possible to mount two or more integrated circuit chips as shown in FIG. Further, as a method of connecting the integrated circuit chip and the connection pad of the multilayer wiring board by wire bonding, a variation as shown in FIG. 5 is possible in addition to the above-described embodiment, and further, the integrated circuit chip and the multilayer wiring board are connected. Connection with the connection pad,
Not limited to wire bonding, TAB as shown in FIG.
It is also possible to use (7d).
【００１５】[0015]
【発明の効果】以上のように、本発明によれば、多層配
線板の内層に形成した集積回路チップとの接続用パッド
を露出するように多層配線板をざぐって凹部を形成し、
第１の集積回路チップは内層に形成した集積回路チップ
との接続用パッドと接続し、更にその上に集積回路チッ
プを重ねて搭載することにより集積回路チップを同一面
積上に２つ以上搭載することが可能になるので実装密度
があがり、更に配線基板の金属層にチップを搭載するこ
とにより放熱効果も向上する。As described above, according to the present invention, the multi-layered wiring board is formed with a recess so as to expose the pad for connection with the integrated circuit chip formed in the inner layer of the multi-layered wiring board,
The first integrated circuit chip is connected to a pad for connection with the integrated circuit chip formed in the inner layer, and the integrated circuit chip is further mounted thereon to mount two or more integrated circuit chips on the same area. Therefore, the mounting density is increased, and the heat dissipation effect is also improved by mounting the chip on the metal layer of the wiring board.
【図１】本発明のマルチチップ半導体装置の実施例を示
す断面図である。FIG. 1 is a sectional view showing an embodiment of a multi-chip semiconductor device of the present invention.
【図２】本発明の実施例の多層配線板の製造過程を示す
断面図である。FIG. 2 is a cross-sectional view showing a manufacturing process of a multilayer wiring board according to an example of the present invention.
【図３】本発明の実施例の製造過程を示すマルチチップ
半導体装置の断面図である。FIG. 3 is a cross-sectional view of a multi-chip semiconductor device showing a manufacturing process of an embodiment of the present invention.
【図４】本発明の他の実施例のマルチチップ半導体装置
の断面図である。FIG. 4 is a sectional view of a multi-chip semiconductor device according to another embodiment of the present invention.
【図５】本発明の他の実施例のマルチチップ半導体装置
の断面図である。FIG. 5 is a sectional view of a multi-chip semiconductor device according to another embodiment of the present invention.
【図６】本発明の他の実施例のマルチチップ半導体装置
の断面図である。FIG. 6 is a sectional view of a multi-chip semiconductor device according to another embodiment of the present invention.
【図７】従来のマルチチップ半導体装置の断面図であ
る。FIG. 7 is a cross-sectional view of a conventional multi-chip semiconductor device.
１…多層配線板 ２…金属板 ３…多層配線板 ４…
プリプレグ ５…多層配線板 ６…凹部 ７ａ…ベアチップ ７ｂ
…ＩＣパッケージ ８…接着剤 ９…エポキシ樹脂 １０…マルチチップ半
導体装置1 ... Multilayer wiring board 2 ... Metal plate 3 ... Multilayer wiring board 4 ...
Prepreg 5 ... Multilayer wiring board 6 ... Recess 7a ... Bare chip 7b
... IC package 8 ... Adhesive 9 ... Epoxy resin 10 ... Multi-chip semiconductor device
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 25/065 25/07 25/18 8719−4Ｍ Ｈ０１Ｌ 23/12 Ｗ 25/08 Ｚ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H01L 25/065 25/07 25/18 8719-4M H01L 23/12 W 25/08 Z
Claims (3)
板に複数の集積回路チップを実装して構成されるマルチ
チップ半導体装置において、 前記多層プリント配線板に、前記導体回路のうち内層の
導体回路の一部を外部へ露出させる段付き凹部が形成さ
れ、その段付き凹部内に集積回路チップが多層プリント
配線板の厚さ方向に複数搭載され、前記集積回路チップ
の少なくとも１つが、前記内層の導体回路と電気的に接
続されていることを特徴とするマルチチップ半導体装
置。1. A multi-chip semiconductor device configured by mounting a plurality of integrated circuit chips on a multilayer printed wiring board having a plurality of conductor circuits, wherein the multilayer printed wiring board has an inner conductor circuit of the conductor circuits. A stepped recess is formed to expose a part of the outside to the outside, and a plurality of integrated circuit chips are mounted in the stepped recess in the thickness direction of the multilayer printed wiring board, and at least one of the integrated circuit chips is A multi-chip semiconductor device, which is electrically connected to a conductor circuit.
つが、リードフレーム上に搭載し樹脂モールドされた集
積回路部品であることを特徴とする請求項１に記載のマ
ルチチップ半導体装置。2. At least one of the plurality of integrated circuit chips.
2. The multi-chip semiconductor device according to claim 1, wherein the one is an integrated circuit component mounted on a lead frame and resin-molded.
が金属板であり、その金属板に少なくとも１つの集積回
路チップが直接実装されることを特徴とする請求項１及
び請求項２に記載のマルチチップ半導体装置。3. The multilayer printed wiring board according to claim 1, wherein at least one layer is a metal plate, and at least one integrated circuit chip is directly mounted on the metal plate. Multi-chip semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5073230A JPH06291246A (en) | 1993-03-31 | 1993-03-31 | Multi-chip semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5073230A JPH06291246A (en) | 1993-03-31 | 1993-03-31 | Multi-chip semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06291246A true JPH06291246A (en) | 1994-10-18 |
Family
ID=13512177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5073230A Pending JPH06291246A (en) | 1993-03-31 | 1993-03-31 | Multi-chip semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06291246A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH098213A (en) * | 1995-06-16 | 1997-01-10 | Nec Corp | Method for mounting semiconductor element and multichip module manufactured by it |
| WO2004073064A1 (en) * | 2003-02-17 | 2004-08-26 | Renesas Technology Corp. | Semiconductor device |
| WO2006095852A1 (en) * | 2005-03-10 | 2006-09-14 | Kyocera Corporation | Electronic component module and method for manufacturing same |
| JP2011228521A (en) * | 2010-04-21 | 2011-11-10 | Fujitsu Ltd | Manufacturing method of semiconductor device |
-
1993
- 1993-03-31 JP JP5073230A patent/JPH06291246A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH098213A (en) * | 1995-06-16 | 1997-01-10 | Nec Corp | Method for mounting semiconductor element and multichip module manufactured by it |
| WO2004073064A1 (en) * | 2003-02-17 | 2004-08-26 | Renesas Technology Corp. | Semiconductor device |
| WO2006095852A1 (en) * | 2005-03-10 | 2006-09-14 | Kyocera Corporation | Electronic component module and method for manufacturing same |
| US7808796B2 (en) | 2005-03-10 | 2010-10-05 | Kyocera Corporation | Electronic component module and method for manufacturing the same |
| JP2011228521A (en) * | 2010-04-21 | 2011-11-10 | Fujitsu Ltd | Manufacturing method of semiconductor device |
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