JP3506789B2 - Semiconductor package - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package.

[0002]

2. Description of the Related Art Generally, an electric connection between an IC chip or an LSI chip and a printed wiring board which is a mother board is made through a semiconductor package. In recent years, resin-encapsulated semiconductor packages (so-called plastic packages) have become the mainstream. When manufacturing a plastic package, it is necessary to surely dissipate the heat generated by the LSI chip in order to prevent malfunction and thermal destruction of the LSI chip. Therefore, in the conventional plastic package, for example, a measure is taken to dispose a radiator, which is a plate material made of a high thermal conductive material such as Cu-W, on the back surface side of the chip mounting portion.

However, if an attempt is made to secure a large heat radiation area in the package by using a large heat radiator, the area where the wiring cannot be formed (dead area) is increased by the area of the heat radiation area. For this reason,
The size of the entire package has to be increased, resulting in deterioration of electrical characteristics such as a decrease in signal propagation speed. On the contrary, if the dead area is made as small as possible to maintain the current state of the package size, the heat radiator must be made small, and as a result, a sufficient heat radiation area cannot be secured.

As a means for solving such a problem,
2. Description of the Related Art There has conventionally been proposed a semiconductor package in which a radiator formed by forming a high-density wiring layer on one side surface of a plate material made of a high thermal conductive material is mounted in a window portion of a base unit having input / output terminals.

The high-density wiring layer of the semiconductor package is
It is a build-up multilayer thin film wiring layer, and generally includes a power supply layer and a ground layer in addition to the signal layer. Various electronic components, LSI chips, and the like are mounted in the electronic component mounting area in the outermost layer of the high-density wiring layer. A plurality of bonding pads are arranged on the outer edge of the electronic component mounting area. Further, a plurality of connection pads are arranged around the window of the base unit so as to correspond to the pads. These pads are electrically connected to each other via bonding wires. Then, an electrical connection portion such as a bonding wire is sealed with potting resin.

[0006]

However, while the above semiconductor package has the advantage of being excellent in both heat dissipation and compactness, it has the following drawbacks.

That is, the ground layer and the power supply layer are usually formed in a large area in the buildup layer and in a nearly solid state. Therefore, two layers are additionally required in addition to the wiring layer and the pad formation layer, and it is inevitable that the buildup layer is multilayered. Then, the cost of forming the build-up layer increases correspondingly, which in turn increases the cost of the entire semiconductor package. On the other hand, if the ground layer and the power supply layer are omitted, it is not possible to reduce the parasitic parameters associated with the semiconductor package, which causes problems such as a slow signal rising speed. In this case, the electrical characteristics are deteriorated, and the high functionality of the semiconductor package cannot be sufficiently achieved.

The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor package having excellent electrical characteristics while avoiding the high cost associated with the multilayering of high-density wiring layers. Especially.

[0009]

In order to solve the above-mentioned problems, the invention according to claim 1 uses a plate material made of a highly heat-conductive material as a heat-dissipating region on one side and a high-density wiring on the opposite side. An electronic component mounting area including a layer, an electronic component mounting portion is provided on the high density wiring layer, and a plurality of connection terminals electrically connected to the electronic component side through the high density wiring layer are mounted on the electronic component. A heat dissipating member disposed at the outer edge of the area and a window portion for exposing the heat dissipating area of the heat dissipating member to the outside are provided in substantially the center of the printed wiring board, and one side surface of the printed wiring board and the window are provided. And a plurality of bonding pads are arranged around the portion, and a plurality of input / output terminals are arranged in a region outside the bonding pad formation region, and a base unit for mounting a radiator is provided. Bonde And Ngupaddo said connection terminal is electrically connected via a bonding wire, a further semiconductor package that connection portion is sealed with a resin, high-density wiring layers of the heat radiating body wiring and the insulating layer
Build-up with a structure in which patterns and layers are stacked alternately
And a printed wiring board constituting the base unit is a multilayer board having at least three conductor layers, and two of the conductor layers are a ground layer and a power supply layer. To do.

According to a second aspect of the present invention, in the first aspect, the printed wiring board is a four-layer board formed by a subtractive process. According to a third aspect of the invention, in the first or second aspect, a conductor pattern for mounting an electronic component is formed on the side of the printed wiring board on which the input / output terminals are not formed.

[0011]

According to the invention described in claims 1 to 3, the provision of the ground layer and the power source layer on the base unit side can reduce the parasitic parameters associated with the semiconductor package. Therefore, the delay of the rising speed of the signal is prevented. Further, since the ground layer and the power supply layer are provided on the base unit side, the necessity of providing the ground layer and the power supply layer on the radiator side is reduced. Therefore, the number of high-density wiring layers can be reduced accordingly.

According to the third aspect of the invention, since the electronic parts can be mounted on the base unit side, it is not necessary to form a conductor pattern or the like for mounting them on the high density wiring layer side.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor package according to an embodiment of the present invention will be described in detail below with reference to FIGS.

The semiconductor package 11 of this embodiment is shown in FIG.
As shown in FIG. 1 and the like, it is basically composed of a PGA type base unit 25 and a build-up multilayer thin film wiring board 12 which is a radiator.

The build-up multilayer thin film wiring board 12 is shown in FIG.
As shown in, the main material is a phosphor bronze plate 13 as a plate material made of a high thermal conductivity material. The entire one side surface of the phosphor bronze plate 13 is a heat dissipation area,
In addition, the entire opposite side surface is an electronic component mounting area. A buildup layer B as a high-density wiring layer is formed in the entire electronic component mounting area. In this embodiment, the buildup layer B has a structure in which the insulating layers 14 and the extremely fine wiring patterns 15 are alternately laminated.
The wiring patterns 15 of the respective layers are connected to each other by via holes 16 formed in the insulating layer 14.

As shown in FIG. 3, build-up layer B
A plurality of die pads 17 as electronic component mounting portions are provided on the top. LSI chips 18 and 19 as electronic components are mounted on the die pad 17. LS
The I chips 18 and 19 and the bonding pad 20 on the buildup layer B are electrically connected via a bonding wire 21. On the outer edge of the buildup layer B, a large number of connection pads 22 as connection terminals are regularly arranged. The LSI chips 18 and 19 and the connection pads 22 are electrically connected to each other through the wiring pattern 15 on the inner layer or the outer layer of the buildup layer B.

The base unit 25 is manufactured by using a printed wiring board 40 whose main forming material is a plastic plate material (in this embodiment, a copper clad laminated board made of BT resin).
This is because this type of plate material has an advantage that it is basically easy to perform drilling and the like. The printed wiring board 40 that constitutes the base unit 25 of this embodiment is a so-called four-layer board including four conductor layers. In FIG. 3, the first conductor layer formed on the pin protruding surface S1 (upper surface in the figure) of the printed wiring board 40 is the through hole 2
8 is a land 31 and a substantially square-shaped sealing pattern 32. Inner layer conductor circuits 42 and 43 as second and third conductor layers are formed on both surfaces of an inner layer board 41 which is a core of the printed wiring board 40. The fourth conductor layer formed on the pin non-projecting surface S2 of the printed wiring board 40 is a land 31 of the through hole 28, a ground pattern 44 of a predetermined shape, and a connection pad as a conductor pattern for mounting electronic components. 47. This pin non-projecting surface S2
Are partially covered with the solder resist 34. As shown in FIG. 3, an electronic component 48 such as a decoupling capacitor is soldered on the connection pad 47 formed on the pin non-projecting surface S2.

In the case of this printed wiring board 40,
The second conductor layer serves as a signal layer, the third conductor layer serves as a power supply layer, and a part of the fourth conductor layer serves as a ground layer. The printed wiring board 40 of this embodiment is manufactured by a normal subtractive process. Further, in this embodiment, the inner layer plate 41 has a thickness of about 1.
It is set to 5 mm. L / S of conductor layer in each layer is 1
25 μm / 125 μm, and the height is about 38 μm.

As shown in FIGS. 1 and 2, a window portion 26 having an outer shape that is substantially the same as the outer shape of the build-up multilayer thin film wiring board 12 is provided at a substantially central portion of the printed wiring board 40. . Around the window portion 26, a number of through holes 28 penetrating the front and back are formed. The through holes 28 electrically connect the conductor layers. A metal pin 29 as an input / output terminal is inserted into each through hole 28. The strip-shaped region of the base unit 25 in which the pins 29 are provided is referred to as an input / output terminal forming region R2 for convenience of description.

As shown in FIGS. 1 and 3, on the inner wall surface of the window portion 26, a pad step portion 27a and a support step portion 27b are provided.
Are provided in a staircase. Pad step 27a
The height of the upper surface of the pin is 0.5 mm to 1.0 mm lower than the height of the pin protruding surface S1 of the printed wiring board 40. A rectangular bonding pad 3 is formed on the upper surface of the pad step portion 27a so as to entirely surround the window portion 26.
0 is set. The respective bonding pads 30 and the through holes 28 are electrically connected via the inner layer conductor circuit 42. In addition, the substantially square-shaped band-shaped region in which the bonding pad 30 is provided in the base unit 25 is referred to as a bonding pad formation region R1 for convenience of description. In addition, the input / output terminal formation region R
The substantially square-shaped strip-shaped region existing between 2 and the bonding pad formation region R1 will be referred to as a blank region R3. In the case of this embodiment, the width of the blank area R3 is about 1 mm to
It is 5 mm.

Here, the pin protruding surface S1 and the pad step portion 2
The difference from the height of the upper surface of 7a is at least 0.3 mm,
It is preferably 0.5 mm to 1.0 mm. If this difference is too small, it may not be possible to reliably prevent the flow of the sealing resin 36. On the other hand, if this difference is too large, it is convenient for enhancing the above-mentioned flow blocking action, but on the other hand, the semiconductor package 11 may be thickened as a whole. In this embodiment, this difference is set to 0.5 mm in consideration of this point.

A supporting step 27b is arranged inside the pad step 27a. The upper surface of the supporting step portion 27b is relatively lower than the upper surface of the pad step portion 27a. In this embodiment, specifically, the difference is approximately equal to the thickness of the build-up multilayer thin film wiring board 12 and is about 1.1.
mm. Build-up multilayer thin film wiring board 12 with window 26
, The outer edge of the back surface of the build-up multilayer thin film wiring board 12 is supported by the upper surface of the supporting step portion 27b.

As shown in FIG. 3, the base unit 2
The bonding pad 30 on the No. 5 side and the connection pad 22 of the build-up multilayer thin film wiring board 12 are electrically connected via a bonding wire 33. And LS
I chip 18, 19 side and build-up multilayer thin film wiring board 1
The electrical connection portion with the second side and the electrical connection portion with the buildup multilayer thin film wiring board 12 side and the base unit 25 side are entirely sealed with a sealing resin 36. In this embodiment, the sealing resin 36 has a viscosity of 500 cps to 1000.
cps epoxy resin (Kyushu Matsushita, trade name: CCN20
01-23P) is used. LSI chip 18,
The electrical connection portion between the 19 side and the buildup multilayer thin film wiring board 12 side is specifically the bonding pad 20, LS.
Bonding pads (not shown) on the upper surfaces of the I-chips 18 and 19 and bonding wires 21 connecting them.
Refers to. The electrical connection portion between the buildup multilayer thin film wiring board 12 side and the base unit 25 side refers to the bonding pad 30, the connection pad 22 and the bonding wire 33 connecting them.

As shown in FIGS. 1 and 3, the sealing pattern 32 formed around the window 26 on the pin projecting surface S1 has a sealing material made of a metal material having excellent conductivity such as Kovar. The stop cap 45 is soldered. The resin sealing portion is entirely covered by the sealing cap 45.

As shown in FIG. 3, the base unit 2
When the build-up multilayer thin-film wiring board 12 is mounted on No. 5, the heat radiation area of the build-up multilayer thin-film wiring board 12 is exposed from the window 26 to the outside. The semiconductor package 11 of this embodiment is mounted face down on a motherboard (not shown) by the pins 29. That is, the heat dissipation area faces upward (outward) and the electronic component mounting area faces downward (inward) during mounting. The area of the heat dissipation area, more specifically, the area of the portion of the heat dissipation area exposed from the window 26 is the actual heat dissipation area of the semiconductor package 11.

Next, the procedure for producing the semiconductor package 11 will be described with reference to FIG. Semiconductor package 11
The build-up multi-layered thin film wiring board 12 constituting the above is manufactured as follows. First, the starting material is phosphor bronze plate 1
One side of 3 is blackened, and a photosensitive epoxy resin is applied thereon. Then, by exposing and developing, a thickness of 15 μm having a via hole forming hole having an inner diameter of 40 μm
The insulating layer 14 is formed. A 0.1 μm thick Cr thin layer is formed on the insulating layer 14 by sputtering, and a 0.2 μm thick Cu thin layer is further formed on the Cr thin layer. L / S = 25 μm /
A plating resist for forming the wiring pattern 15 of 25 μm is arranged on the Cu thin layer. In this state, electrolytic Cu plating and electrolytic Ni plating are sequentially performed to obtain a thickness of 6
A Cu plating layer having a thickness of μm and a Ni plating layer having a thickness of 1 μm are respectively formed. After removing the plating resist, the Cu thin layer and the Cr thin layer in the non-plated portion are etched using a cupric chloride solution and a 20% hydrochloric acid aqueous solution. Then, the insulating layer 14 is formed by repeating the above steps as needed.
And the wiring patterns 15 made of a plurality of kinds of metals are alternately formed. As a result, a build-up multilayer thin-film wiring board (35 mm square, 1.0 mm thick) 12 having 5 layers of wiring patterns 15
Is created. After this, an open / short test is conducted.

On the other hand, the base unit 25 is manufactured as follows. First, a copper-clad laminate made of BT resin (50 mm
(Square, 1.7 mm thick) Around the central part, a counterbore is processed into a substantially square shape (31 mm square). Through this process, a through hole is formed in that portion. Electrolytic Cu plating is performed in a state where a plating resist is arranged on a predetermined portion, to deposit Cu on a necessary portion. After removing the plating resist, unnecessary Cu is etched. By this etching,
The signal layer and the power supply layer (that is, the inner layer conductor circuits 42 and 43 and the bonding pad 30) are formed. A prepreg 46 also made of BT resin is laminated on both surfaces of the obtained inner layer plate 41 (see FIG. 4 (a)). This prepreg 46
Is on the so-called B stage, and copper foil is attached to one side of it. The thickness of the prepreg 46 is 0.1 mm.
~ 0.3 mm. A hole for forming a through hole for inserting a pin is formed by punching a laminated body obtained by laminating.

Electrolytic Cu plating is performed in a state where a plating resist is arranged on a predetermined portion to deposit Cu on a necessary portion. After removing the plating resist, unnecessary Cu
To etch. By this etching, land 3
1, the seal pattern 32, the ground pattern 44, and the connection pad 47 are formed (see FIG. 4B). After that, a solder resist 34 is formed on the pin non-projecting surface S2 side, and then the pin 29 is inserted into the through hole 28. Further, the prepreg 46 on the pin protruding surface S1 side is subjected to a spot facing process to form the pad step portion 27a and expose the bonding pad 30. Further, the prepreg 46 on the pin non-projecting surface S2 side is counterbored to form the supporting stepped portion 27b and penetrate the window portion 26. Finally, the counterbore surface is diced (see Fig. 4 (c)). After this, an open / short test is conducted.

Next, the build-up multilayer thin film wiring board 12 and the base unit 2 which have passed the open / short test.
And 5 are adhesive seals (Mitsubishi Yuka, trade name: YEF-040) 35 arranged on the supporting step 27b of the copper clad laminate.
Temporarily bond with. In this embodiment, the pressure for temporary adhesion is 2
Was 5 kgf / cm ^2, temperature of 220 ° C., the time is 2 minutes. Then, the adhesive seal 35 is completely cured by performing curing at 150 ° C. for 60 minutes.

Next, using a die bonder, the tested LSI chip 18 for CPU is mounted on the die pad 17.
6 and memory LSI chips 19 are mounted. Here, a wire bonding device (made by Kyushu Matsushita, trade name: H
W-2200) is used to wire-bond the LSI chips 18 and 19. At this time, wire bonding is also performed between the bonding pad 30 and the connection pad 22 using the same device.

Then, resin encapsulation is performed by the potting method to electrically connect the LSI chips 18 and 19 with each other.
Build-up multilayer thin film wiring board 12 side and base unit 2
The portion electrically connected to the 5 side is entirely sealed with the sealing resin 36 (see FIG. 4 (d)). Finally, the sealing cap 45
Are soldered to the sealing pattern 32. At this time,
The electronic component 48 is also soldered on the connection pad 47.
The semiconductor package 11 is manufactured through the above procedure.

According to the semiconductor package 11 of this embodiment, the build-up layer B, which is a high-density wiring layer, is formed on one side of the phosphor bronze plate 13 forming the build-up multilayer thin film wiring board 12. . Therefore, even when the semiconductor package 11 is formed together with the base unit 25, a dead area corresponding to the area of the buildup multilayer thin film wiring board 12 does not occur on the surface of the semiconductor package 11. Therefore, the semiconductor package 11
It is possible to secure a sufficient heat dissipation area without making the whole large. In addition, electrical characteristics are improved such that the signal propagation speed is increased due to avoiding the increase in size. Then, as the heat dissipation of the semiconductor package 11 is improved as described above, the LSI chips 18, 19
The malfunctions and heat destruction of are much less than in the past.

When the build-up multilayer thin film wiring board 12 is mounted in the accommodating portion of the base unit 25, the heat radiation area on one side of the phosphor bronze plate 13 is largely exposed from the window 26. Therefore, the heat conducted from the electronic component mounting area to the heat radiation area through the buildup layer B and the phosphor bronze plate 13 is efficiently dissipated to the atmosphere through the window 26.

Then, the semiconductor package 11 of the present embodiment.
Then, the printed wiring board 40 constituting the base unit 25 is a four-layer board, and two of the conductor layers thereof serve as a ground layer and a power supply layer. Therefore,
The parasitic parameter (specifically, the parasitic capacitance added to the signal line) associated with the semiconductor package 11 is reduced. Therefore, the delay of the rising speed of the signal is surely prevented, so that the electrical characteristics are improved.
As a result, high functionality, high added value, and high reliability of the semiconductor package 11 can be achieved.

Further, since the ground layer and the power supply layer are provided on the base unit 25 side, the necessity of providing the ground layer and the power supply layer on the buildup multilayer thin film wiring board 12 side is reduced. Therefore, the number of buildup layers B can be reduced correspondingly. Even with the same number of layers as the conventional one, there is an advantage that more wiring patterns 15 can be formed in the build-up layer B as much as the ground layer and the power supply layer are eliminated. Furthermore, if the ground layer and the power supply layer are eliminated in the buildup layer B, the moisture contained in the insulating layer 14 will easily escape to the outside. This also surely contributes to higher functionality.

Further, in the present embodiment, a four-layer board by the subtractive process is used. Therefore, the base unit 25 can be manufactured relatively easily and inexpensively as compared with, for example, a multilayer board formed by an additive process or the like. Therefore, it is convenient for achieving the cost reduction of the semiconductor package 11. The printed wiring board 40 is formed by laminating prepregs 46 on both surfaces of the inner layer board 41. That is, as compared with the configuration in which the prepreg 46 is laminated only on one surface, the stress that causes the printed wiring board 40 to warp is less likely to be applied. Therefore, the base unit 25 is resistant to thermal deformation.

According to the present embodiment in which the connection pads 47 are provided, the electronic components 48 can be mounted on the base unit 25 side, so that the connection pads and the like for mounting them are formed on the buildup layer B side. There is no need. Therefore, the area of the build-up layer B can be narrowed and the number of layers can be reduced, which in turn prevents an increase in size of the outer shape and an increase in cost. Particularly, in this embodiment, the decoupling capacitor as the electronic component 48 is mounted on the base unit 25 via the connection pad 47. Therefore, the influence of the inductance associated with the parasitic parameters of the semiconductor package 11 is reduced, and the noise can be reduced. Therefore, the electrical characteristics are surely improved.

Also, the pad step portion 2 is formed on the inner wall surface of the window portion 26.
7a and the supporting step portion 27b are provided in a stepped shape,
The bonding pad 30 is provided on the upper surface of the pad step portion 27a. Therefore, the surface on which the bonding pad 30 is formed is the pin protruding surface S of the printed wiring board 40.
It is relatively lower than 1. Therefore, when the sealing resin 36 supplied by potting is about to spread in the direction of the input / output terminal forming region R2, the inner wall surface of the window portion 26 prevents the sealing resin 36 from flowing. As a result, the outline of the sealing resin 36 becomes linear by following the window 26. Therefore, as compared with the conventional package whose outline is likely to be indefinite, the semiconductor package 1
1 The overall appearance will definitely improve.

Further, as a result of eliminating the non-uniform flow of the sealing resin 36, variations in the electric resistance value are eliminated at the same time,
The electrical characteristics of the semiconductor package 11 are surely improved.
Of course, since the uneven flow of the sealing resin 36 is eliminated, the problem at the time of pin mounting is also eliminated. In addition, the work of supplying the sealing resin 36 at the time of potting becomes extremely easy. Furthermore, this semiconductor package 11
However, since no measure is taken to increase the width of the existing blank region R3 to some extent, the external size is not increased. Therefore, the demand for downsizing is not violated.

The present invention can be modified as follows, for example. (1) You may employ | adopt the structure like the semiconductor package 50 of the example 1 shown in FIG. The printed wiring board 52 that constitutes the base unit 51 is a so-called five-layer board.
In this printed wiring board 52, the second and third layers are wiring layers, the fourth layer is a power supply layer, and the fifth layer is a ground layer. On the inner wall surface of the window portion 26 of the printed wiring board 52, step portions 53a, 53b, 53c are provided in three steps and in a stepwise manner. Of these step portions 53a to 53c, two pad step portions 53a, 5 excluding the innermost supporting step portion 53c.
A plurality of bonding pads 3 are provided on the upper surface of 3b.
0 is formed. That is, this semiconductor package 50
Has a so-called two-tier structure. Even when the above-described configuration is adopted, the same operational effects as those of the above-described embodiment can be obtained.

(2) The number of layers of the printed wiring board may be three layers, and conversely may be more than four layers such as five layers, six layers, seven layers, eight layers, nine layers, and ten layers. Further, a plurality of power source layers may be provided and a plurality of ground layers may be provided. With this configuration, electrical characteristics can be further improved.

(3) The electronic component 48 does not have to be the decoupling capacitor as in the embodiment, but may be, for example, a chip capacitor, a chip resistor, a chip coil or the like. Further, not only passive components such as these, but also active components such as chip diodes and chip transistors may be used. In addition to implementing the SMDs listed above, T
Of course, MD may be mounted.

(4) A recess may be provided in the pin non-projecting surface S2 of the printed wiring board 40, the connection pad 47 may be formed in the recess, and the electronic component 48 may be embedded therein. This reduces the protruding portion, and the semiconductor package 11
The whole becomes thin.

(5) The base unit 25 may be provided with a conductor layer having a function different from those of the wiring layer, the ground layer and the power supply layer, for example, a conductor layer for magnetic shield. (6) The formation position of the connection pad 47 may be not only a region corresponding to the back side of the blank region R3 on the pin non-projecting surface S2 as shown in FIG. 2, but also a region on the outer edge side of the through hole 28, for example. Further, the land 31 of the through hole 28 itself can be used as the connection pad 47. Of course, the connection pad 47 is provided on the side surface of the base unit 25.
Can also be formed. In this case, a through hole or the like may be formed on the side surface of the base unit 25 and used as a connection pad. Similarly, it is possible to form the connection pad 47 on the pin protruding surface S1.

(7) It is preferable to secure a space for forming the connection pad 47 for mounting components and the ground pattern 44 by making the through hole 28 a landless through hole.

(8) The base unit 25 is not limited to the PGA type as in the embodiment, but may be the QFP type or the like. Here, in addition to the technical ideas described in the claims, the technical ideas grasped by the above-described embodiments and other examples will be listed below together with their effects.

(1) A window portion for exposing the heat radiation area of the heat radiator to the outside is provided in substantially the center of the printed wiring board,
A base unit in which a plurality of bonding pads are arranged on one side of the printed wiring board and around the window, and a plurality of input / output terminals are arranged in a region outside the bonding pad forming region. The printed wiring board is a multi-layer board having at least three conductor layers, and two layers of the conductor layers are a ground layer and a power supply layer.

(2) In the technical idea (1), a connection pad is provided on a surface of the printed wiring board forming the base unit where input / output terminals are not formed, and a decoupling capacitor is mounted on the pad. thing. With this configuration, the electrical characteristics can be further improved.

(3) In the technical ideas (1) and (2), the main forming material of the printed wiring board is at least one selected from epoxy resin, polyimide resin, BT resin and BCB resin. thing. With this configuration,
In addition to improving the electrical characteristics, the workability and cost of the base unit can be further improved.

The technical terms used in this specification are defined as follows. “High thermal conductivity material: A material having a higher thermal conductivity than a plastic material, for example, a ceramic material such as aluminum nitride, alumina, or mullite, or a metal material such as copper, copper alloy, or aluminum.”

[0051]

As described above in detail, according to the first aspect of the invention, the printed wiring board constituting the base unit is a multi-layer board having a power supply layer and a ground layer.
It is possible to provide a semiconductor package having excellent electrical characteristics while avoiding the high cost associated with the multilayering of high-density wiring layers. According to the second aspect of the present invention, the printed wiring board is a four-layer board formed by a subtractive process, so that the printed wiring board is resistant to thermal deformation and can be manufactured at low cost. According to the third aspect of the present invention, since the electronic component can be mounted on the base unit side, it is possible to reliably prevent an increase in size of the outer shape and an increase in cost.

[Brief description of drawings]

FIG. 1 is a bottom view showing a base unit according to an embodiment.

FIG. 2 is a plan view of the base unit shown in FIG.

FIG. 3 is an enlarged cross-sectional view of essential parts showing a semiconductor package of an example.

4A to 4D are schematic cross-sectional views showing the same manufacturing procedure.

FIG. 5 is a schematic cross-sectional view showing a semiconductor package of another example 1.

[Explanation of symbols]

11, 50 ... Semiconductor package, 12 ... Build-up multilayer thin film wiring board as heat radiator, 13 ... Plate material made of high thermal conductive material, 17 ... Die pad as electronic component mounting portion, 18, 19 ... LSI chip as electronic component , 22
... Connection pads as connection terminals, 25, 51 ... Base unit, 26 ... Window portion, 29 ... Pins as input / output terminals,
30 ... Bonding pad, 33 ... Bonding wire, 36 ... Sealing resin, 40, 52 ... Printed wiring board, 4
2 ... inner layer conductor circuit, 47 ... connection pad as conductor pattern for mounting electronic parts, B ... buildup layer as high density wiring layer, S2 ... input / output terminal non-formed surface.

Claims (3)

(57) [Claims] 1. A plate material made of a high thermal conductive material has one side surface as a heat radiation area and the other side surface as an electronic component mounting area having a high density wiring layer, and the electronic component mounting portion is provided on the high density wiring layer. A heat radiator having a plurality of connection terminals electrically connected to the electronic component side via the high-density wiring layer at an outer edge portion of the electronic component mounting area; and a heat radiation area of the heat radiator outside. A window portion for exposing the printed wiring board is provided substantially at the center of the printed wiring board, and a plurality of bonding pads are arranged on one side of the printed wiring board and around the window portion. A base unit for mounting a heat radiator in which a plurality of input / output terminals are arranged in a region, and the bonding pad and the connection terminal are electrically connected via a bonding wire. It is, a further semiconductor package that connection portion is sealed with a resin, high-density wiring layers of the heat radiating body and the wiring pattern and the insulating layer
A build-up layer having an alternating laminated structure,
The printed wiring board constituting the base unit is a multilayer board having at least three conductor layers, and two of the conductor layers are a ground layer and a power supply layer. 2. The semiconductor package according to claim 1, wherein the printed wiring board is a four-layer board formed by a subtractive process. 3. The semiconductor package according to claim 1, wherein a conductor pattern for mounting an electronic component is formed on a side of the printed wiring board where the input / output terminals are not formed.