JP2000332160A - Cavity-down semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To greatly omit the number of laminating steps for reducing cost and facilitate the wiring design for adjusting characteristic impedances or preventing crosstalks by forming a wiring layer on an insulation layer, formed on a metal plate having a recess for mounting a semiconductor chip. SOLUTION: This cavity-down semiconductor package comprises an insulation layer 121 on a heat sink plate 103, having a recess C for mounting a semiconductor chip 101 and a wiring layer 119 on the insulation layer 121. The semiconductor chip 101 is thus mounted directly on the heat sink plate 103 and hence superior in heat radiation. Since the plate 103 is formed in a concave form to allow the heights of the chip 101, wire bonding pads 107 are made easily adjustable. GND pads of the semiconductor chip are connected directly to the heat sink plate, and hence the wiring density of signal traces, etc., formed on the surface layer of the semiconductor package can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cavity-down type semiconductor package, and more particularly to a cavity-down type semiconductor package which is easy to design.

[0002]

2. Description of the Related Art PBGA (plastic ball grid array) is often used due to demands for miniaturization, thinning, multi-terminals, high density, and low cost. Have been.

As shown in FIG. 7, PBGA has C
A semiconductor chip mounting portion 223 for mounting the semiconductor chip 201 is provided at the center of an insulating substrate (insulating layer 221) on which a u foil (conductor layer 231) is pasted and patterned. A bonding pad portion 225 for connecting the semiconductor chip 201 with the wire 209 is formed around the semiconductor chip mounting portion 223.

On a surface opposite to the semiconductor chip mounting portion 223, solder pads (portions on which solder balls 205 are provided) arranged in a grid for connecting the PBGA to a PCB (printed circuit board) are formed. The conductor layers 231 on the front and back of the package are electrically connected by plated through holes (via holes) 217.

[0005] A solder resist film 215 for protecting the conductor pattern is formed on the surface of the PBGA excluding the semiconductor chip mounting portion 223, the bonding pad portion 225, and the solder pad. The semiconductor chip 201
Die bonding to the PBGA is performed using an adhesive such as Ag paste. The semiconductor chip 201 is connected to a PBGA conductor pattern by a wire 209. Further, the semiconductor chip 201 includes a molding resin 211.
Sealed.

[0006] The PBGA thus manufactured has the characteristics that it is small and thin, and can realize multiple terminals and high-density wiring.

Further, in order to improve the electrical characteristics of the above-mentioned PBGA, a PBGA having a multilayer structure is widely used.

However, in such a PBGA,
Since a material having relatively low thermal conductivity such as BT resin and FR-4 is used for the insulating layer, there is a problem that heat dissipation is poor.

In order to solve such a problem, Japanese Patent Application Laid-Open No. 7-321250 proposes a ball grid array integrated circuit package (stacked PBGA) having a heat conductor. FIG. 8 shows the configuration of this ball grid array integrated circuit package.

Referring to FIG. 8, a cavity (recess) C is provided in the semiconductor chip mounting portion of the laminated PBGA.
The solder balls 20 are formed on the same layer as the wiring layer (conductor layer) 231a.
5 is formed. Wiring layer 23
A metal plate (heat radiating plate) 203 is bonded to the entire surface on the side opposite to 1a. Such a structure is called a cavity down structure.

Since the semiconductor chip 201 is directly bonded to the metal plate 203 exposed from the wiring layer 231a, heat of the semiconductor chip 201 is directly radiated to the metal plate 203. Therefore, a semiconductor chip with higher heat generation can be mounted.

A ground (G) is provided under the wiring layer 231a.
By providing the ND) solid layer 231b, electric characteristics are improved (reduction of inductance, reduction of crosstalk noise, control of characteristic impedance, etc.).

A ring pattern for GND is formed on the wiring layer 231a.
9. The GND ring pattern and the GND solid layer 231b are connected by a copper pattern formed on the side surface of the cavity C. GND
The solid layer 231b is connected to the GND solder pad by a through hole. This through hole is formed by drilling. The wall surfaces of the through holes are plated with copper.

Normally, the semiconductor chip 201 and the wiring layer 231
In order to adjust the height of “a”, a metal ring 233 is stacked between the heat sink 203 and the GND solid layer 231b.

The ball grid array integrated circuit package having the heat conductor (metal plate 203) configured as described above has excellent heat dissipation and electrical characteristics.

[0016]

However, the semiconductor package in the prior art has the following problems.

In order to make the upper surface of the wiring layer higher than the upper surface of the semiconductor chip, it was necessary to insert a metal ring or the like between the build-up wiring layers (FIG. 8). In this case, the number of laminations is further increased by inserting the metal ring, and the cost is increased. Further, when a package is formed by the above method, there is a possibility that peeling may occur between the metal ring and the insulating resin layer, so that there has been a problem that the reliability of the package is reduced.

On the other hand, when the wiring layer is formed of BT resin (FIG. 8), the thickness of the insulating layer is increased, so that it is necessary to increase the wiring width in order to control the characteristic impedance. Further, since the wiring layer is formed by a subtractive method (a method of dissolving and removing a copper foil using a copper-clad laminate as a starting material), the wiring width has been increased. Therefore, for these reasons, it has not been possible to increase the density of the package wiring. As a countermeasure for high density, it is conceivable to laminate wiring layers, but there were problems in terms of cost and reliability as described above.

As a method of solving these problems, a build-up method in which an insulating layer is made thinner and a wiring layer is made finer is effective.
The signal lines on and after the first layer are separated from the ground solid layer and exist above the lower wiring layer. Therefore, in order to adjust the characteristic impedance and to prevent crosstalk with the lower wiring layer, it is necessary to newly provide a solid ground layer. This has the above-mentioned problem because the number of layers further increases.

When no new solid ground layer is provided, the number of stacked layers does not increase as compared with the above case.
Wiring design was complicated, for example, it was necessary to increase the signal line width of the second and subsequent layers for characteristic impedance adjustment, and fine adjustment of wiring was required to prevent crosstalk with the lower wiring layer. .

An object of the present invention is to provide a cavity-down type semiconductor package which can solve the above-mentioned problems.

[0022]

According to one aspect of the present invention, there is provided a cavity-down type semiconductor package comprising: a metal plate having a concave portion for mounting a semiconductor chip; And an insulating layer formed on the insulating layer, and one wiring layer is formed on the insulating layer.

According to the present invention, there is provided a cavity-down type semiconductor package in which cost can be reduced by largely eliminating the number of laminating steps, and wiring design for preventing characteristic impedance adjustment and crosstalk can be facilitated. It becomes possible. Further, delamination can be reduced, and a highly reliable cavity-down type semiconductor package can be provided. Furthermore, since the concave portion is formed in the metal plate, there is an advantage that members such as a metal ring can be omitted.

Preferably, the metal plate is kept at the ground potential. More preferably, the ground terminal of the semiconductor chip and the metal plate are connected by a bonding wire.

More preferably, the insulating layer is formed of a photosensitive resin liquid or a photosensitive resin film.

The use of the photosensitive thin film makes it possible to provide a cavity-down type semiconductor package in which the wiring width can be reduced and the density can be increased.

More preferably, the thickness of the insulating layer is 50 μm.
m or less, the wiring width of the wiring layer is 50 μm or less, and the distance between the wirings of the wiring layer is 50 μm or less.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, one embodiment of the present invention will be described.
A cavity-down type semiconductor package will be described. The cavity-down type semiconductor package according to the present embodiment has a heat sink (metal plate) processed into a concave shape, and a ring shape is formed on one surface of the heat sink by a photosensitive resin (a photosensitive resin liquid or a photosensitive resin film). Has an insulating layer formed thereon. On the surface of the insulating layer, a wiring layer, solder ball mounting pads, and wire bonding pads are formed by plating. Except for the solder ball mounting pad and the wire bonding pad, the surface is protected by the solder resist.

The signal and power supply pads of the semiconductor chip are
The wire is connected to a wire bonding pad formed on the surface of the package.

The GND pad of the semiconductor chip is connected to a heat radiating plate by a wire. The GND solder ball mounting pad is connected to the heat sink through via holes formed in the insulating layer.

The semiconductor chip is die-bonded to the concave portion of the heat sink and is sealed with a mold resin. Also,
A ring dam is provided around the semiconductor chip mounting portion to prevent the mold resin from flowing out.

FIG. 1 is a sectional view showing the structure of a cavity-down type semiconductor package according to one of the embodiments of the present invention.

Referring to the figure, a cavity-down type semiconductor package includes a heat radiating plate (metal plate) 103 in which a concave portion (cavity) C for mounting a semiconductor chip is formed,
An insulating layer 121 formed on the heat sink 103;
One wiring layer 119 is formed over the insulating layer 121.

The heat sink 103 is kept at the ground potential. Then, the ground terminal of the semiconductor chip 101 and the heat sink 103 are connected by bonding wires 109.

The insulating layer 121 is formed of a photosensitive resin liquid or a photosensitive resin film.

The surface of the heat sink 103 on the side on which the semiconductor chip 101 is mounted is chemically roughened in order to improve the adhesion with the insulating layer 121.

An insulating layer 121 made of a photosensitive resin is formed on the outer periphery of the heat sink 103. Also, the insulating layer 1
On the surface of 21, a wiring layer 119 formed by plating is provided. The wiring layer 119 includes the semiconductor chip 10
A wire bonding pad for connecting the package 1 to the package with a wire 109 and a solder pad for mounting the package on a PCB are formed.

The heat radiating plate 103 is formed by the G of the semiconductor chip 101.
It is connected to the ND pad by a wire and serves as a good GND conductor for the signal trace formed on the wiring layer 119.
The insulating layer 121 has a G layer formed on the wiring layer 119.
Vias 117 for electrically connecting the ND solder pads and the heat sink 103 are formed.

The surface of the wiring layer 119 excluding the wire bonding pad portion and the solder pad portion is coated with a solder resist 115 for preventing a solder flow when the solder ball 105 is mounted.

After being mounted on the package, the semiconductor chip 101 is connected to the package by wires 109. Then, the semiconductor chip 101 is molded with a resin (mold resin) 111. The package has a ring-shaped dam 11 for preventing the flow of the mold resin.
3 are provided.

FIG. 2 shows the semiconductor chip 101 and the wiring layer 119 in the cavity-down type semiconductor package of FIG.
FIG. 6 is a plan view showing the relationship with FIG. 3 is a plan view of a solder pad portion of the cavity-down type semiconductor package.

Referring to FIG. 2, wiring layer 119 includes a signal line 119a and a power supply line 119b. Each terminal of the semiconductor chip 101 is connected to a pad of the wiring layer 119 by a wire 109. In addition, the semiconductor chip 10
One GND terminal is connected to the heat sink 103 by a wire 109.

Referring to FIG. 3, solder pad 123 is exposed by solder resist opening 131. A signal trace 119a is provided between the solder pads 123. Here, between the solder pads 123, 6
The signal trace 119a is provided.

When a circuit is formed by etching as in the prior art, L / S = 80.
/ 50 μm is the limit, whereas in the present embodiment, since the circuit is formed by the plating method, L / S =
It is possible to increase the density to about 40/40 μm.

For example, assuming that a semiconductor chip of about 10 × 10 mm is mounted on a package, the PBGA of the prior art can handle only up to about 300 I / Os, whereas the PBGA of the present embodiment can handle only about 300 I / Os.
Then, the number of I / Os can be about 500.

FIG. 4 is a view for explaining a manufacturing process of the cavity-down type semiconductor package according to the present embodiment.

First, as shown in (A), one surface of the metal plate 103 formed into a concave shape by press working is roughened by using microetching, rough plating, or the like.

Next, as shown in (B), a photosensitive liquid resin is applied to the surface of the roughened metal plate. Thereby, the insulating layer 121 is formed. In forming the insulating layer, a photosensitive resin sheet may be pressed.

Next, as shown in (C), by performing exposure and development, unnecessary resin in the cavity C portion is removed, and the via 117 is placed at a predetermined position.
To form Desmearing is performed to clean the cavity C and the bottom metal surface of the via 117.

Next, as shown in (D), wiring is formed and the via is plated by a wiring forming process using a known plating method such as a semi-additive method or a full-additive method.

Next, as shown in (E), a solder resist 115 is applied to the surface of the wiring layer to protect the wiring. Then, excess solder resist applied to the wire bonding pad portion and the solder pad portion by exposure and development is removed.

Next, as shown in (F), a dam 113 for a mold resin is formed at a predetermined position. In this manner, a cavity-down type semiconductor package can be manufactured.

In the above-described embodiment, the metal plate is formed into a concave shape by press working. However, as shown in FIG. 5, the metal sheet 103a having holes C1 and C2 previously formed thereon is formed of a resin layer. 103b through the metal sheet 10
A metal plate having a cavity C whose cross-sectional shape is as shown in FIG. 6 may be formed by bonding to 3c, and this may be used.

According to the semiconductor package of this embodiment, since the semiconductor chip is directly mounted on the heat sink,
There is an advantage of being excellent in heat dissipation. Further, since the heat sink is processed into a concave shape, there is an advantage that the height between the semiconductor chip and the wire bonding pad can be easily adjusted.

The GND pad of the semiconductor chip is directly connected to a heat radiating plate by a wire. Therefore, the wiring density of signal traces and power traces formed on the surface layer of the semiconductor package can be improved. Further, since the heat sink acts as a good GND conductor for the signal trace on the surface layer, the characteristic impedance of the signal trace can be controlled, and countermeasures such as crosstalk noise can be taken.

Further, since the thickness of the heat radiating plate is larger than that of the solid layer, the resistance of GND can be further reduced, and the power supply voltage drop can be further reduced.

Further, since the surface wiring layer is formed by plating, the wiring density can be increased as compared with the conventional BGA package in which the wiring layer is formed by etching. Therefore, there is also an advantage that it is not necessary to perform multi-layering and the manufacturing cost can be reduced.

The insulating layer (the insulating layer 12 in FIG. 1)
The layer thickness of 1) is 50 μm or less, the wiring width of the wiring layer (the wiring layer 119 in FIG. 1) is 50 μm or less, and the distance between the wiring layers is 50 μm or less. Desirable from a viewpoint.

It should be noted that the embodiments disclosed this time are merely examples in all respects and are not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a cavity-down type semiconductor package according to an embodiment of the present invention.

FIG. 2 is a plan view for explaining connection between a semiconductor chip and a wiring layer of the package of FIG. 1;

FIG. 3 is a plan view showing a configuration of a solder pad portion of the package of FIG.

FIG. 4 is a cross-sectional view for explaining a manufacturing process of the package of FIG. 1;

FIG. 5 is a perspective view for explaining another method for forming a heat sink.

FIG. 6 is a sectional view of a heat sink manufactured by the process of FIG. 5;

FIG. 7 is a cross-sectional view illustrating a configuration of a conventional PBGA.

FIG. 8 is a cross-sectional view showing a configuration of a conventional ball grid array integrated circuit package.

[Explanation of symbols]

 Reference Signs List 101 semiconductor chip 103 heat sink (metal plate) 105 solder ball 107 wire bonding pad 109 bonding wire 111 mold resin 113 dam 115 solder resist 117 via 119 wiring layer 121 insulating layer C cavity (recess)

Continued on the front page (72) Inventor Toshige Yamamoto 1-8 Fuso-cho, Amagasaki-shi, Hyogo Sumitomo Metal Industries, Ltd. Electronics Technology Research Laboratory F-term (reference) 4M109 AA01 BA04 CA06 DB03 DB06 GA05

Claims (5)

[Claims] 1. A semiconductor device comprising: a metal plate having a recess for mounting a semiconductor chip; and an insulating layer formed on the metal plate, wherein one wiring layer is formed on the insulating layer. A cavity-down type semiconductor package. 2. The metal plate is maintained at a ground potential.
The cavity-down type semiconductor package according to claim 1. 3. The cavity-down type semiconductor package according to claim 1, wherein a ground terminal of the semiconductor chip and the metal plate are connected by a bonding wire. 4. The cavity-down type semiconductor package according to claim 1, wherein said insulating layer is formed of a photosensitive resin liquid or a photosensitive resin film. 5. The semiconductor device according to claim 1, wherein the thickness of the insulating layer is 50 μm or less, the wiring width of the wiring layer is 50 μm or less, and the distance between the wirings of the wiring layer is 50 μm or less. 3. The cavity-down type semiconductor package according to 1.