JP2003163240A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of cracks in a semiconductor device with a three-dimensional wiring structure where a semiconductor chip is buried between several substrates. <P>SOLUTION: In the semiconductor device 1, which comprises several substrates (a bare substrate 10, a window frame substrate 11, and an upper substrate 12) where conductor patterns are formed and the semiconductor chip 2 buried between several substrates, a convexoconcave part 2b is formed on the surface of the semiconductor chip 2. In addition, in a method for manufacturing the semiconductor device where the semiconductor chip is buried between several substrates, the convexoconcave part is formed on the surface of the semiconductor chip 2, and then the semiconductor chip 2 is buried via a resin between several substrates (the bare substrate 10, the window frame substrate 11, and the upper substrate 12). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip is embedded between a plurality of substrates on which conductor patterns are formed, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in order to meet the demands for downsizing and multi-functionalization of electronic equipment, high density mounting of electronic circuits has been actively carried out. For high-density mounting of such electronic circuits,
A so-called surface mounting method in which parts such as resistors, coils, and capacitors are mounted on the surface of a printed wiring board has become common.

Specifically, flip-chip mounting using a flip-chip which is a leadless semiconductor chip electrically and mechanically connected to a substrate by using a conductive bump, or die-bonding the semiconductor chip directly onto a printed circuit board. , Wire bond, COB (Chip On Board) which is resin-sealed and mounted together with other components.

Further, there is three-dimensional mounting as a method for realizing higher density mounting. In three-dimensional mounting, electronic components are not mounted only on the surface of the printed wiring board like surface mounting, but the mounting density is increased by embedding a semiconductor chip inside the base material such as resin that constitutes the printed wiring board. It is a technology. In other words, in surface mounting, the base material forming the printed wiring board becomes a dead space, and by arranging the semiconductor chip in this portion, higher density mounting than surface mounting is realized.

Since the surface of the semiconductor device formed by such three-dimensional mounting is flat, electronic parts such as semiconductor chips can be mounted also on this surface. A normal reflow method is used to mount electronic components on the surface. This reflow method is a state in which cream solder is applied on the electric wiring land of the board, and the terminals of electronic components such as semiconductor chips are mounted in contact therewith, and the solder is melted by heating above the melting point of the solder. It is a method of physically and electrically connecting electronic components by solidifying.

[0006]

However, a semiconductor device formed by three-dimensional mounting in which semiconductor chips and the like are embedded between a plurality of substrates has a problem that the resistance to bending and thermal expansion is weaker than that of the surface mounting semiconductor device. is there. For example, due to external stress or thermal stress, cracks are likely to occur in the bonding portion between the semiconductor chip embedded between the substrates and the substrate. That is, cracks occur due to high temperature steam explosion due to moisture absorption of resin used for joining the semiconductor chip and the substrate, breakage due to difference in thermal expansion coefficient between the semiconductor chip and the substrate, stress concentration on the semiconductor chip in the deformed substrate, etc. The problem of being easy arises.

[0007]

The present invention has been made to solve the above problems. That is, the present invention is a semiconductor device including a plurality of substrates on which a conductor pattern is formed and a semiconductor chip embedded between the plurality of substrates, in which an uneven portion is formed on the surface of the semiconductor chip. is there.

Further, in this method of manufacturing a semiconductor device, after the unevenness is formed on the surface of the semiconductor chip, the semiconductor chip is embedded between a plurality of substrates with a resin interposed therebetween.

In the present invention as described above, since the uneven portion is formed on the surface of the semiconductor chip, when the semiconductor chip is embedded between a plurality of substrates and bonded with resin or the like, the resin enters the uneven portion. Thus, the adhesion between the semiconductor chip and the substrate can be improved.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to this embodiment, in which (a) is a completed view,
(B) is an exploded view. That is, the semiconductor device 1 according to the present embodiment is configured to stack a plurality of substrates to form a three-dimensional wiring and to embed the semiconductor chip 2 between the plurality of substrates to realize high-density mounting. is there.

As the plurality of substrates in the semiconductor device 1 of this embodiment, the bare substrate 1 on which the semiconductor chips 2 are mounted is used.
0, a window frame substrate 11 having an opening for fitting the semiconductor chip 2 substantially in the center, and an upper substrate 12 attached to the uppermost surface. Further, these substrates are adhered to each other by a prepreg 13 made of a thermosetting resin.

Of the substrates, the bare substrate 10 is the mounting substrate 10
a and the lower substrate 10b are bonded together, and the bumps 2a of the semiconductor chip 2 are mounted on the mounting substrate 10a.
A metal bump B is formed to obtain a connection between a pad (not shown) connected to the lower substrate 10b. Further, the lower substrate 10b is provided with a metal bump B for obtaining a connection with the mounting substrate 10a, and the lower surface is provided with an electrode land L for obtaining a connection with the outside.

The window frame substrate 11 is provided with an opening that is substantially the same as the outer shape of the semiconductor chip 2 to be embedded, and
Electrode lands L for connecting to the metal bumps B of the bare substrate 10 and the metal bumps B of the upper substrate 12 are formed.

The upper substrate 12 is formed with metal bumps B for connecting to the electrode lands L of the window frame substrate 6, and the surface thereof has electrode lands for connecting the surface-mounted electronic components 20. L is provided.

The prepreg 13 is formed by semi-curing a thermosetting resin into a plate shape, and if necessary, electrode lands L for connecting to an adjacent substrate are formed.

In the semiconductor device 1 of this embodiment in which a plurality of such substrates are stacked via the prepreg 13 to form a three-dimensional wiring structure, the semiconductor chip 2 embedded between the substrates is provided with the uneven portion 2b. There is a feature in that.

Concavo-convex portion 2b on the surface of the semiconductor chip 2
Has a surface roughness (10-point average roughness) of 0.1 μm or more,
It is 0.5 μm or less. By making the surface roughness 0.1 μm or more, the surface of the semiconductor chip 2 and the prepreg 1
The contact area with the semiconductor chip 3 is increased, and the adhesion between the semiconductor chip 2 and the substrate can be increased.

In the conventional semiconductor device, a problem occurs that a crack is generated between the semiconductor chip embedded between the substrates and the substrate, but in the semiconductor device 1 of this embodiment, the adhesiveness between the semiconductor chip 2 and the substrate is high. Therefore, even if external stress or heat stress is applied, the semiconductor chip 2
A crack is not generated between the substrate and the substrate, and a highly reliable device can be configured.

Next, a method of manufacturing the semiconductor device 1 of this embodiment will be described in order. First, as shown in FIG. 2, the uneven portion 2b is formed on the surface of the semiconductor chip 2. This uneven portion 2b
As a method of forming the
When polishing (the surface on which a is not formed), for example, # 6
Polishing is performed at a pressure of 00 or less to form the uneven portion 2b having a predetermined roughness.

This polishing is performed in a wafer state when the semiconductor chip 2 is formed. Normally, by polishing with # 2000, the surface roughness is 0.01 μm in 10-point average roughness.
Is about 0.02 μm. In the present embodiment, by performing this polishing at # 600 or less (or finishing only by rough polishing), the 10-point average roughness is 0.1 μm or more and 0.1.
The uneven portion 2b of 5 μm or less is formed.

Next, as shown in FIG. 3, the bare substrate 10,
A predetermined conductor pattern, electrode lands L and metal bumps B are formed on the window frame substrate 11 and the upper substrate 12. Then, the semiconductor chip 2 is mounted on the bare substrate 10. Then, the window frame substrate 11 is stacked on the bare substrate 10 via the prepreg 13, and the upper substrate 1 is placed on the window frame substrate 11 via the prepreg 13.
Stack two. At this time, the semiconductor chip 2 is fitted into the opening of the window frame substrate 11.

Next, as shown in FIG. 4, the bare substrate 1
0, the window frame substrate 11, and the upper substrate 12 are heated and pressure-contacted in a state of being overlapped with each other via the prepreg 13. Prepreg 13
Is melted by this heating and then thermally cured to physically connect the superposed substrates.

When the prepreg 13 is heated, the gap between the window frame substrate 11 and the semiconductor chip 2 is filled, and the metal bumps B provided on each substrate are connected to the prepreg 1.
3 and the electrode lands L of the opposing substrate are contacted. The prepreg 13 also comes into close contact with the uneven portion 2b of the semiconductor chip 2 and firmly connects the semiconductor chip 2 and the substrate. As a result, the semiconductor device 1 of this embodiment is completed.

After the semiconductor device 1 of this embodiment is completed, as shown in FIG. 5, even if the electronic component 20 for surface mounting is mounted on the electrode land L provided on the surface of the upper substrate 12. Good. A normal reflow method is used for the surface mounting of the electronic component 20, but cracks occur between the semiconductor chip and the substrate because the semiconductor chip 2 and the substrate are firmly connected even when heated during reflow. There is no such thing.

FIG. 6 is a diagram for explaining the results of a moisture absorption reflow test of a semiconductor device in which a semiconductor chip is embedded between substrates. Here, the surface roughness is the 10-point average roughness of the surface of the semiconductor chip, and the rate of occurrence of peeling is the ratio of the number of peeled samples to the total number of samples that have undergone the moisture absorption reflow test. Further, Rissho's epoxy ES3305H is used as the prepreg of the configured semiconductor device.

That is, when the surface roughness is 0.01 μm (conventional example), the incidence of peeling (peeling between the semiconductor chip and the substrate) is about 48%, whereas the surface roughness is In the case of 0.1 μm or more and 0.5 μm or less (the present embodiment), the rate of occurrence of peeling is very small, 1% to 7%. On the other hand, if the surface roughness exceeds 0.5 μm, cracks may occur in the semiconductor chip manufacturing process, and
The handling property when vacuum-sucking a semiconductor chip deteriorates.

Therefore, it is desirable that the unevenness on the surface of the semiconductor chip has a 10-point average roughness of 0.1 μm or more and 0.5 μm or less.

The uneven portion 2b on the surface of the semiconductor chip 2
May be wholly or partially. Further, the uneven portion 2b can be formed by the following method other than polishing. That is, a hole (recess) is formed on the surface of the semiconductor chip 2 by a drill (special carbide drill),
Irregularities may be formed by irradiating the surface of the semiconductor chip 2 with a laser beam from a YAG laser or the like, or may be formed by chemical treatment with an etching solution.

In the above embodiment, the bare substrate 10, the window frame substrate 11 and the upper substrate 12 are stacked as substrates, but the present invention is applicable to the case where other substrates are stacked. The same effect can be obtained by providing the uneven portion 2b on the surface of the semiconductor chip 2 built in between.

[0030]

As described above, the present invention has the following effects. That is, even with a three-dimensional wiring structure in which a semiconductor chip is embedded between a plurality of substrates, it is possible to suppress the occurrence of cracks between the semiconductor chip and the substrate due to external stress or thermal stress, and to provide a highly reliable semiconductor device. It becomes possible.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to this embodiment.

FIG. 2 is a schematic perspective view illustrating a state of a semiconductor chip.

FIG. 3 is a schematic cross-sectional view illustrating superposition of substrates with a semiconductor chip in between.

FIG. 4 is a schematic cross-sectional view showing a superposed state of substrates in which semiconductor chips are embedded.

FIG. 5 is a schematic cross-sectional view illustrating a state where surface mounting is performed.

FIG. 6 is a diagram illustrating a result of a moisture absorption reflow test of a semiconductor device in which a semiconductor chip is embedded between substrates.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor chip, 2b ... Concavo-convex part, 1
0 ... Bare substrate, 10a ... Mounting substrate, 10b ... Lower substrate, 11 ... Window frame substrate, 12 ... Upper substrate, 13 ... Prepreg, B ... Metal bump, L ... Electrode land

Claims (7)

[Claims] 1. A semiconductor device comprising a plurality of substrates on which a conductor pattern is formed and a semiconductor chip embedded between the plurality of substrates, wherein an uneven portion is formed on the surface of the semiconductor chip. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the unevenness has a surface roughness of 0.1 μm or more and 0.5 μm or less in 10-point average roughness. 3. A method of manufacturing a semiconductor device, which comprises embedding a semiconductor chip between a plurality of substrates on which a conductor pattern is formed, the method comprising: forming irregularities on a surface of the semiconductor chip; A method for manufacturing a semiconductor device, characterized by embedding a resin between the substrates. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the unevenness is formed on the surface of the semiconductor chip by polishing. 5. The method for manufacturing a semiconductor device according to claim 3, wherein the unevenness is formed on the surface of the semiconductor chip by drilling. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the unevenness is formed on the surface of the semiconductor chip by irradiation with a laser beam. 7. The method for manufacturing a semiconductor device according to claim 3, wherein the unevenness is formed on the surface of the semiconductor chip by a chemical treatment with an etching solution.