JP3196758B2 - Lead frame, method of manufacturing lead frame, semiconductor device, and method of manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame which is connected to an electrode of a semiconductor chip by an inner lead of a lead and is connected to an electrode of a wiring board or the like via a protruding electrode by an outer lead. The present invention relates to a semiconductor device using such a lead frame and a method for manufacturing such a semiconductor device.

[0002]

2. Description of the Related Art FIGS. 7 and 8 show a structure in which a semiconductor chip can be connected to a wiring board or the like via an organic substrate provided with projecting electrodes such as solder balls. First, the conventional example shown in FIG. 7 will be described. In the drawing, a is a multilayer organic wiring board of about 2 to 6 layers using an organic material, and a semiconductor chip b is mounted on the surface thereof. c is a wiring film formed on the surface of the multilayer organic wiring board a, for example, a connect wire d made of gold.
Is connected to the electrode of the semiconductor chip b via the.

Reference numeral e denotes a solder ball formed on the back surface of the multilayer organic wiring board a, which is electrically connected to the wiring film c via a through hole. f is a solder resist film, g is a sealing resin, and h is a wiring board. The conventional example shown in FIG. 7 uses a multi-layer organic wiring board a, mounts a semiconductor chip b on one main surface thereof, seals with resin, and forms a solder ball e as a protruding electrode on the other surface. This solder ball e is connected to the wiring board g. Next, the conventional example shown in FIG. 8 will be described. In this example, a multilayer organic wiring board a having a device hole i is used, and an outer lead of a TAB tape k based on polyimide j is connected to a wiring film on the surface thereof, and the above-mentioned inner lead is connected to an inner lead. The electrode of the semiconductor chip b located in the device hole i is bonded. The other points are substantially the same as the conventional example shown in FIG. The multilayer organic wiring board a is often referred to as a ball grid array (BGA) because a large number of solder balls are arranged in a grid.

[0004]

FIG. 7 shows a structure in which a connection wire d made of gold is provided between an electrode of a semiconductor chip b and a wiring film c of a multilayer organic wiring board a called BGA. The problem is that the parasitic resistance inevitably increases due to the connection, and the wire bonding process is required, which takes a considerable amount of time, which contributes to an increase in cost. is there. In addition, since the semiconductor chip b is mounted on one main surface of the multilayer organic wiring substrate a and sealed with resin, it is difficult to meet the demand for thinning, which tends to increase the mounting of the semiconductor device.

[0005] The structure shown in FIG. 8 can be said to substantially eliminate the above-mentioned disadvantages of the structure shown in FIG. 7. That is, the semiconductor chip b
Is directly connected to the wiring film c of the multilayer organic wiring board a without the intermediary of the connect wire d, so that the electric resistance can be reduced by that amount, and the wire bonding step is not required, so that the cost is reduced accordingly. In addition, since the semiconductor chip b can be accommodated in the device hole b, it is relatively easy to cope with the thinning which is often strongly required for mounting the semiconductor device. But TA
There is a problem that the process of bonding the B tape k to the multilayer organic wiring substrate a is relatively complicated, and the positioning accuracy is not sufficient at least at the present technical level, and the occurrence rate of the positioning failure is high. In particular, since the TAB tape k and the like are deformed by high heat (480 ° C.), the deformation is one of the causes of deteriorating the positioning accuracy.

The disadvantages common to the conventional examples shown in FIGS. 7 and 8 are that the manufacturing process of the multilayer organic wiring board a is complicated, the price is extremely high, and the multilayer organic wiring board a is warped. Therefore, the warp failure rate is so high that it cannot be ignored, and there is no possibility that moisture may enter from the side surface of the multilayer organic wiring board a.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and can meet the demand for lowering the cost and thickness of a semiconductor device. It is another object of the present invention to provide a semiconductor device using such a lead frame and a method for manufacturing the same.

[0008]

According to a first aspect of the present invention, there is provided a lead frame, wherein a plurality of leads, the plurality of leads form a flat surface with each of the leads and itself, and one end of each of the leads is covered. A solder resist embedded so as to be exposed.

According to a second aspect of the present invention, there is provided a method for manufacturing a lead frame.
A large number of leads are formed on the surface of the lead forming substrate via an etching stop layer, and an insulating protective film having a device hole is adhered to the surface of each lead on the side opposite to the lead forming substrate. The formation region of the lead is removed by etching from the back side, the etching stop layer is etched using the lead as a mask, and an external electrode is formed on the outer lead of each lead.

According to a third aspect of the present invention, the semiconductor device includes a plurality of leads,
And a lead frame including a solder resist in which the plurality of leads form a flat surface with each of the leads and itself and one end of each of the leads is embedded so as to protrude;
A semiconductor chip having electrodes connected to one ends of the plurality of leads protruding from the solder resist is provided.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a lead frame is formed by the method of the second aspect, and a semiconductor element is connected to the lead frame.

[0012]

According to the lead frame of the first aspect, the plurality of leads are embedded in the solder resist and a flat surface is formed by the plurality of leads and the solder resist. This makes it easy to perform the bonding operation and enhances the heat dissipation to the upper side of the semiconductor element. Also,
Since a multi-layer organic wiring board is not used, the cost can be reduced, and since no TAB tape is used, the TAB tape is not used.
No complicated process of bonding the tape to the wiring board is necessary. Therefore, there is no possibility that the yield may be reduced due to misalignment of the TAB tape.

According to the method for manufacturing a lead frame of the present invention, since the leads are formed on the surface of the lead forming substrate via the etching stop layer, the leads can be formed in a fine pattern. In addition, the presence of the lead forming substrate can prevent deformation during the manufacture of the lead frame.

After the leads are formed, electrodes are formed on the leads by electrolytic plating using the solder resist layer as a mask. Therefore, an etching stop layer is used to apply a potential necessary for electrolytic plating to the portions where the electrodes are to be formed. And the formation of external electrodes by electrolytic plating becomes possible. Therefore, it is not necessary to replace the external electrode material at each external electrode forming portion, and the efficiency of the external electrode forming operation can be increased, and the production cost can be reduced. Therefore, a lead frame can be obtained at low cost.

According to the third aspect of the present invention, there is provided the semiconductor device according to the first aspect.
Since the semiconductor element is connected to the lead frame of (1), the effect of the lead frame of claim 1 can be enjoyed.

According to the method of manufacturing a semiconductor device of the fourth aspect, the semiconductor device is manufactured by connecting a semiconductor element to the lead frame after manufacturing the lead frame by the method of manufacturing the lead frame of the second aspect. The effect of the method for manufacturing a lead frame of item 2 can be enjoyed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. FIG. 1 is a cross-sectional view showing an example of a lead frame manufactured by one embodiment (the embodiment shown in FIGS. 2 and 3) of the lead frame manufacturing method of the present invention. In the drawing, reference numeral 1 denotes an insulating protective film, which is a two-layer film of a polyimide film 1a and an adhesive film (for example, made of an epoxy resin or polyimide having a TG of 200 ° C. or lower) 1b. When the polyimide film 1a itself is used as an adhesive film, it is a single layer. Reference numeral 2 denotes a device hole of the insulating protective film 1. Reference numeral 3 denotes a lead formed on the surface of the insulating protective film 1, which is formed by, for example, electrolytic copper plating. The patterning is carried out by selective plating using, for example, a photomask. The line width is, for example, 20 to 100 μm, the pitch is, for example, 50 to 100 μm (the limit of the pitch is 100 μm in the case of a conventional type in which a lead and a chip electrode are connected by a gold wire), and the thickness is, for example, a line. 0.7 of width
２．０2.0 times, for example, 30 μm.

Reference numeral 3i denotes an inner lead of the lead 3, which protrudes from the surface of the insulating protective film 1 onto the device hole 2, and
The tip is joined to the electrode of the semiconductor chip 4.
A semiconductor device is constituted by the present lead frame and the semiconductor chip 4 in which electrodes are joined to the inner leads 3i. The bonding is performed by, for example, an ultrasonic method with aluminum coating on the electrode, or a gold / tin eutectic gag bonding with tin coating. 3o is an outer lead of the lead 3. Reference numeral 5 denotes a reinforcing plate, which is adhered to the back surface of the insulating protective film 1, that is, the surface on the side opposite to the lead, and is made of, for example, a metal plate such as copper or a ceramic sheet. A metal plate such as a copper plate or a ceramic sheet has a rigidity and thus plays a role as a reinforcing plate. However, since it has a better thermal conductivity, it also plays a role as a heat radiating plate and is therefore most suitable as a reinforcing plate. Also, for weight reduction,
Instead of a single layer structure, a laminated structure may be considered.

Reference numeral 6 denotes a solder resist selectively formed on the surface of the insulating protective film 1 on which the leads 3 are formed. The occurrence of a solder bridge between adjacent leads when forming a solder ball (7) described below. It plays a role of prevention and insulation between electrodes and between leads. Specifically, for example, 10 to 50 μm
It is made of a polyimide film or an epoxy resin film having a thickness of about m. The solder resist 6 is patterned so that an opening is formed in a portion where the solder ball (7) is to be formed.

Reference numeral 7 denotes a solder ball which forms a protruding external electrode formed on the outer lead 3o, and is connected to a wiring film of a wiring board on which the semiconductor device is mounted. The solder balls 7 are formed by, for example, performing flux coating on the surface of the insulating protective film 1 on which the leads 3 and the solder resist 6 are formed, and then applying a ball-shaped solder prepared in advance to each solder ball. The solder may be placed on the formation position and then the solder may be melted by reflow. Alternatively, solder plating may be performed by electroplating on the exposed portion of the outer lead 3o using the solder resist 3 as a mask. You may go. Also, electroplating metal such as nickel or copper,
It may be used as a core and plated with solder thereon.

Reference numeral 8 denotes a sealing resin. The sealing with the resin 8 may be performed by a transfer molding method using a mold or a potting method using a dispenser. According to the embodiment shown in FIG. 1, the back surface of the semiconductor chip 4 is not exposed to the back surface of the resin 8, that is, the back surface of the package, but the portion 8 of the resin 8 lower than the back surface of the semiconductor chip.
The shape of a may be cut out to expose the back surface of the semiconductor chip to enhance heat dissipation. Further, a heat radiation fin may be adhered to the back surface to enhance heat radiation.

Further, the insulating protective film 1 is bonded to the upper surface of the dish-shaped reinforcing plate 5 having good heat dissipation, and the semiconductor chip 4 is bonded to the inner bottom surface of the reinforcing plate 5 (see FIG. 4).
Various modifications may be conceived, such as joining of each electrode of the semiconductor chip 4 to the inner lead of each lead, that is, inner lead bonding may be performed.

According to the lead frame shown in FIG. 1, the lead 3 composed of a single-layer wiring film on the surface of the insulating protective film 1 is formed by the electrodes of the semiconductor chip 4 and the projecting electrodes without using an organic multilayer wiring substrate. Since it is interposed between certain solder balls 7,
The price can be reduced. In addition, since the lead has a single layer, moisture does not intrude between the layers, so that the moisture resistance and the water resistance can be improved, and the reliability is further increased. Then, the insulating protective film 1 is formed in the device hole 2
Since the semiconductor chip is placed in the device hole 2, the thickness can be reduced.

Also, since no TAB tape is used,
No complicated process of bonding the B tape to the wiring board is required. Therefore, there is no possibility that the yield may be reduced due to misalignment of the TAB tape. Further, according to this lead frame, since the reinforcing plate 5 is bonded to the back surface of the insulating protective film 1, the lead frame is deformed or damaged during the manufacturing process of the lead frame, the mounting of the semiconductor chip 4, and the resin sealing process. Can be prevented.

FIGS. 2A and 2B and FIGS.
(H) is a perspective view and a sectional view showing an example of the method for manufacturing a lead frame as shown in FIG. 1 (first embodiment of the lead frame of the present invention) in the order of steps ((A) to (H)). . (A) A base 9 is prepared for forming a lead frame. The base 9 has an aluminum film 1 having a thickness of, for example, about 3 μm on a surface of a thin plate (hereinafter, referred to as “copper substrate”) 10 made of, for example, copper having a thickness of, for example, about 150 μm.
1 is formed, and a thin copper film 12 having a thickness of, for example, about 2 μm is formed on the surface of the aluminum film 11 (a cross-sectional structure is shown in the lower right part of FIG. 2A).

The aluminum film 11 is formed later on the copper substrate 10.
Serves as an etching stop film for preventing the surface side of the base 9 from being etched when etching is performed. The thin copper film 12 serves as a base for copper plating for forming the leads 3, and good plating is difficult without it. Incidentally, the copper substrate 10 corresponds to a lead forming substrate referred to in the claims. The lead forming substrate does not become a lead itself and is eventually unnecessary, but it is excessively necessary as a substrate for forming a very thin lead and thereafter as a frame. It is called a forming substrate.

Next, the lead 3 made of copper is selectively plated on the surface of the base 9, that is, the surface of the thin copper film 12.
To form The selective plating is performed by selectively covering the surface with a resist film or the like and performing electrolytic plating using the resist film as a mask. As described above, when leads are formed by selectively plating copper on the base 9 made of metal by electrolytic plating, fan patterns can be formed while improving the film quality of the leads as compared with the TAB tape leads. .

Then, the base 9 is selectively masked on both sides thereof with a resist film, and is etched about 1/2 of its thickness from both sides in this state, so that holes necessary for convenience of manufacture or for preventing deformation are formed. A slit is formed in the base 9 and a portion of the copper substrate 10 corresponding to the lead 3 formation region is half-etched. FIG. 2A shows a state after the completion of the etching.

(B) Next, as shown in FIG. 2B, a solder resist 6 is selectively formed on the surface of the base 9 on which the leads 3 are formed. Specifically, the outer lead 3
An o is formed so that an opening is formed in a portion where the solder ball (7) is to be formed and the tip of the inner lead 3i is not covered. (C) Next, as shown in FIG. 3 (C), solder balls 7 are formed on the tips of the outer leads 3o of the leads 3 (opening of the solder resist 6). The formation of the solder balls 7 can be performed by an electrolytic plating method, and the working efficiency can be increased. Because base 9
(A three-layer laminated plate including a copper substrate 10 serving as a lead forming substrate, an aluminum film 11 serving as an etching stop layer, and a thin copper film 12 serving as a plating base for forming leads) is made of a conductive material, Base 9 without doing
Since the potential required for electrolytic plating can be applied to each solder ball forming portion via itself, it is possible to form solder balls by electrolytic plating without forming a circuit for electrolytic plating in particular, and therefore, This is because the troublesome work of replacing the ball-shaped solder at each solder ball forming position is not required.

(D) Next, the copper substrate 10 of the base 9 is etched by etching the entire surface of the lead frame with the resist film and selectively masking the rear surface with the resist film. An unnecessary portion of the substrate 10 (mainly, the remaining portion of the half-etched portion) is removed. FIG. 3D shows a state after the etching is completed. (E) Next, using the lead 3 as a mask, the aluminum film 1
Then, the thin copper film 12 is removed by copper etching. As a result, the leads 3 become electrically independent. FIG. 3E shows a state after the completion of both the etchings.

(F) Next, as shown in FIG. 3 (F), a laminate of the insulating protective film 1 and the reinforcing plate 5 is bonded to the surface of the lead frame opposite to the surface on which the solder balls 7 are formed. I do. (G) Thereafter, inner lead bonding is performed, and thereafter, resin sealing is performed. FIG. 3G shows a state after resin sealing. Then, when the surface on which the solder balls 7 are formed faces downward, the state shown in FIG. Note that the order of the step of bonding the laminate of the insulating protective film 1 and the reinforcing plate 5 and the step of inner lead bonding may be reversed.

According to such a method for manufacturing a lead frame, the solder balls 7 serving as projecting electrodes are removed before the step of removing the etching stop layer 11 made of aluminum of the base 9 by etching using the leads 3 as a mask. Since it is formed, the etching stop layer 11 can be used as a path for applying a potential required for electrolytic plating, and thus the formation of the solder balls 7 by electrolytic plating becomes possible. Therefore, it is not necessary to prepare a large number of ball-shaped solders and replace them at the respective solder ball forming portions, and it is possible to increase the efficiency of the solder ball projecting electrode forming operation, thereby reducing the manufacturing cost. Can be.

After the etching of the etching stop layer 11 made of aluminum using the leads 3 as a mask, a multilayer body of the insulating protective film 1 and the reinforcing plate 5 is formed on the leads 3 so that inner lead bonding or resin sealing is performed. Deformation of the lead 3 due to stopping or the like can be prevented by the insulating protective film 1 or the like. Therefore, the lead frame shown in FIG. 1 can be obtained without any trouble.

FIG. 4 is a cross-sectional view for explaining a modification of the method of manufacturing the lead frame shown in FIGS. In this modification, after the step shown in FIG. 3E is completed, as shown in FIG.
The semiconductor chip 4 is chip-bonded on the inner bottom surface of a heat sink (made of, for example, copper) 5 to which is adhered, and the electrodes of the semiconductor chip 4 are joined to the inner leads 3 i of the leads 3. By doing so, the heat dissipation can be made extremely good. In other respects, there is no difference from the manufacturing method shown in FIGS.

FIGS. 5A and 5B are cross-sectional views showing one embodiment of the lead frame of the present invention. FIG. 5A shows a state before the lead bonding of the lead frame, and FIG. This shows the state after lead bonding. Reference numeral 13 denotes a lead, on one surface of which a solder resist 6 is formed, and on an outer lead 13o, a solder ball 7 as a protruding electrode is formed through an opening of the solder resist 6. Numeral 10 denotes a so-called lead frame, which is a so-called lead frame, which is cut off after the completion of inner lead bonding and resin sealing. 4 is an electrode whose inner lead 13i
The semiconductor chip 8 connected to is a sealing resin.

The lead frame is mounted on the semiconductor chip 4 with the sealing resin 8 interposed therebetween, so that the solder balls 7 are located above the semiconductor chip 4.
Accordingly, it is possible to contribute to miniaturization of the semiconductor device.
Since the single-layer leads 13 on the surface of the insulating protective film are interposed between the electrodes of the semiconductor chip 4 and the solder balls 7 without using an organic multilayer wiring board, the cost can be reduced. Also, since no TAB tape is used,
No complicated process of bonding the tape to the wiring board is required. Therefore, there is no possibility that the yield may be reduced due to misalignment of the TAB tape.

Since the plurality of leads 3 are embedded in the solder resist 6 and a flat surface is formed by the plurality of leads 3 and the solder resist 6, the semiconductor element 4 is more closely adhered to the surface. The bonding operation can be easily performed, and the heat radiation to the upper side of the semiconductor element 4 can be improved.

FIGS. 6A to 6E are sectional views showing an example of the method for manufacturing the lead frame shown in FIG. 5 (second embodiment of the lead frame of the present invention) in the order of steps. (A) As shown in FIG. 6A, a base 9 having a three-layer structure in which a thin copper film 13 serving as a lead is formed on the surface of a copper substrate 10 via an etching stop layer 11 made of aluminum.
Prepare (B) Next, as shown in FIG.
The leads 13 are formed by patterning 3 by selective etching.

(C) Next, the solder resist 6 is selectively formed on the surface of the base 9 on which the leads 13 are formed, and then the solder balls 7 are formed by, for example, electrolytic plating. FIG. 6C shows a state after the formation of the solder ball 7. Since the solder balls 7 are formed by the electrolytic plating method, it goes without saying that the efficiency of the forming operation can be improved. (D) Next, the front surface side of the base 9 is entirely masked, and the back surface side is selectively masked, and the copper substrate 10 is etched to remove the portion corresponding to the back surface of the lead formation region. Only the portion corresponding to the lead frame is left.

(E) Thereafter, as shown in FIG. 6E, the etching stop layer 3 is removed by etching. Then, each lead 13 is independent of the other leads. Thus, the semiconductor chip 4 is ready for inner lead bonding. Thereafter, when the inner lead bonding, resin sealing (for example, bonding method or transfer molding method) and the remaining portion of the copper substrate 10 are cut, the assembling is completed.

According to such a method of manufacturing a lead frame, the leads 3 and the positional relationship therebetween can be fixed by the semiconductor chip 4 through the resin 8 by sealing, and the semiconductor chip 4 Acts as a board. The formation of the lead 13 is shown in FIGS.
Similar to the manufacturing method shown in FIG. 4 and the manufacturing methods shown in FIGS. 2 and 3, the thin copper film may be used as an underlayer to perform the electrolytic selective plating method. Further, in each of the above embodiments, the lead of the lead frame may have a multilayer wiring structure such as two layers instead of a single layer wiring structure.

[0042]

According to the lead frame of the first aspect, the plurality of leads are embedded in the solder resist and a flat surface is formed by the plurality of leads and the solder resist. Bonding can be performed more completely, so that the bonding operation can be easily performed, and heat radiation to the upper side of the semiconductor element can be improved. Also, since the organic multilayer wiring board is not used, the price can be reduced, and since no TAB tape is used,
No complicated process of bonding the TAB tape to the wiring board is required. Therefore, there is no possibility that the yield may be reduced due to misalignment of the TAB tape.

According to the method for manufacturing a lead frame of the present invention, since the leads are formed on the surface of the lead forming substrate via the etching stop layer, the leads can be formed in a fine pattern. In addition, the presence of the lead forming substrate can prevent deformation during the manufacture of the lead frame.

After the formation of the leads, the electrodes are formed on the leads by electrolytic plating using the solder resist layer as a mask. Thus, an external electrode such as a protruding electrode can be formed by electrolytic plating. Therefore, there is no need to replace the external electrode material at each external electrode forming portion, and the external electrode forming operation can be performed with high efficiency.
As a result, manufacturing costs can be reduced. Therefore, a lead frame can be obtained at low cost.

According to the semiconductor device of the third aspect, the first aspect
Since the semiconductor element is connected to the lead frame of (1), the effect of the lead frame of claim 1 can be enjoyed.

According to the method of manufacturing a semiconductor device of the fourth aspect, the semiconductor device is manufactured by connecting a semiconductor element to the lead frame after manufacturing the lead frame by the method of manufacturing the lead frame of the second aspect. The effect of the method for manufacturing a lead frame of item 2 can be enjoyed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing an example of a lead frame manufactured by a method for manufacturing a lead frame of the present invention.

FIGS. 2A and 2B show steps (A) and (B) of an example of the method for manufacturing the lead frame shown in FIG. 1 (first embodiment of the method for manufacturing a lead frame of the present invention); It is a perspective view and a sectional view.

3 (C) to 3 (H) show steps (C) to (H) of an example of the method for manufacturing the lead frame shown in FIG. 1 (first embodiment of the method for manufacturing a lead frame of the present invention). It is a perspective view and a sectional view.

FIG. 4 is a cross-sectional view illustrating a modification of the method of manufacturing the lead frame shown in FIGS. 2 and 3.

5A and 5B are cross-sectional views showing one embodiment of the lead frame of the present invention, wherein FIG. 5A shows a state before inner lead bonding, and FIG. 5B shows a state after sealing. Show.

6A to 6E are cross-sectional views showing an example of the method for manufacturing the lead frame shown in FIG. 5 (second embodiment of the method for manufacturing a lead frame of the present invention) in the order of steps.

FIG. 7 is a cross-sectional view showing one conventional example.

FIG. 8 is a sectional view showing another conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Insulating protective film, 2 ... Device hole, 3
··· Lead, 3i ··· Inner lead, 3o ··· Outer lead, 4 ··· Semiconductor chip, 5 ··· Reinforcing plate, 6 ··· Solder resist, 7 ··· Projecting electrode (solder ball), 9: Base, 10: Lead forming substrate (copper substrate), 11: Etching stop layer (aluminum film), 13: Lead

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/60 H01L 23/50 H01L 23/12

Claims (4)

(57) [Claims] An electrode formed on a semiconductor chip is connected to an external power supply.
A lead frame for connecting to a pole, wherein a plurality of leads patterned on the same plane, and the plurality of leads form a flat surface with each of the leads and itself.
And embedded so that one end of each lead protrudes
A lead frame , comprising: a solder resist . 2. A step of forming a large number of leads on a lead forming substrate via an etching stop layer, and forming an opening on a surface of the lead forming substrate on which the leads are formed, on a portion where an external electrode is to be formed. Forming a solder resist that does not cover one end of the lead, forming an electrode on the lead by electrolytic plating using the solder resist as a mask, and forming a solder resist on the back surface of the lead forming region of the lead forming substrate. Etching a remaining portion. A method for manufacturing a lead frame, comprising: 3. A plurality of patterns patterned on the same plane.
The lead and the plurality of leads are flat with each of the leads and itself.
It forms a flat surface and one end of each lead protrudes
A lead frame with embedded solder resist cormorants, characterized by comprising a semiconductor chip connected to the electrode at one end exiting run off from the solder resist of the plurality of leads of the lead frame Semiconductor device. 4. A step of forming a large number of leads on a lead forming substrate via an etching stop layer, and forming an opening on a portion of the lead forming substrate on which leads are to be formed, on a surface on which the leads are formed. Forming a solder resist that does not cover one end of the lead, forming a protruding electrode on the lead by electrolytic plating using the solder resist as a mask, and a back surface of a lead forming region of the lead forming substrate. A method of manufacturing a semiconductor device, comprising: a step of etching a remaining portion of the lead; and a step of connecting one end of each lead to each electrode of a semiconductor chip.