JP2001053194A - Double layer wiring tab tape and manufacturing method thereof - Google Patents

Double layer wiring tab tape and manufacturing method thereof

Info

Publication number
JP2001053194A
JP2001053194A JP22687499A JP22687499A JP2001053194A JP 2001053194 A JP2001053194 A JP 2001053194A JP 22687499 A JP22687499 A JP 22687499A JP 22687499 A JP22687499 A JP 22687499A JP 2001053194 A JP2001053194 A JP 2001053194A
Authority
JP
Japan
Prior art keywords
layer
wiring
polyimide
tab tape
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22687499A
Other languages
Japanese (ja)
Inventor
Gunichi Takahashi
軍一 高橋
Kenji Yamaguchi
健司 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP22687499A priority Critical patent/JP2001053194A/en
Publication of JP2001053194A publication Critical patent/JP2001053194A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To provide a double-layer wiring TAB tape of high reliability, wherein generation of strain due to heat is little, configuration is superior, flexibility in wiring design of BGA, CSP, etc., is high and adhesion to photo solder resist, and in particular, adhesion of a stiffener sticking side are superior, and a manufacturing method of the double layer wiring TAB tape of high productivity and a low cost. SOLUTION: This TAB tape is provided with a polyimide layer 1 of 30-45 μm thickness, a first wiring layer 8 formed on one surface of the polyimide layer 1 by patterning via an adhesive agent layer 4, a second wiring layer 9 formed on the other surface of the polyimide layer 1 by patterning without going through the intermediary of an adhesive agent layer, a bind via 6 formed penetrating the polyimide layer 1, the adhesive agent layer 4 and the second wiring layer 9, a copper plating layer 7, which is formed on the inner surface of the blind via 6 and the surface of the second wiring layer 9 and connects electrically the second wiring layer 9 with the first wiring layer 8, solder balls 26 arranged on a ball pad layer formed on the surface of the copper plating layer 7, and a photo-solder resist layer 10 formed in a region, except the ball pad layer of the second wiring layer 9.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、2層配線TAB
(Tape Automated Bonding)テ
ープ及びその製造方法に関し、特に、CSP(Chip
Scale Package)用およびBGA(Ba
ll Grid Array)用として好適であり、熱
による歪みの発生が少なく、形状性に優れ、BGA・C
SP等の配線の設計における自由度が高く、かつフォト
ソルダレジストとの密着性、特にステフナー貼り付け側
の密着性が良好で信頼性の高い2層配線TABテープ、
及び高生産性かつ低コストの2層配線TABテープの製
造方法に関する。
The present invention relates to a two-layer wiring TAB.
(Tape Automated Bonding) tape and a method of manufacturing the same, particularly, a CSP (Chip)
Scale Package) and BGA (Ba
BGA / C
A highly reliable two-layer wiring TAB tape that has a high degree of freedom in the design of wiring such as SP and has good adhesion to the photo solder resist, particularly good adhesion on the side where the stiffener is attached;
And a method of manufacturing a two-layer wiring TAB tape with high productivity and low cost.

【0002】[0002]

【従来の技術】2層配線のBGA・CSP用TABの製
造方法として、例えば、図3に示すものがある。図3
(イ)及び(ロ)に示すように、2層配線TABテープ
として、接着剤レス2層CCL(Copper C1a
d Laminate)3を用いてフォトプロセスで予
め片面の銅層2にフォトプロセスとエッチングで貫通孔
を形成した後、レーザ加工によって絶縁層であるポリイ
ミドテープ1に貫通孔を形成してブラインドビア6を形
成する。図3(ハ)に示すように、その後ブラインドビ
ア6の内壁をデスミヤ処理後、導電化処理して約8μm
厚さの銅めっき8を施して製造する(例えば、特開昭6
1−176193号公報)。なお、接着剤レス2層CC
L3は、銅箔2の上にポリイミドワニスを塗布し、それ
をヒーターで加熱してポリイミド層1とするキャスティ
ング工程によって製造される。
2. Description of the Related Art FIG. 3 shows an example of a method of manufacturing a TAB for a BGA / CSP having two layers. FIG.
As shown in (a) and (b), as a two-layer wiring TAB tape, an adhesive-less two-layer CCL (Copper C1a) is used.
d Laminate) 3, through holes are formed in the copper layer 2 on one side in advance by a photo process using a photo process and etching, and through holes are formed in the polyimide tape 1 as an insulating layer by laser processing to form blind vias 6. Form. As shown in FIG. 3C, after the inner wall of the blind via 6 is desmeared, the inner wall of the blind via 6 is made conductive to about 8 μm.
It is manufactured by applying a copper plating 8 having a thickness (for example,
1-1176193). In addition, adhesive-less two-layer CC
L3 is manufactured by applying a polyimide varnish on the copper foil 2 and heating it with a heater to form a polyimide layer 1.

【0003】[0003]

【発明が解決しようとする課題】しかし、接着剤レス2
層CCLを用いた従来の2層配線TABテープによる
と、ポリイミド層が50μm程度の厚さになると、ポリ
イミドワニスをヒーターで加熱する時に生じる歪みが大
きくなり、これによって接着剤レス2層CCLに蛇行が
生じるため、搬送時にガイドに引っ掛かることがあり、
また、配線のエッチングパターンにズレが生じることが
ある。エッチングパターンのズレは配線の微細化を妨
げ、配線ピッチを40μm以下にすることが困難にな
る。また、キャスティングによって形成されたポリイミ
ド層は、フォトソルダレジストとの密着性が悪いため、
フォトソルダレジストに接着剤を介してステフナーを貼
付した構造の半導体装置では、フォトソルダレジストと
ポリイミド層の間に剥離が生じて信頼性を低下させる。
また、2層配線のTABテープでは、BGA・CSPの
配線パターン引き回しが限定され、ボールパッド(Ba
ll Pad)数が増加すると、可能な配線パターン引
き回し配線ピッチは40μm以下となり、銅箔層をエッ
チングすることは極めて困難であった。
However, no adhesive is required.
According to the conventional two-layer wiring TAB tape using the layer CCL, when the polyimide layer has a thickness of about 50 μm, the distortion generated when the polyimide varnish is heated by the heater increases, thereby meandering the adhesive-less two-layer CCL. May be caught on the guide during transport,
In addition, the etching pattern of the wiring may be shifted. Misalignment of the etching pattern hinders miniaturization of the wiring and makes it difficult to reduce the wiring pitch to 40 μm or less. Also, the polyimide layer formed by casting has poor adhesion to the photo solder resist,
In a semiconductor device having a structure in which a stiffener is attached to a photo solder resist via an adhesive, peeling occurs between the photo solder resist and the polyimide layer, thereby lowering reliability.
In the case of a TAB tape with two-layer wiring, the wiring pattern of BGA / CSP is limited, and the ball pad (Ba)
When the number of (ll Pad) increases, the possible wiring pitch of the wiring pattern becomes 40 μm or less, and it is extremely difficult to etch the copper foil layer.

【0004】従って、本発明の目的は、熱による歪みの
発生が少なく、形状性に優れ、BGA・CSP等の配線
の設計における自由度が高く、かつフォトソルダレジス
トとの密着性、特にステフナー貼り付け側の密着性が良
好で信頼性の高い2層配線TABテープ、及び高生産性
かつ低コストの2層配線TABテープの製造方法を提供
することにある。
Accordingly, it is an object of the present invention to reduce the occurrence of distortion due to heat, to be excellent in shape, to have a high degree of freedom in designing wiring such as BGA and CSP, and to improve the adhesion with a photo solder resist, particularly, by using a stiffener. An object of the present invention is to provide a highly reliable two-layer wiring TAB tape having good adhesion on the attachment side and a method of manufacturing a two-layer wiring TAB tape with high productivity and low cost.

【0005】[0005]

【課題を解決するための手段】本発明は、上述の課題を
解決するため、下記[1]〜[6]の2層配線TABテ
ープ及びその製造方法を提供する。すなわち、
In order to solve the above-mentioned problems, the present invention provides the following two-layered TAB tape [1] to [6] and a method of manufacturing the same. That is,

【0006】[1] 厚さが30〜45μmのポリイミ
ド層と、前記ポリイミド層の一面に接着剤層を介してパ
ターン化して形成した第1の配線層と、前記ポリイミド
層の他面に接着剤層を介さないでパターン化して形成し
た第2の配線層と、前記ポリイミド層、前記接着剤層及
び前記第2の配線層を貫通して設けたブラインドビア
と、前記ブラインドビアの内面及び前記第2の配線層の
表面に形成して前記第2の配線層を前記第1の配線層に
電気的に接続する銅めっき層と、前記銅めっき層の表面
に形成したボール・パッド層に配設したはんだボール
と、前記第2の配線層の前記ボール・ パッド層を除く領
域に形成したフォトソルダレジスト層を備えてなること
を特徴とする2層配線TABテープ。
[1] A polyimide layer having a thickness of 30 to 45 μm, a first wiring layer formed on one side of the polyimide layer by patterning via an adhesive layer, and an adhesive on the other side of the polyimide layer A second wiring layer patterned and formed without a layer, a blind via provided through the polyimide layer, the adhesive layer and the second wiring layer, an inner surface of the blind via, and A copper plating layer formed on the surface of the second wiring layer to electrically connect the second wiring layer to the first wiring layer; and a ball pad layer formed on the surface of the copper plating layer. A two-layer wiring TAB tape, comprising: a solder ball formed as described above; and a photo solder resist layer formed in a region of the second wiring layer excluding the ball pad layer.

【0007】[2] 前記ポリイミド層が、前記一面に
半導体チップを搭載する領域を有するとともに、フォト
ソルダレジスト層及び接着剤層を介してステフナーを貼
付する領域を有する構成の前記[1]に記載の2層配線
TABテープ。
[2] The above-mentioned [1], wherein the polyimide layer has a region for mounting a semiconductor chip on the one surface and a region for attaching a stiffener via a photo solder resist layer and an adhesive layer. 2-layer wiring TAB tape.

【0008】[3] 厚さが30〜45μmのポリイミ
ド層の片面に第2の銅箔層を積層した接着剤レス片面銅
貼りCCL基材のポリイミド層側の表面に、接着剤層を
介して第1の銅箔層を貼付してキュアして複合基材を形
成し、前記複合基材の第2の銅箔層にエッチング加工を
施すとともに、前記ポリイミド層及び前記接着剤層に直
接レーザ(Laser)加工を施してブラインドビアを
形成し、デスミヤ処理後導電処理して前記ブラインドビ
アに銅めっき層を形成し、前記第1の銅箔層を所定のパ
ターンの第1の配線層に加工し、前記第2の銅箔層を所
定のパターンの第2の配線層に加工し、前記第1及び第
2の配線層を前記銅めっき層によって相互に電気的に接
続し、さらに、前記銅めっき層及び前記第2の配線層の
表面にボール・パッド層を形成し、前記第2の配線層の
前記ボール・ パッド層を除く領域にフォトソルダレジス
ト層を形成し、前記ボール・パッド層にはんだボールを
配設してなることを特徴とする2層配線TABテープの
製造方法。
[3] An adhesive-less single-sided copper-clad CCL substrate in which a second copper foil layer is laminated on one side of a polyimide layer having a thickness of 30 to 45 μm, a polyimide layer side surface of the CCL substrate is interposed therebetween. The first copper foil layer is attached and cured to form a composite base material, and the second copper foil layer of the composite base material is subjected to an etching process, and the polyimide layer and the adhesive layer are directly subjected to laser ( (Laser) processing to form a blind via, a desmearing treatment and a conductive treatment to form a copper plating layer on the blind via, and process the first copper foil layer into a first wiring layer having a predetermined pattern. Processing the second copper foil layer into a second wiring layer having a predetermined pattern, electrically connecting the first and second wiring layers to each other by the copper plating layer, Ball and the surface of the second wiring layer. Forming a layer, forming a photo solder resist layer in a region of the second wiring layer excluding the ball / pad layer, and disposing a solder ball on the ball / pad layer. A method for manufacturing a wiring TAB tape.

【0009】本発明は、上記の構成としたので、ポリイ
ミド層に熱による歪みが発生せず、従って、テープに蛇
行が生ずることがなく、また、配線パターンにズレが生
じない。また、BGA・CSP等の配線の設計における
自由度が高く、さらに、フォトソルダレジストからなる
ボール・パッド層がキャスティングに形成されたポリイ
ミド層と直接接触しないので、剥離を回避することがで
きる。
According to the present invention, since the above-described structure is employed, no distortion occurs due to heat in the polyimide layer, so that the tape does not meander, and the wiring pattern does not shift. Further, the degree of freedom in designing wiring such as BGA / CSP is high, and furthermore, since the ball pad layer made of a photo solder resist does not directly contact the polyimide layer formed on the casting, peeling can be avoided.

【0010】[0010]

【発明の実施の形態】以下、本発明の実施の形態を図面
を参照しつつ具体的に説明する。
Embodiments of the present invention will be specifically described below with reference to the drawings.

【0011】図1は、本発明の2層配線TABテープを
使用した半導体装置を示す。図1(イ)及び(ロ)に示
すように、この半導体装置は、厚さが30〜45μmの
ポリイミド層1と、ポリイミド層1の一面に接着剤層4
を介してパターン化して形成した第1の配線層8と、ポ
リイミド層1の他面に接着剤層を介さないでパターン化
して形成した第2の配線層9と、ポリイミド層1、接着
剤層4及び第2の配線層9を貫通して設けたブラインド
ビア6と、ブラインドビア6の内面及び第2の配線層9
の表面に形成した銅めっき層7と、銅めっき層7の表面
に形成したボール・パッド層10に配設したはんだボー
ル26と、ボール・パッド層26を除く第2の配線層1
0上に形成されたフォトソルダレジスト10を備え、か
つ第1及び第2の配線層8,9を銅めっき層7によって
相互に電気的に接続している。
FIG. 1 shows a semiconductor device using a two-layer wiring TAB tape of the present invention. As shown in FIGS. 1A and 1B, this semiconductor device has a polyimide layer 1 having a thickness of 30 to 45 μm, and an adhesive layer 4 on one surface of the polyimide layer 1.
A first wiring layer 8 formed by patterning through the polyimide layer 1, a second wiring layer 9 formed by patterning the other surface of the polyimide layer 1 without using the adhesive layer, the polyimide layer 1, the adhesive layer 4 and the second wiring layer 9, the blind via 6 provided through the second wiring layer 9, and the inner surface of the blind via 6 and the second wiring layer 9.
, A solder ball 26 disposed on a ball pad layer 10 formed on the surface of the copper plating layer 7, and a second wiring layer 1 excluding the ball pad layer 26.
The first and second wiring layers 8 and 9 are electrically connected to each other by a copper plating layer 7.

【0012】ここで、ポリイミド層1の厚さは、30〜
45μmであることが必要である。30μm未満である
と機械的強度が不十分となり、45μmを超えると、キ
ャスティング時の熱による歪みが発生して形状性が低下
する。また、第1の銅箔層5の厚さは、5〜35μmが
好ましい。この範囲を外れると、電解銅箔では製造でき
ないことがある。また、ブラインドビア6の径は、30
〜80μmが好ましい。80μmを超えると、リード配
線ピッチが80μm未満のファインピツチの配線の引き
回しが困難となることがあり、30μm未満であると、
レーザの穴明けが不安定となり、またデスミヤ処理が不
確実となることがある。また、第2の銅箔層2の厚さ
は、5〜35μmが好ましい。この範囲を外れると、電
解銅箔では製造できないことがある。さらに、接着剤層
4の厚さは、5〜15μmが好ましい。5μm未満であ
ると、機械的強度が不十分となり、15μmを超えると
フレキシビリティが不十分となる。
Here, the thickness of the polyimide layer 1 is 30 to
It needs to be 45 μm. If it is less than 30 μm, the mechanical strength becomes insufficient, and if it exceeds 45 μm, distortion due to heat at the time of casting occurs, and the shape is reduced. Further, the thickness of the first copper foil layer 5 is preferably from 5 to 35 μm. Outside of this range, it may not be possible to produce with an electrolytic copper foil. The diameter of the blind via 6 is 30
~ 80 µm is preferred. If it exceeds 80 μm, it may be difficult to route fine pitch wiring with a lead wiring pitch of less than 80 μm, and if it is less than 30 μm,
Laser drilling may be unstable and desmear processing may be uncertain. Further, the thickness of the second copper foil layer 2 is preferably from 5 to 35 μm. Outside of this range, it may not be possible to produce with an electrolytic copper foil. Further, the thickness of the adhesive layer 4 is preferably 5 to 15 μm. If it is less than 5 μm, the mechanical strength becomes insufficient, and if it exceeds 15 μm, the flexibility becomes insufficient.

【0013】本発明の2層配線TABテープの好適な例
として、ポリイミド層1が、一面に、半導体チップ20
を搭載する領域を有するものを挙げることができる。
As a preferred example of the two-layer wiring TAB tape of the present invention, the polyimide layer 1 has a semiconductor chip 20
Can be used.

【0014】また、好適な例として、ポリイミド層1
が、一面に、フォトソルダレジスト10及び接着剤層2
5を介してステフナー24を貼付する領域を有するもの
を挙げることができる。
As a preferred example, a polyimide layer 1
However, on one side, the photo solder resist 10 and the adhesive layer 2
One having a region to which the stiffener 24 is attached via the step 5 can be used.

【0015】さらに好適な例として、第1及び第2の配
線層8,9が、それぞれの表面に、ニッケル層、金層、
スズ層、又は、はんだめっき層をさらに備えてなるもの
を挙げることができる。
As a further preferred example, the first and second wiring layers 8 and 9 have a nickel layer, a gold layer,
Examples further include a tin layer or a solder plating layer.

【0016】図2(イ)〜(ハ)に示すように、本発明
の2層配線TABテープは、厚さが30〜45μmのポ
リイミド層1の片面に第2の銅箔層2を積層した接着剤
レス片面銅貼りCCL基材3のポリイミド層1側の表面
に、接着剤層4を介して第1の銅箔層5を貼付してキュ
アして複合基材を形成し、複合基材の第2の銅箔層2に
フォトプロセスとエッチング加工を施すとともに、ポリ
イミド層1及び接着剤層4に直接レーザ(Laser)
加工を施してブラインドビア6を形成し、デスミヤ処理
後導電処理してブラインドビア6に銅めっき層7を形成
し、第1の銅箔層5を所定のパターンの第1の配線層8
に加工し、第2の銅箔層2を所定のパターンの第2の配
線層9に加工し、第1及び第2の配線層8,9を銅めっ
き層7によって相互に電気的に接続し、さらに、銅めっ
き層7及び第2の配線層8,9の表面にボール・パッド
層10を形成し、ボール・パッド層10にはんだボール
26を配設し、第2の配線層9のボール・ パッド層10
のない領域にフォトソルダレジスト10を形成すること
により製造することができる。
As shown in FIGS. 2A to 2C, in the two-layer wiring TAB tape of the present invention, a second copper foil layer 2 is laminated on one side of a polyimide layer 1 having a thickness of 30 to 45 μm. The first copper foil layer 5 is adhered to the surface of the adhesive-less single-sided copper-clad CCL substrate 3 on the polyimide layer 1 side via the adhesive layer 4 and cured to form a composite substrate. The second copper foil layer 2 is subjected to a photo process and an etching process, and a laser (Laser) is directly applied to the polyimide layer 1 and the adhesive layer 4.
Processing is performed to form a blind via 6, a desmear treatment is performed, and then a conductive treatment is performed to form a copper plating layer 7 on the blind via 6, and the first copper foil layer 5 is formed into a first wiring layer 8 having a predetermined pattern.
The second copper foil layer 2 is processed into a second wiring layer 9 having a predetermined pattern, and the first and second wiring layers 8 and 9 are electrically connected to each other by a copper plating layer 7. Further, the ball pad layer 10 is formed on the surfaces of the copper plating layer 7 and the second wiring layers 8 and 9, and the solder balls 26 are provided on the ball pad layer 10, and the balls of the second wiring layer 9 are formed.・ Pad layer 10
It can be manufactured by forming the photo-solder resist 10 in a region where there is not.

【0017】また、本発明の2層配線TABテープの製
造方法の好適な例として、第1及び第2の配線層8,9
のそれぞれの表面に、ニッケル層、金層、スズ層、又
は、はんだめっき層をさらに形成する方法を挙げること
ができる。
As a preferred example of the method for manufacturing a two-layer wiring TAB tape of the present invention, first and second wiring layers 8 and 9 are used.
And a method of further forming a nickel layer, a gold layer, a tin layer, or a solder plating layer on each of the surfaces.

【0018】以下、実施例によって本発明をさらに具体
的に説明する。 (実施例1)図2(イ)に示すように、厚さが40μm
のポリイミド層1の片面に、厚さが18μmの第2の銅
箔層2を積層した、幅が70mmの接着剤レス片面銅貼
りCCL(Copper C1ad Laminat
e)基材3のポリイミド層側の表面に、ポリイミド系接
着剤を塗布して厚さが12μmの接着剤層4を形成し、
この表面上に厚さが18μmの第1の銅箔層5を貼付
し、キュアして複合基材を形成した。
Hereinafter, the present invention will be described more specifically with reference to examples. (Example 1) As shown in FIG.
Adhesive-less single-sided copper-clad CCL (Copper C1ad Laminat) having a width of 70 mm in which a second copper foil layer 2 having a thickness of 18 μm is laminated on one side of a polyimide layer 1
e) A polyimide adhesive is applied to the surface of the substrate 3 on the polyimide layer side to form an adhesive layer 4 having a thickness of 12 μm,
A first copper foil layer 5 having a thickness of 18 μm was stuck on the surface and cured to form a composite substrate.

【0019】次に、図2(ロ)に示すように、得られた
複合基材の第2の銅箔層2にフォトプロセスとエッチン
グ加工を施した後に、ポリイミド層1及び接着剤層4に
レーザ加工により直接60μm径のブラインドビア(B
lind Via)6を64個形成した後、過マンガン
酸カリでデスミヤ処理をし、その後にカーボン導通化処
理した。
Next, as shown in FIG. 2B, the second copper foil layer 2 of the obtained composite base material is subjected to a photo process and an etching process. Blind via with a diameter of 60 μm directly by laser processing (B
After forming 64 (Via vial), desmear treatment was performed with potassium permanganate, and then carbon conduction treatment was performed.

【0020】次に、図2(ハ)に示すように、厚さ10
μmの銅めっき層7を形成した。
Next, as shown in FIG.
A μm copper plating layer 7 was formed.

【0021】次に、図1(イ)及び(ロ)に示すよう
に、第2の銅箔層2をフォトプロセスとエッチングで、
所定のパターンの第2の配線層9に加工するとともに、
第1の銅箔層5をフォトプロセスとエッチングで所定の
パターンの第1の配線層8に加工した。
Next, as shown in FIGS. 1A and 1B, the second copper foil layer 2 is subjected to a photo process and an etching process.
While processing into the second wiring layer 9 of a predetermined pattern,
The first copper foil layer 5 was processed into a first wiring layer 8 having a predetermined pattern by a photo process and etching.

【0022】次に、第2の配線層9にボール・パツド層
10を形成し、第2の配線層9及び第1の配線層8にN
i,Auめっき層(図示せず)を形成し、2層配線のT
ABテープを製造した。
Next, a ball pad layer 10 is formed on the second wiring layer 9, and N is added to the second wiring layer 9 and the first wiring layer 8.
i, Au plating layer (not shown) is formed, and T
AB tape was produced.

【0023】次に、LSIチップ20をポリイミドテー
プ1にダイアタッチ剤21で貼付し、シングルポイント
ボンダでボンディングワイヤー27をボンディング後、
ポッテング封止樹脂23で封止した。ステフナー24を
ステフナー貼り付け接着剤25で貼付し、パッケージと
した。
Next, the LSI chip 20 is adhered to the polyimide tape 1 with the die attach agent 21, and the bonding wire 27 is bonded with a single point bonder.
It was sealed with a potting sealing resin 23. The stiffener 24 was stuck with a stiffener sticking adhesive 25 to form a package.

【0024】次に、はんだボール26を搭載後、FR4
基板(図示せず)に実装して信頼性を測定した。その結
果、温度サイクル試験(−55℃(30分保持)⇔12
5℃(30分保持)の1000サイクルと高温バイアス
試験(85℃x85%RH、印荷電圧7V)を1000
時間でも不具合がなく良好な結果を得た。
Next, after the solder balls 26 are mounted, FR4
It was mounted on a substrate (not shown) and its reliability was measured. As a result, the temperature cycle test (−55 ° C. (hold for 30 minutes) ⇔12
1000 cycles of 5 ° C (holding for 30 minutes) and high temperature bias test (85 ° C x 85% RH, imprint voltage 7V)
Even in time, there was no problem and good results were obtained.

【0025】(実施例2)実施例1において、50μm
径のブラインドビア(Blind Via)を形成した
こと以外は実施例と同様にした。その結果、前記温度サ
イクル試験と前記高温バイアス試験を1000時間でも
不具合がなく良好な結果を得た。
(Embodiment 2) In the embodiment 1, 50 μm
The procedure was the same as in the example except that a blind via having a diameter was formed. As a result, good results were obtained in the temperature cycle test and the high temperature bias test without any trouble even after 1000 hours.

【0026】なお、本発明の2層配線TABテープは、
アウターホール無しでデバイスホール無しのFlip
Chip接合の2層配線TABテープの構造にも適用可
能である。
It should be noted that the two-layer wiring TAB tape of the present invention
Flip without outer hole and no device hole
The present invention is also applicable to the structure of a chip bonding two-layer wiring TAB tape.

【0027】また、本発明の2層配線TABテープは,
微細配線リードピッチが80μm以下の前記Wire
BondingタイプのCSP及びTape BGA
(Ball Gride Array)等にも適用可能
である。
Also, the two-layer wiring TAB tape of the present invention is
The wire having a fine wiring lead pitch of 80 μm or less.
Bonding type CSP and Tape BGA
(Ball Grid Array) and the like.

【0028】[0028]

【発明の効果】以上説明した通り、本発明によって、熱
による歪みの発生が少なく、形状性に優れ、BGA・C
SP等の配線の設計における自由度が高く、かつフォト
ソルダレジストとの密着性、特にステフナー貼り付け側
の密着性が良好で信頼性の高い2層配線TABテープ、
及び高生産性かつ低コストの2層配線TABテープの製
造方法を提供することができる。
As described above, according to the present invention, the generation of distortion due to heat is small, the shape is excellent, and BGA / C
A highly reliable two-layer wiring TAB tape that has a high degree of freedom in the design of wiring such as SP and has good adhesion to the photo solder resist, particularly good adhesion on the side where the stiffener is attached;
Further, it is possible to provide a method of manufacturing a two-layer wiring TAB tape with high productivity and low cost.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の2層配線TABテープの1 実施例を、
BGAに適用した場合を模式的に示す断面図(イ)及び
その一部拡大図(ロ)である。
FIG. 1 shows an embodiment of a two-layer wiring TAB tape of the present invention.
FIG. 3A is a cross-sectional view schematically showing a case where the present invention is applied to a BGA, and FIG.

【図2】本発明の2層配線TABテープの1 実施例にお
いて、片面CCLにブラインドビアを形成し、銅メッキ
を施こす工程[(イ)〜(ハ)]を模式的に示す断面図
である。
FIG. 2 is a cross-sectional view schematically showing steps ((a) to (c)) of forming a blind via on one side CCL and performing copper plating in one embodiment of the two-layer wiring TAB tape of the present invention. is there.

【図3】従来の導通化処理及び銅めっきを施した片面C
CLの製造工程[(イ)〜(ハ)]を模式的に示す断面
図である。
FIG. 3 shows one side C subjected to a conventional conduction treatment and copper plating.
It is sectional drawing which shows the manufacturing process [(a)-(c)] of CL typically.

【符号の説明】[Explanation of symbols]

1:ポリイミド層 2:第2の銅箔層 3:CCL基材 4:接着剤層 5:第1の銅箔層 6:ブラインドビア 7:銅めっき層 8:第1の配線層 9:第2の配線層 10:フォトソルダレジスト 20:LSIチップ 21:ダイアタッチ剤 22:アウターリード 23:ポッティング封止樹脂 24:ステフナー 25:ステフナー貼り付け接着剤 26:はんだボール 27:ボンディングワイヤー 1: polyimide layer 2: second copper foil layer 3: CCL substrate 4: adhesive layer 5: first copper foil layer 6: blind via 7: copper plating layer 8: first wiring layer 9: second Wiring layer 10: Photo solder resist 20: LSI chip 21: Die attach agent 22: Outer lead 23: Potting sealing resin 24: Stiffener 25: Stiffener bonding adhesive 26: Solder ball 27: Bonding wire

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/42 610 H05K 3/42 610A Fターム(参考) 5E317 AA07 AA25 BB03 BB12 CC31 CD01 CD11 CD21 CD27 CD32 GG03 GG17 GG20 5F044 MM04 MM11 MM48 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (Reference) H05K 3/42 610 H05K 3/42 610A F-term (Reference) 5E317 AA07 AA25 BB03 BB12 CC31 CD01 CD11 CD21 CD27 CD32 GG03 GG17 GG20 5F044 MM04 MM11 MM48

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 厚さが30〜45μmのポリイミド層
と、前記ポリイミド層の一面に接着剤層を介してパター
ン化して形成した第1の配線層と、前記ポリイミド層の
他面に接着剤層を介さないでパターン化して形成した第
2の配線層と、前記ポリイミド層、前記接着剤層及び前
記第2の配線層を貫通して設けたブラインドビアと、前
記ブラインドビアの内面及び前記第2の配線層の表面に
形成して前記第2の配線層を前記第1の配線層に電気的
に接続する銅めっき層と、前記銅めっき層の表面に形成
したボール・パッド層に配設したはんだボールと、前記
第2の配線層の前記ボール・ パッド層を除く領域に形成
したフォトソルダレジスト層を備えてなることを特徴と
する2層配線TABテープ。
1. A polyimide layer having a thickness of 30 to 45 μm, a first wiring layer formed by patterning one surface of the polyimide layer via an adhesive layer, and an adhesive layer on the other surface of the polyimide layer. A second wiring layer formed by patterning without passing through, a blind via provided through the polyimide layer, the adhesive layer, and the second wiring layer; an inner surface of the blind via; A copper plating layer formed on the surface of the wiring layer and electrically connecting the second wiring layer to the first wiring layer; and a ball pad layer formed on the surface of the copper plating layer. A two-layer wiring TAB tape, comprising: a solder ball; and a photo solder resist layer formed in a region of the second wiring layer excluding the ball pad layer.
【請求項2】 前記ポリイミド層が、前記一面に半導体
チップを搭載する領域を有するとともに、フォトソルダ
レジスト層及び接着剤層を介してステフナーを貼付する
領域を有する構成の請求項1に記載の2層配線TABテ
ープ。
2. The structure according to claim 1, wherein the polyimide layer has a region for mounting a semiconductor chip on the one surface and a region for attaching a stiffener via a photo solder resist layer and an adhesive layer. Layer wiring TAB tape.
【請求項3】 厚さが30〜45μmのポリイミド層の
片面に第2の銅箔層を積層した接着剤レス片面銅貼りC
CL基材のポリイミド層側の表面に、接着剤層を介して
第1の銅箔層を貼付してキュアして複合基材を形成し、
前記複合基材の第2の銅箔層にエッチング加工を施すと
ともに、前記ポリイミド層及び前記接着剤層に直接レー
ザ(Laser)加工を施してブラインドビアを形成
し、デスミヤ処理後導電処理して前記ブラインドビアに
銅めっき層を形成し、前記第1の銅箔層を所定のパター
ンの第1の配線層に加工し、前記第2の銅箔層を所定の
パターンの第2の配線層に加工し、前記第1及び第2の
配線層を前記銅めっき層によって相互に電気的に接続
し、さらに、前記銅めっき層及び前記第2の配線層の表
面にボール・パッド層を形成し、前記第2の配線層の前
記ボール・ パッド層を除く領域にフォトソルダレジスト
層を形成し、前記ボール・パッド層にはんだボールを配
設してなることを特徴とする2層配線TABテープの製
造方法。
3. An adhesive-less single-sided copper paste C in which a second copper foil layer is laminated on one side of a polyimide layer having a thickness of 30 to 45 μm.
On the surface of the CL substrate on the polyimide layer side, a first copper foil layer is attached via an adhesive layer and cured to form a composite substrate,
The second copper foil layer of the composite base material is subjected to an etching process, and the polyimide layer and the adhesive layer are directly subjected to a laser (Laser) process to form a blind via. Forming a copper plating layer on a blind via, processing the first copper foil layer into a first wiring layer having a predetermined pattern, and processing the second copper foil layer into a second wiring layer having a predetermined pattern; And electrically connecting the first and second wiring layers to each other by the copper plating layer, further forming a ball pad layer on the surfaces of the copper plating layer and the second wiring layer, A method of manufacturing a two-layer wiring TAB tape, comprising: forming a photo solder resist layer in a region of the second wiring layer other than the ball / pad layer; and arranging solder balls on the ball / pad layer. .
JP22687499A 1999-08-10 1999-08-10 Double layer wiring tab tape and manufacturing method thereof Pending JP2001053194A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22687499A JP2001053194A (en) 1999-08-10 1999-08-10 Double layer wiring tab tape and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22687499A JP2001053194A (en) 1999-08-10 1999-08-10 Double layer wiring tab tape and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JP2001053194A true JP2001053194A (en) 2001-02-23

Family

ID=16851938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22687499A Pending JP2001053194A (en) 1999-08-10 1999-08-10 Double layer wiring tab tape and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2001053194A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005340596A (en) * 2004-05-28 2005-12-08 Toppan Printing Co Ltd Compound stiffener and substrate for semiconductor device as well as semiconductor device equipped therewith
JP2007242790A (en) * 2006-03-07 2007-09-20 Hitachi Cable Ltd Double-sided wiring tape carrier for semiconductor device, and its manufacturing method
KR100835720B1 (en) 2006-12-04 2008-06-05 삼성전기주식회사 Image sensor module and camera module using it
JP2011171404A (en) * 2010-02-17 2011-09-01 Hitachi Cable Ltd Tab tape for semiconductor device, and method of manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005340596A (en) * 2004-05-28 2005-12-08 Toppan Printing Co Ltd Compound stiffener and substrate for semiconductor device as well as semiconductor device equipped therewith
JP4599891B2 (en) * 2004-05-28 2010-12-15 凸版印刷株式会社 Semiconductor device substrate and semiconductor device
JP2007242790A (en) * 2006-03-07 2007-09-20 Hitachi Cable Ltd Double-sided wiring tape carrier for semiconductor device, and its manufacturing method
KR100835720B1 (en) 2006-12-04 2008-06-05 삼성전기주식회사 Image sensor module and camera module using it
JP2011171404A (en) * 2010-02-17 2011-09-01 Hitachi Cable Ltd Tab tape for semiconductor device, and method of manufacturing the same

Similar Documents

Publication Publication Date Title
JP2748768B2 (en) Thin film multilayer wiring board and method of manufacturing the same
JPH09199635A (en) Multilayer film for forming circuit substrate, multilayer circuit substrate using it, and package for semiconductor device
KR100339252B1 (en) Semiconductor device with solder bumps and manufacturing method thereof
JP2833642B2 (en) Multilayer wiring board and method of manufacturing the same
JP2001053194A (en) Double layer wiring tab tape and manufacturing method thereof
JP2002151853A (en) Multilayer printed wiring board and manufacturing method thereof
JP3926064B2 (en) Printed wiring board and method for manufacturing printed wiring board
JPH0982751A (en) Mounting structure for device
JP4779619B2 (en) Support plate, multilayer circuit wiring board, and semiconductor package using the same
JP2002076166A (en) Resin sealing type semiconductor device and its manufacturing method
JP2006310543A (en) Wiring board and its production process, wiring board with semiconductor circuit element
JP4711757B2 (en) Wiring board
JP2001053116A (en) Two-layer tab tape and manufacture thereof
JP2008098202A (en) Multilayer wiring circuit board, multilayer wiring circuit board structure
JP3541741B2 (en) Method of manufacturing multilayer TAB tape
JP2000031319A (en) Substrate carrier for mounting semiconductor element and semiconductor device using the same
JP3351312B2 (en) Method of manufacturing TAB tape for T-BGA
JP3324472B2 (en) Method for manufacturing TAB tape for BGA
JP3362636B2 (en) Method for manufacturing TAB tape carrier
JP3196758B2 (en) Lead frame, method of manufacturing lead frame, semiconductor device, and method of manufacturing semiconductor device
JP2002043745A (en) Wiring board and semiconductor device using it
JP3893088B2 (en) Manufacturing method of substrate for semiconductor package
JP2666569B2 (en) Manufacturing method of substrate with lead for semiconductor mounting
JP4655917B2 (en) Multilayer substrate for semiconductor package and manufacturing method thereof
JP4591098B2 (en) Manufacturing method of semiconductor device mounting substrate

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040427

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040907

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041105

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050419

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20050816