JP2007242790A - Double-sided wiring tape carrier for semiconductor device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of communication between conductor foils covering both surfaces of an insulating tape, to make fine pitches of a wiring pattern, and to improve a yield in forming the wiring pattern. <P>SOLUTION: A double-sided wiring tape carrier includes a three-layered tape base having a first conductor foil and a second conductor foil stuck respectively to both surfaces of the insulating tape, a blind via hole provided through the first conductor foil and the insulating tape in the thickness direction of the tape base having a bottom closed with the second conductor foil, and a metal plated layer formed entirely on the surface of the first conductor foil to entirely bury the inside of the blind via hole for making the first and second conductor foils conductive. A total thickness from a rear face of the first conductor foil as a reference plane to the surface of a conductor layer consisting of the first conductor foil and the metal plated layer is specified to be 15 μm or less. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a tape carrier used for a semiconductor device and a manufacturing method thereof, and more particularly to a double-sided wiring tape carrier for a semiconductor device suitable for fine pitch and a manufacturing method thereof.

  In recent years, information-related devices such as mobile phones and IC cards have been required to have low noise and high wiring density in the high frequency region in addition to downsizing and thinning. In response to this, tape carriers for semiconductor devices have been put into practical use.

  As a material for a double-sided wiring tape carrier for semiconductor devices, generally, a three-layer tape base material having an organic insulating tape such as polyimide and a copper foil covering both surfaces of the insulating tape is used.

  In order to electrically connect the copper foils on both sides, the tape base material is provided with a blind via hole that penetrates one copper foil and the insulating tape in the thickness direction and whose bottom surface is closed by the other copper foil. By covering the inner surface of the blind via hole with a copper plating layer, the copper foils on both sides are made conductive.

  After conducting the copper foils on both sides, a wiring pattern is formed on the copper foils on both sides using a photoetching method. In this case, a dry film resist may be used because it is possible to simultaneously form wiring patterns on both sides in addition to a liquid resist and to sufficiently protect the surface irregularities. (For example, see Patent Document 1)

  After the wiring pattern is formed, a protective insulating layer or the like is formed on the surface of the wiring pattern, and the manufacture of the double-sided wiring tape carrier for a semiconductor device is completed.

  Here, it is desirable that the inside of the blind via hole is completely filled with copper plating in order to improve the conduction reliability between the copper foils. On the other hand, it is desirable that the thickness of the copper plating layer deposited on the surface of the copper foil is thin in order to request a fine pitch wiring pattern formed on the copper foil.

As a method for covering the inner surface of the blind via hole with a copper plating layer, a conformal plating method and a via filling plating method are known.
The conformal plating method is an electroplating method in which copper plating is deposited at a uniform rate according to the shape of the base. According to this method, a copper plating layer having a uniform thickness is formed on the copper foil surface and the inner surface of the blind via hole.
On the other hand, the via filling plating method is an electroplating method that promotes the deposition of copper plating on the inner surface of the blind via hole while suppressing the deposition of copper plating on the surface of the copper foil using an additive. According to this method, the entire interior of the blind via hole can be filled with copper plating while the copper plating layer deposited on the copper foil surface is kept thin. (For example, see Patent Documents 2 and 3)

JP-A-11-251374 JP 2005-19577 A JP 2005-217216 A

  However, the above-described conformal plating method and via filling plating method have the following problems.

(1) Problems of conformal plating method In the conformal plating method, when the copper plating layer deposited on the copper foil surface is thinned, the copper plating layer deposited on the inner surface of the blind via hole is also thinned. In such a case, the fine pitch of the wiring pattern is possible because the copper plating layer deposited on the surface of the copper foil is thin, but the copper plating layer on the inner surface of the blind via hole tends to break due to temperature changes, and the conduction reliability between the copper foils It becomes low.

  In the conformal plating method, when the copper plating layer deposited on the inner surface of the blind via hole is thickened, the copper plating layer deposited on the copper foil surface is also thickened. In this case, although conduction reliability between the copper foils is high, it is difficult to make a fine pitch of the wiring pattern formed on the copper foil.

  Here, after the copper plating layer is deposited thickly on the inner surface of the blind via hole using the conformal plating method, only the copper plating layer excessively deposited on the copper foil surface can be polished and thinned afterwards. . However, in the conformal plating method, the entire interior of the blind via hole is not filled with the copper plating layer, and the abrasive enters the inside of the blind via hole during the above polishing, so only the copper foil surface is selectively used. Polishing is difficult.

  In the conformal plating method, as described above, the entire interior of the blind via hole is not filled with the copper plating layer. Therefore, when the dry film resist covers the opening of the blind via hole, a cavity is formed on the back side of the dry film resist (that is, the tent property is poor), and the dry film resist is easily broken. For this reason, the thin dry film resist suitable for fine pitch cannot be used, and it becomes difficult to make fine pitch of the wiring pattern formed on the copper foil.

(2) Problems of Via Filling Plating Method In the via filling plating method, the additive in the plating solution is decomposed together with the plating electrolysis, and a part of the decomposition product accumulates in the plating solution.
The decomposition product adversely affects the promotion of copper plating deposition on the inner surface of the blind via hole. Therefore, if plating electrolysis is continued using the same plating solution without removing such decomposition products, the entire interior of the blind via hole cannot be gradually filled with copper plating, and the conduction reliability between the copper foils is impaired. End up.

  In order to avoid an adverse effect due to accumulation of decomposition products, it is effective to perform plating electrolysis while keeping the copper plating layer deposited on the surface of the copper foil thick. However, if the copper plating layer deposited on the surface of the copper foil is thick, it becomes difficult to make a fine pitch of the wiring pattern formed on the copper foil.

(3) Common problems The conformal plating method and via filling plating method are bright plating, and the surface of the copper foil after plating is very smooth and has a low coefficient of friction. Therefore, the adhesiveness between the copper foil surface after the plating treatment and the dry film resist is low, and the yield when forming a wiring pattern on the copper foil is deteriorated.

Therefore, in view of the above circumstances, the present invention
Double-sided wiring for semiconductor manufacturing equipment that improves conduction reliability between conductor foils covering both sides of insulating tape, realizes finer pitch of wiring patterns formed on conductor foils, and improves yield when forming wiring patterns An object of the present invention is to provide a tape carrier and a manufacturing method thereof.

  In order to solve the above problems, the present invention has the following configuration.

  A double-sided wiring tape carrier for a semiconductor device according to the invention of claim 1 includes a three-layer tape base material in which a first conductor foil and a second conductor foil are respectively attached to both surfaces of an insulating tape, and the first tape A blind via hole provided so as to penetrate through the conductor foil and the insulating tape in the thickness direction of the tape base material, and a bottom surface thereof being blocked by the second conductive foil, and the entire interior of the blind via hole is filled A metal plating layer that is formed on the entire surface of the first conductor foil and conducts the first conductor foil and the second conductor foil, with the back surface of the first conductor foil as a reference plane, The total thickness from the reference plane to the surface of the conductor layer composed of the first conductor foil and the metal plating layer is 15 μm or less.

  According to a second aspect of the present invention, in the double-sided wiring tape carrier for a semiconductor device according to the first aspect, the surface of the conductive layer is a rough surface.

  According to a third aspect of the present invention, in the double-sided wiring tape carrier for a semiconductor device according to the first or second aspect, the thickness of the second conductive foil is 15 μm or less.

  According to a fourth aspect of the present invention, in the double-sided wiring tape carrier for a semiconductor device according to any one of the first to third aspects, the center line surface roughness of the surface of the conductor layer and the surface of the second conductive foil is It is 0.2 μm or more.

  According to a fifth aspect of the present invention, in the double-sided wiring tape carrier for a semiconductor device according to any one of the first to fourth aspects, a wiring pattern is formed on the first conductive foil and the second conductive foil. The wiring pitch of the wiring pattern is 60 μm or less.

  The method for manufacturing a double-sided wiring tape carrier for a semiconductor device according to the invention of claim 6 forms a three-layer tape base by affixing a first conductive foil and a second conductive foil on both sides of the insulating tape, respectively. Forming a blind via hole whose bottom surface is covered with the second conductive foil by punching the first conductive foil and the insulating tape in the thickness direction of the tape base, and By forming a metal plating layer having a predetermined thickness on the entire surface of the first conductor foil, the entire interior of the blind via hole is filled with metal plating, and the first conductor foil and the second conductor foil are The total thickness from the reference surface to the surface of the conductor layer composed of the first conductor foil and the metal plating layer is less than the reference thickness with the conducting step and the back surface of the first conductor foil as the reference surface So that Characterized in that it comprises a step of scraping the surface of the conductor layer.

  A seventh aspect of the present invention is the method of manufacturing a double-sided wiring tape carrier for a semiconductor device according to the sixth aspect, wherein the predetermined thickness of the metal plating layer is 5 μm or more.

  The invention according to claim 8 is the method for manufacturing a double-sided wiring tape carrier for a semiconductor device according to claim 6 or 7, wherein the reference thickness is 15 μm or less.

  The invention according to claim 9 is the method of manufacturing a double-sided wiring tape carrier for a semiconductor device according to any one of claims 6 to 8, wherein the step of cutting the surface side of the conductor layer includes the surface of the conductor layer and A step of polishing the surface of the second conductive foil so that the center line surface roughness is 0.2 μm or more is included.

  A tenth aspect of the present invention is the method for manufacturing a double-sided wiring tape carrier for a semiconductor device according to any one of the sixth to ninth aspects, wherein the step of forming the metal plating layer after the step of forming the blind via hole. Before, forming a conductive thin film made of any one of tin-palladium or a compound thereof, nickel or a compound thereof, graphite, conductive carbon, or a conductive polymer on the inner surface of the blind via hole. And

  Invention of Claim 11 is the manufacturing method of the double-sided wiring tape carrier for semiconductor devices in any one of Claim 6 to 10, After the process of shaving the surface side of the said conductor layer, the surface of the said conductor layer, The method includes a step of laminating a surface of the second conductive foil with a dry film resist, and a step of etching the conductive layer and the second conductive foil to form a wiring pattern.

  According to a twelfth aspect of the present invention, in the method for manufacturing a double-sided wiring tape carrier for a semiconductor device according to the eleventh aspect, the dry film resist has a thickness of 20 μm or less.

  According to a thirteenth aspect of the present invention, in the method for manufacturing a double-sided wiring tape carrier for a semiconductor device according to the eleventh or twelfth aspect, after the step of forming the wiring pattern, the surface of the wiring pattern is thermosetting or photosensitive. A step of forming an insulating layer such as a conductive solder resist or a coverlay.

  According to the double-sided wiring tape carrier for a semiconductor manufacturing apparatus and the method for manufacturing the same according to the present invention, the conduction reliability between the conductive foils covering both surfaces of the insulating tape can be improved, and the fine pitch of the wiring pattern formed on the conductive foil can be achieved. This can be realized, and the yield when forming the wiring pattern can be improved.

  Next, an embodiment according to the present invention will be described with reference to the drawings. FIG. 1 is an explanatory view of a method for manufacturing a double-sided wiring tape carrier for a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a double-sided wiring tape carrier for a semiconductor device according to an embodiment of the present invention. FIG. 3 is an explanatory diagram of a via filling plating method. FIG. 4 is an explanatory diagram showing the filling rate of the copper plating layer in the blind via hole. FIG. 5 is an explanatory diagram showing how the filling rate deteriorates due to accumulation of decomposition products.

  As shown in FIG. 2, a copper foil 2 a as a first conductor foil is attached to the surface of the polyimide tape 2 as an insulating tape, and a copper foil 2 b as a second conductor foil is attached to the back surface of the polyimide tape 2. Is attached to form a three-layer tape substrate 1.

  The tape substrate 1 is provided with a plurality of blind via holes 3 penetrating the copper foil 2a and the polyimide tape 2 in the thickness direction. The bottom surface of each blind via hole 3 is closed with a copper foil 2 b on the back side of the polyimide tape 2. The diameter of the blind via hole 3 is, for example, 40 μm to 100 μm.

  On the inner surface of the blind via hole 3 and the surface of the copper foil 2a, there is a conductive thin film 4 made of a conductive polymer such as tin-palladium or a compound thereof, nickel or a compound thereof, graphite, conductive carbon, or polypyrrole. Is formed.

  Further, a copper plating layer 5 as a metal plating layer is formed on the inner surface of the blind via hole 3 and the surface of the copper foil 2a with the conductive thin film 4 as a base, and the copper foil 2a and the copper foil 2b are electrically connected. Is conducted. In addition, the laminated body which consists of the copper foil 2a, the electroconductive thin film 4, and the copper plating layer 5 is called the conductor layer 6. FIG. The conductor layer 6 covers the surface of the polyimide tape 2.

  The entire interior of the blind via hole 3 is filled with the copper plating layer 5. In FIG. 4, when A / B × 100% is defined as the filling rate, the filling rate in the present embodiment is 90% or more. Therefore, the upper surface of the blind via hole 3 has a substantially flat structure. Here, A is the height from the bottom surface of the blind via hole 3 to the surface of the conductor layer 6 in a region other than the blind via hole 3, and B is the bottom surface of the conductor layer 6 inside the blind via hole 3 from the bottom surface of the blind via hole 3. Up to.

  When the back surface of the copper foil 2a is taken as a reference surface, the total thickness d1 from the reference surface to the surface of the conductor layer 6 is set to 15 μm or less. Therefore, when the thickness of the copper foil 2 a is less than 15 μm, the uppermost surface of the conductor layer 6 becomes the copper plating layer 5 or the conductive thin film 4. On the other hand, when the thickness of the copper foil 2 a is 15 μm, the uppermost surface of the conductor layer 6 on the polyimide tape 2 becomes the copper foil 2 a or the conductive thin film 4.

  On the other hand, the thickness d2 of the copper foil 2b is also set to 15 μm or less.

  Moreover, the surface of the conductor layer 6 and the surface of the copper foil 2b are roughened, and the center line surface roughness of each surface is 0.2 μm or more.

  A wiring pattern 9 is formed on the conductor layer 6 and the copper foil 2b in a region other than the blind via hole 3. The wiring pitch 10 of the wiring pattern 9 is 60 μm or less.

  A part of the surface of the wiring pattern 9 is covered with a thermosetting or photosensitive solder resist as the insulating layer 7 or a coverlay. On the other hand, the surface of the wiring pattern 9 not covered with the insulating layer 7 is covered with a surface treatment layer 8 by nickel plating or gold plating.

  Then, the manufacturing method of the said double-sided wiring tape carrier for semiconductor devices is demonstrated using FIG.

  Prepare a polyimide tape 2 as an insulating tape, affix a copper foil 2a as a first conductor foil on the surface of the polyimide tape 2, and affix a copper foil 2b as a second conductor foil on the back surface of the polyimide tape 2 A three-layer tape substrate 1 is formed.

  Such attachment may or may not use an adhesive. As a method not using an adhesive, there are a casting method in which a varnish-like resin is applied to a copper foil, a laminating method in which the copper foil and a film are pressure-bonded by heat, and a plating method in which copper is deposited on the film. The order of attachment is not limited, and either the copper foil 2a or the copper foil 2b may be attached first, or the copper foil 2a and the copper foil 2b may be attached simultaneously. The copper foil 2b may be attached after perforating a copper foil 2a and a polyimide tape 2 described later.

  Thereafter, a perforation hole (not shown) for product conveyance is formed in the tape substrate 1 using a mold press.

  Thereafter, a part of the copper foil 2a is removed by a photoetching method to expose the surface of the polyimide tape 2 (FIG. 1B). The shape of the part to be removed is generally a circle having a diameter of about 40 to 100 μm.

Thereafter, the exposed surface of the polyimide tape 2 is irradiated with CO ₂ laser light to perforate the polyimide tape 2 in the thickness direction to form blind via holes 3 (FIG. 1C). The bottom surface of the blind via hole 3 is closed with a copper foil 2 b on the back surface side of the polyimide tape 2.

  When a burnt residue called smear remains on the inner surface of the blind via hole 3 during laser processing, it is necessary to remove smear called desmear treatment. Note that the polyimide tape 2 may be perforated using an etching means by wet processing.

  Then, using means such as electroless plating, the inner surface of the blind via hole 3 and the surface of the copper foil 2a are made of a conductive polymer such as tin-palladium or a compound thereof, nickel or a compound thereof, graphite, conductive carbon, or polypyrrole. A conductive thin film 4 made of any one of the materials is formed (FIG. 1D). The conductive thin film 4 serves as a base electrode for depositing a copper plating layer 5 described later.

  Thereafter, a copper plating layer 5 as a metal plating layer is formed on the inner surface of the blind via hole 3 and the surface of the copper foil 2a using the conductive thin film 4 as a base (FIG. 1 (e)). At this time, by using a via filling plating method to be described later, the entire interior of the blind via hole 3 is filled with the copper plating layer 5 and the copper foil 2a and the copper foil 2b are electrically connected.

  In carrying out via filling plating, a copper plating layer 5 having a predetermined thickness is deposited on the surface of the copper foil 2a so that a filling rate of 90% or more can be stably obtained. The predetermined thickness varies depending on the diameter and depth of the blind via hole 3, but is generally preferably 5 μm or more. Thereby, the upper surface of the blind via hole 3 has a substantially flat structure.

  Thereafter, the copper plating layer 5 excessively deposited on the surface of the conductor layer 6 so that the total thickness d1 from the reference surface to the surface of the conductor layer 6 is equal to or less than the reference thickness using the back surface of the copper foil 2a as a reference surface. Is removed by polishing (FIG. 1 (f)). In order to realize a fine pitch of the wiring pattern, it is desirable that the reference thickness is 15 μm or less. Therefore, when the thickness of the copper foil 2 a is less than 15 μm, the uppermost surface of the conductor layer 6 becomes the copper plating layer 5 or the conductive thin film 4. On the other hand, when the thickness of the copper foil 2 a exceeds 15 μm, the uppermost surface of the conductor layer 6 on the polyimide tape 2 becomes the copper foil 2 a or the conductive thin film 4.

  The above polishing may be chemical polishing using a hydrosulfuric acid based soft etching solution or mechanical polishing.

  On the other hand, even when the thickness d2 of the copper foil 2b exceeds 15 μm, the same polishing means is used to adjust the thickness to 15 μm or less in order to realize a fine pitch of the wiring pattern.

  In the above polishing, polishing is performed so that the center line surface roughness of the surface of the conductor layer 6 and the surface of the copper foil 2b is 0.2 μm or more. Such roughening increases the coefficient of friction of the surface.

  After the polishing is completed, a dry film resist (not shown) is laminated on the surfaces of the conductor layer 6 and the copper foil 2b in order to form a wiring pattern described later. In order to efficiently form a wiring pattern on both sides, it is desirable to laminate a dry film resist on both sides simultaneously. Further, in order to realize a fine pitch of the wiring pattern, the thickness of the dry film resist is preferably 20 μm or less.

  Next, the dry film resist is photocured by irradiating the surface of the dry film resist with ultraviolet rays through a photomask. Thereafter, using a developing solution such as an organic solvent or an alkaline aqueous solution, the dry film resist in the uncured portion is removed to form a resist pattern (not shown).

  The conductor layer 6 and the copper foil 2b not covered with the resist pattern are removed by etching to form a wiring pattern 9 (FIG. 1 (g)). The wiring pitch 10 of the wiring pattern 9 is 60 μm or less on both sides. After the wiring pattern 9 is formed, the resist pattern is removed.

  Thereafter, a thermosetting or photosensitive solder resist is applied onto a part of the surface of the wiring pattern 9 by using a screen printing method, thereby forming the insulating layer 7 (FIG. 1 (h)). As the insulating layer 7, a coverlay may be attached using an adhesive.

Finally, the surface treatment layer 8 is applied to the surface of the wiring pattern 9 not covered with the insulating layer 7 in the order of electro nickel plating and electro gold plating (FIG. 1 (i)).
Thus, the manufacture of the double-sided wiring tape carrier for a semiconductor device shown in FIG. 2 is completed.

  According to the present embodiment, by depositing a copper plating layer 5 having a predetermined thickness or more on the surface of the copper foil 2a at the time of via filling plating, the filling rate of the copper plating layer 5 in the blind via hole 3 is always set. It can be 90% or more. Therefore, the conduction reliability between the copper foil 2a and the copper foil 2b is high.

  Further, the thickness d1 of the conductor layer 6 and the thickness d2 of the copper foil 2b are polished so as to be 15 μm or less. Therefore, the fine pitch of the wiring pattern 9 can be realized.

  Furthermore, since the tent property of the blind via hole 3 is good, a thin dry film resist suitable for fine pitch can be used. Therefore, the fine pitch of the wiring pattern 9 can be realized.

  Further, the surface of the conductor layer 6 and the surface of the copper foil 2b are polished so that the center line surface roughness is 0.2 μm or more, and the adhesion to the dry film resist is high. Therefore, the yield when forming the wiring pattern 9 is good.

  Next, the above-described via filling plating method will be described with reference to FIG.

  First, an additive called leveler 11 and brightener 12 is added to the plating solution, and plating electrolysis is started. At the time of plating electrolysis, a large amount of leveler 11 is adsorbed on the surface of the copper foil 2a, and a large amount of brightener 12 is adsorbed on the bottom of the blind via hole 3 (FIG. 3A).

  Since the leveler 11 has a precipitation suppressing effect, the deposition of the copper plating layer 5 on the surface of the copper foil 2a is suppressed. On the other hand, since the brightener 12 has a precipitation promoting effect, the deposition of the copper plating layer 5 on the inner surface of the blind via hole 3 is promoted (FIG. 3B).

  Thereafter, when the filling rate of the copper plating layer 5 into the blind via hole 3 becomes 90% or more, the plating electrolysis is finished (FIG. 3C).

  The filling characteristic of the copper plating layer 5 into the blind via hole 3 varies depending on the composition variation of the plating solution, that is, the leveler 11, the brightener 12, and the polymer concentration. Therefore, during plating electrolysis, it is necessary to frequently analyze the concentration of the additive in the plating solution and to control the plating solution composition to be constant.

  Here, the additive in the plating solution is decomposed together with the plating electrolysis, and a part thereof accumulates in the plating solution as a decomposition product (waste product). As the decomposition products accumulate, the filling rate into the blind via hole 3 is deteriorated.

  FIG. 5 shows how the decomposition products deteriorate the filling rate into the blind via hole 3. Immediately after the start of plating electrolysis, there is little accumulation of decomposition products, and a high filling rate is obtained (FIG. 5 (a)). However, as the plating electrolysis proceeds using the same plating solution, the accumulation of decomposition products gradually proceeds and the filling rate begins to deteriorate (FIG. 5B). As the decomposition products further accumulate, the filling rate is further deteriorated (FIG. 5 (c)). Therefore, it is necessary to periodically filter the decomposition products using an activated carbon filter or the like.

  In order to prevent the filling rate from deteriorating due to accumulation of decomposition products, it is an effective means to increase the thickness of the copper plating layer 5 deposited on the surface of the copper foil 2a. The necessary thickness of the copper plating layer 5 varies depending on the diameter and depth of the blind via hole 3, but the thicker the copper plating layer 5 deposited on the surface of the copper foil 2a, the higher the filling rate tends to be stably obtained. is there. Generally, when the thickness of the copper plating layer 5 deposited on the surface of the copper foil 2a is 5 μm or less, it is difficult to stabilize the filling rate.

  However, if the copper plating layer 5 deposited on the surface of the copper foil 2a becomes thick, there is a problem that it becomes difficult to make the wiring pattern 9 fine pitch.

  Therefore, in this embodiment, in order to stably obtain a high filling rate, a copper plating layer 5 of 5 μm or more is once deposited on the surface of the copper foil 2a, and then the conductor layer 6 is polished and thinned. It is said.

Hereinafter, Example 1 and Comparative Examples 1 to 3 will be described using Table 1.

Example 1
A double-sided wiring tape carrier for a semiconductor device was manufactured by the method shown in the present embodiment.

  The thickness of the polyimide tape 2 was 25 μm, and the thicknesses of the copper foil 2a and the copper foil 2b were 9 μm.

  When performing the via filling plating, the concentration of the plating solution was a copper sulfate concentration of 200 g / L, a sulfuric acid concentration of 50 g / L, and a chlorine ion concentration of 500 mg / L.

  As the additive, JGB (Janus Green B) was used as the leveler 11, SPS (SPS (3-sulfopropyl) disulfide) as the brightener 12, and PEG (polyethylene glycol) as the polymer. The leveler 11, the brightener 12, and the polymer concentration were all 100 ppm.

  The current density was 1 A / dm 2, the plating time was 45 minutes, and the predetermined thickness of the copper plating layer 5 deposited on the copper foil 2a was 10 μm.

  After the formation of the copper plating layer 5, the conductor layer 6 was chemically polished so that the thickness d1 of the conductor layer 6 was 14 μm or less.

After chemical polishing, a wiring pattern 9 was formed using a dry photoresist having a thickness of 10 μm. At that time, the wiring pitch 10 of the wiring pattern 9 of the copper foil 2a was set to 45 μm, and the target value of the lead width of the leads constituting the wiring pattern 9 was set to 22.5 ± 5 μm.
Further, the wiring pitch 10 of the wiring pattern 9 of the copper foil 2b was set to 50 μm, and the target value of the lead width of the leads constituting the wiring pattern 9 was set to 25 ± 6 μm.

  Under the above conditions, 10 lots of 100 m double-sided wiring tape carriers for a semiconductor device, in which a plurality of units are arranged, were prepared. Thereafter, the following evaluation was performed on the first unit of each lot.

  The average filling rate and variation were measured for 10 units. As a result, the average filling rate was as high as 97%, and the variation was as small as 2.2% and was stable.

  A reliability test was conducted on 5 units. As a result of conducting a 1000 cycle temperature cycle test (TCT) in the range of −55 ° C. to 125 ° C., all units passed. In addition, as a result of performing a high temperature and high pressure bias test (THB) at a temperature of 85 ° C., a humidity of 85%, a bias voltage of 3.5 V, and 1000 hours, all the units passed.

  The stability of wiring formation was evaluated for 10 units. With respect to the target value of the lead width, the process capability index (Cpk) was 1.33 or more as a pass condition. As a result, the average lead width of the wiring pattern 9 of the copper foil 2a was 21.2 μm, and Cpk was 1.35, which passed. On the other hand, the average lead width of the wiring pattern 9 of the copper foil 2b was 24.5 μm, and Cpk was 1.33, which passed.

(Comparative Example 1)
A double-sided wiring tape carrier for semiconductor devices was manufactured by the conformal plating method shown in FIG.

 First, the conductive thin film 4 was formed after forming the blind via hole 3 in the tape base material 1 on the same conditions as Example 1 (FIG. 6 (a)-(d)).

Then, the copper plating layer 5 was formed using the conformal plating method (FIG.6 (e)). In this manufacturing method, since no additive is added to the plating solution, the copper plating layer 5 is deposited at a uniform rate both on the surface of the copper foil 2a and on the inner surface of the blind via hole 3.
The predetermined thickness of the copper plating layer 5 deposited on the copper foil 2a was 15 μm, and the total thickness d1 of the conductor layer 6 was 24 μm.

  After the formation of the copper plating layer 5, chemical polishing was not performed. Thereafter, the wiring pattern 9, the insulating layer 7, and the surface treatment layer 8 were formed under the same conditions as in Example 1 (FIGS. 6F to 6H).

  Under these conditions, 10 lots of 100 m double-sided wiring tape carriers for a semiconductor device, in which a plurality of units are arranged, were prepared. Thereafter, the following evaluation was performed on the first unit of each lot.

  A conformal plating method is used, and the interior of the blind via hole is not filled with the copper plating layer 5 as shown in FIG. Therefore, the average filling rate and its variation were not measured.

  The temperature cycle test (TCT) passed all units. On the other hand, the high temperature and high pressure bias test (THB) was rejected because there was a unit in which the copper residue was generated at the lead bottom because the conductor layer 6 was thick.

  The average lead width of the wiring pattern 9 of the copper foil 2b was 23.5 μm, and Cpk was 1.44, which passed. However, the average lead width of the wiring pattern 9 of the copper foil 2a was 24 μm, and Cpk was 0.4, which was not acceptable.

(Comparative Example 2)
A double-sided wiring tape carrier for a semiconductor device was manufactured by a conventional via filling plating method without polishing.

  The thickness of the copper plating layer 5 deposited on the surface of the copper foil 2a was 10 μm, and the total thickness d1 of the conductor layer 6 was 19 μm. Chemical polishing was not performed.

  Other conditions are the same as in the first embodiment. Under these conditions, 10 lots of 100 m double-sided wiring tape carriers for a semiconductor device, in which a plurality of units are arranged, were prepared. Thereafter, the following evaluation was performed on the first unit of each lot.

 The average filling rate was as high as 97%, and the variation was stable at 2.2%.

  For the temperature cycle test (TCT), all units passed. However, the high temperature and high pressure bias test (THB) was rejected because there was a unit in which the copper residue at the lead bottom occurred because the conductor layer 6 was thick.

  The average lead width of the wiring pattern 9 of the copper foil 2b was 20.5 μm, and Cpk was 1.35, which passed. However, the average lead width of the wiring pattern 9 of the copper foil 2a was 25 μm, and Cpk was 0.8, which was unacceptable.

(Comparative Example 3)
A double-sided wiring tape carrier for a semiconductor device was manufactured using a conventional via filling plating method without polishing.

  The thickness of the copper plating layer 5 deposited on the surface of the copper foil 2a was 5 μm, and the total thickness d1 of the conductor layer 6 was 14 μm. Chemical polishing was not performed.

  Other conditions are the same as in the first embodiment. Under these conditions, 10 lots of 100 m double-sided wiring tape carriers for a semiconductor device, in which a plurality of units are arranged, were prepared. Thereafter, the following evaluation was performed on the first unit of each lot.

  The thickness of the copper plating layer 5 deposited on the surface of the copper foil 2a was insufficient, the average filling rate decreased to 44.5% due to the influence of decomposition products, and the variation increased to 21.5%.

  For the high temperature high pressure bias test (THB), all units passed. However, the temperature cycle test (TCT) was rejected because there was a unit in which cracks occurred inside the blind via hole 3.

  The average lead width of the wiring pattern 9 of the copper foil 2a was 27 μm, and Cpk was 1.35, which passed. Moreover, the average lead width of the wiring pattern 9 of the copper foil 2b was 20.8 μm, and Cpk was 1.52, which passed.

It is explanatory drawing of the manufacturing method of the double-sided wiring tape carrier for semiconductor devices concerning embodiment of this invention. It is sectional drawing of the double-sided wiring tape carrier for semiconductor devices concerning embodiment of this invention. It is explanatory drawing of the via filling plating method. It is explanatory drawing which shows the filling rate of the copper plating layer in a blind via hole. It is explanatory drawing of a mode that a filling rate deteriorates by accumulation | storage of a decomposition product. It is explanatory drawing of the manufacturing method of the double-sided wiring tape carrier for semiconductor devices by a conformal plating method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Tape base material 2 Polyimide tape 2a Copper foil 2b Copper foil 3 Blind via hole 4 Conductive thin film 5 Copper plating layer 6 Conductive layer 7 Insulating layer 8 Surface treatment layer 9 Wiring pattern 10 Pitch 11 Leveler 12 Brighter

Claims (13)

A three-layer tape base material in which the first conductor foil and the second conductor foil are respectively attached to both surfaces of the insulating tape;
A blind via hole provided so as to pass through the first conductive foil and the insulating tape in the thickness direction of the tape base material, and a bottom surface thereof being closed by the second conductive foil;
A metal plating layer formed on the entire surface of the first conductor foil so as to fill the entire interior of the blind via hole, and conducting the first conductor foil and the second conductor foil;
The back surface of the first conductor foil is used as a reference surface, and the total thickness from the reference surface to the surface of the conductor layer composed of the first conductor foil and the metal plating layer is 15 μm or less. Double-sided wiring tape carrier for semiconductor devices.   The double-sided wiring tape carrier for a semiconductor device according to claim 1, wherein the surface of the conductive layer is a rough surface.   The double-sided wiring tape carrier for a semiconductor device according to claim 1 or 2, wherein the thickness of the second conductor foil is 15 µm or less.   4. The double-sided wiring tape carrier for a semiconductor device according to claim 1, wherein the center line surface roughness of the surface of the conductor layer and the surface of the second conductor foil is 0.2 μm or more. 5. .   5. The semiconductor according to claim 1, wherein a wiring pattern is formed on the first conductor foil and the second conductor foil, and a wiring pitch of the wiring pattern is 60 μm or less. Double-sided wiring tape carrier for equipment. Forming a three-layer tape base by affixing the first conductor foil and the second conductor foil to both surfaces of the insulating tape,
A step of forming a blind via hole whose bottom surface is closed by the second conductive foil by punching the first conductive foil and the insulating tape in the thickness direction of the tape base;
By forming a metal plating layer having a predetermined thickness on the entire surface of the first conductor foil, the entire interior of the blind via hole is filled with metal plating, and the first conductor foil, the second conductor foil, A process of conducting,
With the back surface of the first conductor foil as a reference surface, the total thickness from the reference surface to the surface of the conductor layer composed of the first conductor foil and the metal plating layer is equal to or less than the reference thickness. A method of manufacturing a double-sided wiring tape carrier for a semiconductor device, comprising a step of cutting the surface side of the conductor layer.   The method for manufacturing a double-sided wiring tape carrier for a semiconductor device according to claim 6, wherein the predetermined thickness of the metal plating layer is 5 μm or more.   8. The method for manufacturing a double-sided wiring tape carrier for a semiconductor device according to claim 6, wherein the reference thickness is 15 [mu] m or less. In the step of cutting the surface side of the conductor layer,
9. The method according to claim 6, further comprising a step of polishing the surface of the conductor layer and the surface of the second conductor foil so that the center line surface roughness is 0.2 μm or more. Manufacturing method of double-sided wiring tape carrier for semiconductor device. After the step of forming the blind via hole and before the step of forming the metal plating layer,
And forming a conductive thin film made of any one of tin-palladium or a compound thereof, nickel or a compound thereof, graphite, conductive carbon, and a conductive polymer on an inner surface of the blind via hole. Item 10. A method for producing a double-sided wiring tape carrier for a semiconductor device according to any one of Items 6 to 9. After the step of cutting the surface side of the conductor layer,
Laminating the surface of the conductor layer and the surface of the second conductor foil with a dry film resist;
The method for manufacturing a double-sided wiring tape carrier for a semiconductor device according to any one of claims 6 to 10, further comprising a step of etching the conductive layer and the second conductive foil to form a wiring pattern.   12. The method of manufacturing a double-sided wiring tape carrier for a semiconductor device according to claim 11, wherein the dry film resist has a thickness of 20 [mu] m or less. After the step of forming the wiring pattern,
13. The double-sided wiring tape carrier for a semiconductor device according to claim 11, comprising a step of forming an insulating layer such as a thermosetting or photosensitive solder resist or a coverlay on the surface of the wiring pattern. Production method.