JP2004128177A - Wiring board and its manufacturing method, and semiconductor device - Google Patents

Wiring board and its manufacturing method, and semiconductor device Download PDF

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Publication number
JP2004128177A
JP2004128177A JP2002289550A JP2002289550A JP2004128177A JP 2004128177 A JP2004128177 A JP 2004128177A JP 2002289550 A JP2002289550 A JP 2002289550A JP 2002289550 A JP2002289550 A JP 2002289550A JP 2004128177 A JP2004128177 A JP 2004128177A
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Japan
Prior art keywords
wiring
plating
insulating substrate
main surface
wiring board
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JP2002289550A
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JP3937993B2 (en
Inventor
Satoshi Chinda
珍田　聡
Mamoru Onda
御田　護
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To increase the productivity of a wiring board wherein a first interconnection and a second interconnection, which are formed on a front and a rear face of an insulation substrate respectively, are connected via a blind via hole. <P>SOLUTION: A method of manufacturing the wiring board comprises a process of forming an interconnection connecting conductor which includes a first plating formation process wherein first plating 3A thinner than a thickness of the insulation substrate 1 is formed inside the blind via hole by electroplating with a second conductor film as an electrode (cathode), and a second plating formation process wherein second plating 3B is formed on the first conductor film and on the first plating by electroplating with the first conductor film or both the first conductor film and the second conductor film as an electrode (cathode). In the first plating formation process, the current density of electroplating is set higher than in the second plating formation process. This method allows electroplating with a sufficiently large current density, and hence increases the productivity. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、配線板の製造方法に関し、特に、絶縁基板の両面に形成された配線がブラインドビアで接続された配線板に適用して有効な技術に関するものである。
【０００２】
【従来の技術】
従来、絶縁基板の表面に配線を設けた配線板には、前記絶縁基板の第１主面に第１配線が設けられ、前記絶縁基板の第１主面の裏面（以下、第２主面と称する）に第２配線が設けられた両面配線板がある。
【０００３】
前記両面配線板は、例えば、図９及び図１０、ならびに図１１に示すように、絶縁基板１の第１主面１Ａに第１配線２Ａが設けられ、第２主面１Ｂに第２配線２Ｂが設けられている。ここで、図１０は図９の領域ＡＲ３の拡大図、図１１は図１０のＢ−Ｂ’線での断面図である。
【０００４】
また、前記両面配線板は、前記第１配線２Ａと前記第２配線２Ｂとは、図１１に示したように、前記第１配線２Ａ及び前記絶縁基板１を貫通して前記第２配線２Ｂに達する開口部（ブラインドビアホール；Ｂｌｉｎｄ　Ｖｉａ　Ｈｏｌｅ）ＢＶＨに設けられた配線接続導体３により電気的に接続されている。前記配線接続導体３は、例えば、電気銅めっきでなり、図１１に示したように、前記第１配線２Ａ上にも前記配線接続導体（電気銅めっき）３の薄い層が設けられている。以下、前記配線接続導体３のうち、前記ブラインドビアホールＢＶＨ内に設けられた部分を、ブラインドビアと称する。
【０００５】
また、前記第１配線２Ａ（配線接続導体３）及び前記第２配線２Ｂの表面には、例えば、金めっき、錫めっき、錫銀合金めっきなどの機能めっき４が設けられている。
【０００６】
また、前記絶縁基板１は、例えば、ポリイミドテープのように一方向に長尺なテープ状であり、図９に示したような、配線板として用いる領域ＡＲ４が繰り返し設けられている。
【０００７】
前記両面配線板を製造するときには、まず、図１２（ａ）に示すように、絶縁基板１の第１主面１Ａに第１導体膜２Ａ’を接着し、前記絶縁基板１の第２主面１Ｂに第２導体膜２Ｂ’を接着するとともに、前記第１導体膜２Ａ’及び前記絶縁基板１を貫通して前記第２導体膜２Ｂ’に達する開口部（ブラインドビアホール）ＢＶＨを形成する。
【０００８】
このとき、前記ブラインドビアホールＢＶＨは、例えば、前記絶縁基板１の第１主面１Ａに銅箔などの第１導体膜２Ａ’を接着し、前記絶縁基板１の第２主面１Ｂに第２導体膜２Ｂ’を接着した後、前記第１導体膜２Ａ’上から炭酸ガスレーザなどのレーザ光を照射して形成する。
【０００９】
また、前記ブラインドビアホールＢＶＨは、例えば、前記絶縁基板１の第１主面１Ａに前記第１導体膜２Ａ’を接着し、金型（抜き型）を用いた打ち抜き加工で貫通穴を形成した後、前記絶縁基板１の第２主面１Ｂに前記第２導体膜２Ｂ’を接着してもよい。このとき、前記第２導体膜２Ｂ’を接着することにより前記絶縁基板１の貫通穴の開口端がふさがれた状態になり、ブラインドビアホールＢＶＨとなる。
【００１０】
次に、図１２（ｂ）に示すように、前記ブラインドビアホールＢＶＨ内及び前記第１導体膜２Ａ’上に配線接続導体３を形成する。このとき、前記配線接続導体３は、例えば、電気銅めっきにより形成する（例えば、特許文献１参照）。
なお、ＢＶＨ内壁には無電解銅めっきやパラジウム系触媒による導通処理が前処理工程で必要である。
【００１１】
またこのとき、前記電気銅めっきは、前記ブラインドビアホールＢＶＨ内に選択的に形成され、且つ前記第１導体膜２Ａ’上に形成されるめっきの平坦性をよくするために、専用のめっき液（めっき浴）を用い、電流密度を２Ａ／ｄｍ２程度で行う。
【００１２】
またこのとき、例えば、前記ブラインドビアホールＢＶＨの開口径が６０μｍであり、深さが５０μｍであるときに、前記めっき条件により、前記ブラインドビアホールＢＶＨ内を前記配線接続導体３で完全に埋め込むには約４０分かかる。またこのとき、前記第１導体膜２Ａ’上に成膜されるめっきは１０μｍ程度増加する。
【００１３】
次に、図１２（ｃ）に示すように、前記第１導体膜２Ａ’及び前記第１導体膜２Ａ’上の配線接続導体３の不要な部分を除去して第１配線２Ａを形成するとともに、前記第２導体膜２Ｂ’の不要な部分を除去して第２配線２Ｂを形成する。
【００１４】
その後、前記第１配線２Ａ（配線接続導体３）及び前記第２配線２Ｂの表面に、例えば、金めっき、錫めっき、錫銀合金めっきなどの機能めっき４を形成すると、図１１に示したような配線板が得られる。
【００１５】
前記両面配線板は、例えば、ＬＧＡ型の半導体装置に用いられ、例えば、図１３に示すように、前記配線板の第１配線２Ａが設けられた面に半導体チップ５を設け、前記第１配線２Ａと前記半導体チップ５の外部電極５０１と接続導体（バンプ）６により電気的に接続する。また、前記配線板と前記半導体チップ５の間には、絶縁体７を設け、前記第１配線２Ａと前記半導体チップ５の外部電極５０１との接続部を封止する。またこのとき、前記第２配線２Ｂは、電子装置（電子モジュール）を形成するための実装基板などに設けられた配線（端子）と接続される外部接続端子（ランド）として用いられる。
【００１６】
【特許文献】
特開平１１−１０２９３７号公報（第３〜５頁、第１図）
【００１７】
【発明が解決しようとする課題】
しかしながら、前記従来の技術では、前記配線接続導体３を形成するための電気銅めっきを行うときに、電流密度が小さいので、前記ブラインドビアホールＢＶＨ内に前記銅めっきを充填させる時間が長くなり、生産性が悪いという問題があった。また、前記配線板の生産性が悪いため、前記配線板の製造コストが高くなるという問題があった。
【００１８】
また、前記ブラインドビアホールＢＶＨ内の配線接続導体（ブラインドビア）３は、前記絶縁基板１の熱膨張などによりはがれやクラックが発生して断線するのを防ぐために、なるべく厚く形成したほうがよい。しかしながら、従来の方法で形成した場合、電流密度が低く、めっきの成長速度が遅いので、前記ブラインドビアホール内の銅めっきを厚くすると、図１４に示すように、前記第１導体膜２Ａ’上のめっきも厚くなる。前記第１導体膜２Ａ’上のめっきが厚くなり、前記第１導体膜２Ａ’と前記第１導体膜２Ａ’上のめっきの厚さとの和Ｔ２が大きくなると、エッチングしたときに、エッチング残りや配線の形状不良が起こりやすい。そのため、前記第１配線２Ａの微細化が難しくなるという問題があった。
【００１９】
また、前記第１導体膜２Ａ’上のめっきが厚くなると、前記第１導体膜２Ａ’と前記第１導体膜２Ａ’上のめっきの厚さとの和Ｔ２と、前記第２導体膜２Ｂ’の厚さＴ３の差が大きくなるので、前記第１導体膜２Ａ’及び前記めっきと、前記第２導体膜２Ｂ’を同時にエッチングすると、前記第１配線２Ａもしくは前記第２配線２Ｂに形状不良が起こりやすい。そのため、前記第１導体膜２Ａ’上のめっきを研磨して薄くしたり、前記第１配線２Ａと前記第２配線２Ｂを個別に形成したりする必要があり、配線板の生産性が低下するという問題があった。
【００２０】
本発明の目的は、絶縁基板の第１主面に設けられた第１配線と前記絶縁基板の第２主面に設けられた第２配線がブラインドビアで接続されている配線板の生産性を向上させることが可能な技術を提供することにある。
【００２１】
本発明の他の目的は、絶縁基板の第１主面に設けられた第１配線と前記絶縁基板の第２主面に設けられた第２配線がブラインドビアで接続されている配線板において、ブラインドビアの接続性を向上させるとともに、配線の微細化を容易にすることが可能な技術を提供することにある。
【００２２】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。
【００２３】
【課題を解決するための手段】
本願において開示される発明の概要を説明すれば、以下の通りである。
【００２４】
（１）絶縁基板の第１主面に第１導体膜を接着し、前記絶縁基板の第１主面の裏面（第２主面）に第２導体膜を接着するとともに、前記前記第１導体膜及び前記絶縁基板を貫通して前記第２導体膜に達する開口部（以下、ブラインドビアホールと称する）を形成するブラインドビアホール形成工程と、前記ブラインドビアホール内および前記第１導体膜の表面に配線接続導体を形成して前記第１導体膜と前記第２導体膜を電気的に接続する配線接続導体形成工程と、前記第１導体膜及び前記配線接続導体の不要な部分を除去して第１配線を形成し、前記第２導体膜の不要な部分を除去して第２配線を形成する配線形成工程とを備える配線板の製造方法であって、前記配線接続導体形成工程は、前記第２導体膜を電極（陰極）とした電気めっきにより、前記ブラインドビアホール内に、前記絶縁基板の厚さよりも薄い第１めっきを形成する第１めっき形成工程と、前記第１導体膜、あるいは前記第１導体膜及び前記第２導体膜を電極（陰極）とした電気めっきにより、前記第１導体膜及び前記第１めっき上に第２めっきを形成する第２めっき形成工程とを備え、前記第１めっき形成工程は、電気めっきの電流密度を、前記第２めっき形成工程の電気めっきの電流密度よりも高くして行う配線板の製造方法である。
【００２５】
前記（１）の手段によれば、前記配線接続導体形成工程を、前記第１めっき形成工程と前記第２めっき形成工程に分けることにより、途中までは電流密度が大きい状態で電気めっきを行うことができる。一般に、電気めっきの厚さは電流密度に比例するので、前記（１）の手段を用いることにより、従来の配線板の製造方法のように最初から電流密度が小さい状態で電気めっきを行う場合に比べて、短時間で前記配線接続導体を形成することができる。そのため、前記配線板の生産性が向上し、前記配線板の製造コストを低減することができる。
【００２６】
また、前記第１めっき形成工程において、電流密度が高い状態で前記第１めっきを形成した後、前記第２めっき形成工程で前記第２めっきを形成することにより、前記ブラインドビアホール内の配線接続導体（ブラインドビア）を厚くすることができる一方で、前記第１導体膜上の配線接続導体（第２めっき）が厚くなるのを防ぐことができる。そのため、前記ブラインドビアの接続性を向上させるとともに、前記第１配線の微細化を容易にすることができる。
【００２７】
またこのとき、前記第１めっきは、電流密度が大きい状態で形成しているので、前記第１めっきと前記第１導体膜とが電気的に接続されると、電流密度が不安定になり、前記第１導体膜上のめっきの平坦性が悪くなる可能性がある。そのため、前記第１めっきの厚さは、前記第１導体膜と電気的に接続されないように、前記絶縁基板の厚さよりも薄くすることが好ましく、特に、前記ブラインドビアホールの深さの３分の１から２分の１程度の厚さに形成することが好ましい。
【００２８】
（２）絶縁基板の第１主面に第１配線が設けられ、前記絶縁基板の第１主面の裏面（第２主面）に第２配線が設けられており、前記第１配線と前記第２配線とは、前記第１配線及び前記絶縁基板を貫通して前記第２配線に達する開口部（以下、ブラインドビアホールと称する）に設けられた配線接続導体により電気的に接続されている配線板であって、前記配線接続導体は、前記ブラインドビアホールを通して前記絶縁基板の第１主面に露出する第２配線の上に設けられ、且つ前記絶縁基板の厚さよりも薄い第１めっきと、前記第１めっき上に設けられた第２めっきからなる配線板である。
【００２９】
前記（２）の手段によれば、前記配線接続導体が前記第１めっきと前記第２めっきからなることにより、前記ブラインドビアホール内の配線接続導体を厚くすることができる一方で、前記第１配線上のめっき（第２めっき）が厚くなるのを防ぐことができる。そのため、前記第１配線と前記第２配線の接続信頼性を向上させるとともに、前記第１配線を微細化することができる。
【００３０】
また、前記（２）の手段の配線板は、例えば、前記（１）の手段を用いて製造することで得られる。そのため、前記第１めっきの厚さは、例えば、前記ブラインドビアホールの深さの３分の１から２分の１程度の厚さになっている。
【００３１】
（３）絶縁基板の第１主面に第１配線が設けられ、前記絶縁基板の第１主面の裏面（第２主面）に第２配線が設けられており、前記第１配線と前記第２配線とは、前記第１配線及び前記絶縁基板を貫通して前記第２配線に達する開口部（以下、ブラインドビアホールと称する）に設けられた配線接続導体により電気的に接続されている配線板と、前記配線板上に設けられた半導体チップとを有し、前記配線板の第１配線もしくは第２配線と前記半導体チップの外部電極とが電気的に接続された半導体装置であって、前記配線接続導体は、前記ブラインドビアホールを通して前記絶縁基板の第１主面に露出する第２配線の上に設けられ、且つ前記絶縁基板の厚さよりも薄い第１めっきと、前記第１めっき上に設けられた第２めっきからなる半導体装置である。
【００３２】
前記（３）の手段によれば、前記（２）の手段と同様に、前記ブラインドビアホール内の配線接続導体を厚くすることができる一方で、前記第１配線上のめっき（第２めっき）が厚くなるのを防ぐことができる。そのため、前記第１配線と前記第２配線の接続信頼性を向上させるとともに、前記第１配線を微細化することができる。
【００３３】
また、前記（３）の手段の半導体装置が備える配線板は、例えば、前記（１）の手段を用いて製造することで得られる。そのため、前記第１めっきの厚さは、例えば、前記ブラインドビアホールの深さの３分の１から２分の１程度の厚さになっている。
【００３４】
以下、本発明について、図面を参照して実施の形態（実施例）とともに詳細に説明する。
【００３５】
なお、実施例を説明するための全図において、同一機能を有するものは、同一符号を付け、その繰り返しの説明は省略する。
【００３６】
【発明の実施の形態】
（実施例）
図１乃至図３は、本発明による一実施例の配線板の概略構成を示す模式図であり、図１は配線板の平面図、図２は図１の領域ＡＲ１の拡大平面図、図３は図２のＡ−Ａ’線での断面図である。
【００３７】
図１において、１は絶縁基板、１Ａは絶縁基板の第１主面、１Ｂは絶縁基板の第２主面、２Ａは第１配線（第１導体パターン）、２Ｂは第２配線（第２導体パターン）、３Ａは第１めっき、３Ｂは第２めっき、４は機能めっき、ＢＶＨはブラインドビアホール（Ｂｌｉｎｄ　Ｖｉａ　Ｈｏｌｅ）である。
【００３８】
本実施例の配線板は、図１及び図２、ならびに図３に示すように、絶縁基板１の第１主面１Ａに第１配線（第１導体パターン）２Ａが設けられ、前記絶縁基板１の第１主面１Ａの裏面（以下、第２主面と称する）１Ｂに第２配線（第２導体パターン）２Ｂが設けられている両面配線板である。
【００３９】
また、前記第１配線２Ａと前記第２配線２Ｂとは、図３に示すように、前記第１配線２Ａ及び前記絶縁基板１を貫通して前記第２配線２Ｂに達する開口部（以下、ブラインドビアホールと称する）ＢＶＨに設けられた配線接続導体（以下、ブラインドビアと称する）により電気的に接続されている。このとき、前記ブラインドビアは、図３に示したように、前記ブラインドビアホールＢＶＨの底面、すなわち前記第２配線２Ｂ上に設けられた第１めっき３Ａと、前記第１めっき３Ａ上及び前記第１配線２Ａ上に設けられた第２めっき３Ｂからなる。前記第１めっき３Ａ及び前記第２めっき３Ｂは、例えば、電気銅めっきでなる。
【００４０】
また、前記第１配線２Ａ（第２めっき３Ｂ）及び前記第２配線２Ｂの表面には、図３に示したように、機能めっき４が設けられている。前記機能めっき４は、例えば、半導体チップを実装するときの接合材としての機能を有するめっきであり、金めっき、錫めっき、錫銀合金めっきなどでなる。
【００４１】
また、本実施例の配線板は、例えば、ＬＧＡ（Ｌａｎｄ　Ｇｒｉｄ　Ａｒｒａｙ）などの半導体装置のインターポーザとして用いられる配線板であって、一般に、ポリイミドテープなどの一方向に長尺なテープ状の絶縁基板１に、図１に示したような、配線板として用いる領域ＡＲ２が繰り返し設けられている。
【００４２】
図４及び図５は、本実施例の配線板の製造方法を説明するための模式図であり、図４（ａ）はブラインドビアホールを形成する工程の断面図、図４（ｂ）は第１めっきを形成する工程の断面図、図４（ｃ）は第２めっきを形成する工程の断面図、図５は第１配線及び第２配線を形成する工程の断面図である。また、図４（ａ）及び図４（ｂ）、ならびに図４（ｃ）において、２Ａ’は第１導体膜、２Ｂ’は第２導体膜である。
【００４３】
以下、図４及び図５に沿って、本実施例の配線板の製造方法について説明する。
【００４４】
まず、図４（ａ）に示すように、絶縁基板１の第１主面１Ａに第１導体膜２Ａ’を接着し、前記絶縁基板１の第２主面１Ｂに第２導体膜２Ｂを接着するとともに、前記第１導体膜２Ａ’及び前記絶縁基板１を貫通して前記第２導体膜２Ｂ’に達する開口部（ブラインドビアホール）ＢＶＨを形成する。
【００４５】
このとき、前記ブラインドビアホールＢＶＨは、例えば、前記絶縁基板１に前記第１導体膜２Ａ’及び前記第２導体膜２Ｂ’を接着した後、前記第１導体膜２Ａ’上から炭酸ガスレーザなどのレーザ光を照射して形成する。また、例えば、前記絶縁基板１に前記第１導体膜２Ａ’を接着し、金型（抜き型）を用いた打ち抜き加工で貫通穴をあけた後、前記絶縁基板１の第２主面１Ｂに前記第２導体膜２Ｂ’を接着して、前記貫通穴の一方の開口端をふさぐように形成してもよい。
【００４６】
次に、図４（ｂ）に示すように、前記ブラインドビアホールＢＶＨ内に、第１めっき３Ａを形成する。前記第１めっき３Ａは、例えば、前記第２導体膜２Ｂ’を電極（陰極）とした電気銅めっきで形成する。
【００４７】
このとき、前記第２導体膜２Ｂ’を電極とすることにより、前記第１導体膜２Ａ’上にはめっきが成長しないので、前記第１めっき３Ａは、電流密度が大きい状態で形成することができ、例えば、電流密度を２０Ａ／ｄｍ２程度にすることができる。
【００４８】
またこのとき、前記第１めっき３Ａが成長して前記第１導体膜２Ａ’と接触してしまうと、前記第１導体膜２Ａ’も電極となり、電流密度が不安定な状態で前記第１導体膜２Ａ’上にめっきが形成され、前記第１導体膜２Ａ’の平坦性が悪くなってしまう。そのため、前記第１めっき３Ａは、前記絶縁基板１の厚さＴ１よりも薄く形成することが好ましく、例えば、前記ブラインドビアホールＢＶＨの深さ、すなわち前記絶縁基板１と前記第１導体膜２Ａ’の厚さとの和の３分の１から２分の１程度の厚さになるようにする。
【００４９】
以上のようなことから、例えば、前記ブラインドビアホールＢＶＨの開口径が６０μｍであり、深さ、言い換えると前記絶縁基板１及び前記第１導体膜２Ａ’の厚さの和が５０μｍであるとすると、前記第１めっき３Ａは、３５μｍ程度の厚さするのが好ましく、電流密度を２０Ａ／ｄｍ２にした場合、前記第１めっき３Ａは、約８分で形成することができる。
【００５０】
次に、図４（ｃ）に示すように、前記ブラインドビアホールＢＶＨ内の第１めっき３Ａ上及び前記第１導体膜２Ａ’上に、第２めっき３Ｂを形成する。前記第２めっき３Ｂは、前記第１めっき３Ａと同様に、電気銅めっきで形成するが、前記第１導体膜２Ａ’上に形成されるめっきの平坦性をよくするために、電流密度は、例えば、２Ａ／ｄｍ２程度にして行う。
【００５１】
このとき、前記ブラインドビアホールＢＶＨ内には、すでに前記第１めっき３Ａが形成されているため、前記第１めっき３Ａ上の第２めっき３Ｂの厚さは５μｍ程度あれば十分であるが、図４（ｃ）に示したように、前記ブラインドビアホールＢＶＨを完全に埋め込むまで形成した場合でも、約１２分で形成することができる。
【００５２】
またこのとき、前記第２めっき３Ｂの形成するために必要な時間が短いので、前記第１導体膜２Ａ’上に形成されるめっき（第２めっき３Ｂ）が厚くなるのを防げる。そのため、前記第１導体膜２Ａ’と前記第１導体膜２Ａ’上の第２めっき３Ｂの厚さとの和Ｔ２と、前記第２導体膜２Ｂ’の厚さＴ３の差を小さくすることができる。
【００５３】
本実施例の配線板の製造方法を用いた場合、前記配線接続導体（ブラインドビア）を形成する工程には、前記第１めっき３Ａを形成する工程と前記第２めっき３Ｂを形成する工程の他に、例えば、洗浄工程などの工程が必要となるが、それらの工程でかかる時間を含めても、２５分から３０分程度で前記第１めっき３Ａ及び前記第２めっき３Ｂを形成することができる。一方、従来の配線板の製造方法のように、最初から電流密度が小さい状態で配線接続導体（ビア）３を形成した場合、前記ブラインドビアホールＢＶＨの開口径が６０μｍであり、深さが５０μｍであるとし、前記ブラインドビアホールＢＶＨ内の配線接続導体３の厚さが１５μｍ程度になるようにするには、電気銅めっきを行う工程だけで約４０分かかり、洗浄工程などを含めると５０分から１時間かかる。つまり、本実施例の配線板の製造方法を適用することで、前記ブラインドビアホールＢＶＨ内に配線接続導体を形成する工程に用する時間が約半分になり、配線板の製造にかかる時間を短縮することができる。
【００５４】
次に、図５に示すように、前記第１導体膜２Ａ’及び前記第１導体膜２Ａ’上の第２めっき３Ｂの不要な部分を除去して第１配線２Ａを形成し、前記第２導体膜２Ｂ’の不要な部分を除去して第２配線２Ｂを形成する。このとき、前記第１配線２Ａは、エッチングで不要な部分を除去して形成するが、前記第１導体膜２０１上の第２めっき３Ｂが薄いので、前記第１配線２Ａの微細化が容易になる。
【００５５】
その後、前記第１配線２Ａの表面及び前記第２配線２Ｂの表面に、機能めっき４を形成すると、図３に示したような配線板が得られる。前記機能めっき４は、例えば、金めっき、ニッケルめっきを下地とした金めっき、錫めっき、錫銀合金めっきなどで形成する。
【００５６】
図６は、本実施例の配線板を用いた半導体装置の概略構成を示す模式断面図である。また、図６において、５は半導体チップ、５０１は半導体チップの外部電極、６は接続導体（バンプ）、７は絶縁体である。
【００５７】
本実施例の配線板は、例えば、ＬＧＡ型の半導体装置のインターポーザとして用いられ、図６に示すように、前記配線板の第１配線２Ａが設けられた面に半導体チップ５を設け、前記第１配線２Ａと前記半導体チップ５の外部電極５０１と接続導体（バンプ）６により電気的に接続する。また、前記配線板と前記半導体チップ５の間には、絶縁体７を設け、前記第１配線２Ａと前記半導体チップ５の外部電極５０１との接続部を封止する。またこのとき、前記第２配線２Ｂは、電子装置（電子モジュール）を形成するための実装基板などに設けられた配線（端子）と接続される外部接続端子（ランド）として用いられる。
【００５８】
以上説明したように、本実施例の配線板の製造方法によれば、電流密度が大きい状態で前記第１めっき３Ａを形成した後、電流密度を小さくして前記第２めっき３Ｂを薄く形成することにより、従来のように始めから電流密度が小さい状態で前記配線接続導体（ブラインドビア）３を形成する場合に比べて、短時間で配線板を形成することができる。そのため、前記配線板の生産性が向上し、前記配線板の製造コストを低減することができる。
【００５９】
また、前記ブラインドビアホールＢＶＨ内に、前記絶縁基板の厚さＴ１よりも薄く、且つ、前記ブラインドビアホールＢＶＨの深さの３分の１から２分の１程度の厚さの前記第１めっき３Ａを形成することにより、前記第１めっき３Ａ上の第２めっき３Ｂが薄くても、前記第１配線２Ａと前記第２配線２Ｂの接続信頼性を確保することができる。また、前記第１めっき３Ａ上の第２めっき３Ｂが薄い場合、前記第１配線２Ａ（第１導体膜２Ａ’）上のめっきも薄くすることができるので、前記第１配線２Ａの微細化が容易である。すなわち、本実施例の配線板の製造方法によれば、前記第１配線２Ａと前記第２配線２Ｂの接続信頼性を向上させるとともに、前記第１配線２Ａの微細化を容易にすることができる。
また、従来のビアフィリング法では、ＢＶＨ内壁に無電解銅めっき膜やパラジウム系触媒などの導通皮膜の形成が必要で、そのために複雑な前処理工程が必要であったが、本発明を用いることにより、導通皮膜の形成が必要となるので、前処理工程の大幅な簡略化を図ることができる。
【００６０】
図７及び図８は、前記実施例の配線板の応用例を説明するための模式図であり、図７は前記配線板を用いた半導体装置の概略構成を示す断面図、図８は前記配線板の拡大断面図である。
【００６１】
前記実施例で説明した配線板のように、前記絶縁基板１の第１主面１Ａに第１配線２Ａが設けられ、前記絶縁基板１の第２主面１Ｂに第２配線２Ｂが設けられた両面配線板は、図６に示したように、前記第２配線２Ｂを外部接続端子として用いるＬＧＡ型の半導体装置に用いることが多い。しかしながら、前記実施例で説明した配線板は、前記ＬＧＡ型の半導体装置に限らず、例えば、ＢＧＡ（ＢａｌｌＧｒｉｄ　Ａｒｒａｙ）、ＣＳＰ（Ｃｈｉｐ　Ｓｉｚｅ／Ｓｃａｌｅ　Ｐａｃｋａｇｅ）などの半導体装置のインターポーザとして用いることもできる。前記ＢＧＡ型の半導体装置のインターポーザとして用いた場合には、図７に示すように、前記第２配線２Ｂ上に、錫鉛合金（はんだ）などのボール状の外部接続端子８を設ければよい。
【００６２】
またこのとき、前記絶縁基板１の第２主面１Ｂ側には、図８に示したように、前記外部接続端子８を形成する領域を除く領域に、はんだ保護膜（ソルダレジスト）などの保護膜９を設ける。
【００６３】
以上、本発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において、種々変更可能であることはもちろんである。
【００６４】
【発明の効果】
本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下の通りである。
【００６５】
（１）絶縁基板の第１主面に設けられた第１配線と前記絶縁基板の第２主面に設けられた第２配線がブラインドビアで接続されている配線板の生産性を向上させることができる。
【００６６】
（２）絶縁基板の第１主面に設けられた第１配線と前記絶縁基板の第２主面に設けられた第２配線がブラインドビアで接続されている配線板において、ブラインドビアの接続性を向上させるとともに、配線の微細化を容易にすることができる。
【図面の簡単な説明】
【図１】本発明による一実施例の配線板の概略構成を示す模式平面図である。
【図２】本実施例の配線板の概略構成を示す模式図であり、図１の領域ＡＲ１の拡大平面図である。
【図３】本実施例の配線板の概略構成を示す模式図であり、図２のＡ−Ａ’線での断面図である。
【図４】本実施例の配線板の製造方法を説明するための模式図であり、図４（ａ）はブラインドビアホールを形成する工程の断面図、図４（ｂ）は第１めっきを形成する工程の断面図、図４（ｃ）は第２めっきを形成する工程の断面図である。
【図５】本実施例の配線板の製造方法を説明するための模式図であり、第１配線及び第２配線を形成する工程の断面図である。
【図６】本実施例の配線板を用いた半導体装置の概略構成を示す模式断面図である。
【図７】前記実施例の配線板の応用例を説明するための模式図であり、前記配線板を用いた半導体装置の概略構成を示す断面図である。
【図８】前記実施例の配線板の応用例を説明するための模式図であり、前記配線板の拡大断面図である。
【図９】従来の配線板の概略構成を示す模式平面図である。
【図１０】従来の半導体装置に用いられる配線板の概略構成を示す模式図であり、図９の領域ＡＲ３の拡大平面図である。
【図１１】従来の半導体装置に用いられる配線板の概略構成を示す模式図であり、図１０のＢ−Ｂ’線での断面図である。
【図１２】従来の配線板の製造方法を説明するための模式図であり、図１２（ａ）はブラインドビアホールを形成する工程の断面図、図１２（ｂ）は配線接続導体（ブラインドビア）を形成する工程の断面図、図１２（ｃ）は第１配線及び第２配線を形成する工程の断面図である。
【図１３】従来の半導体装置の概略構成を示す模式断面図である。
【図１４】従来の配線板の課題を説明するための模式断面図である。
【符号の説明】
１　絶縁基板
１Ａ　絶縁基板の第１主面
１Ｂ　絶縁基板の第２主面
２　第１配線
２Ａ　第１配線
２Ａ’　第１導体膜
２Ｂ　第２配線
２Ｂ’　第２導体膜
３　配線接続導体（ブラインドビア）
３Ａ　第１めっき
３Ｂ　第２めっき
４　機能めっき
５　半導体チップ
５０１　半導体チップの外部電極
６　接続導体（バンプ）
７　絶縁体
８　外部接続端子
９　保護膜
ＢＶＨ　ブラインドビアホール[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a wiring board, and more particularly to a technique effective when applied to a wiring board in which wirings formed on both surfaces of an insulating substrate are connected by blind vias.
[0002]
[Prior art]
Conventionally, on a wiring board having wiring provided on the surface of an insulating substrate, a first wiring is provided on a first main surface of the insulating substrate, and a back surface of the first main surface of the insulating substrate (hereinafter, referred to as a second main surface). There is a double-sided wiring board provided with a second wiring.
[0003]
In the double-sided wiring board, for example, as shown in FIGS. 9, 10 and 11, a first wiring 2A is provided on a first main surface 1A of an insulating substrate 1, and a second wiring 2B is provided on a second main surface 1B. Is provided. Here, FIG. 10 is an enlarged view of a region AR3 in FIG. 9, and FIG. 11 is a cross-sectional view taken along line BB 'in FIG.
[0004]
Further, in the double-sided wiring board, as shown in FIG. 11, the first wiring 2A and the second wiring 2B pass through the first wiring 2A and the insulating substrate 1 and are connected to the second wiring 2B. The opening (blind via hole) that reaches is electrically connected by a wiring connection conductor 3 provided in the BVH. The wiring connection conductor 3 is made of, for example, electrolytic copper plating. As shown in FIG. 11, a thin layer of the wiring connection conductor (electric copper plating) 3 is provided also on the first wiring 2A. Hereinafter, a portion of the wiring connection conductor 3 provided in the blind via hole BVH is referred to as a blind via.
[0005]
On the surfaces of the first wiring 2A (wiring connection conductor 3) and the second wiring 2B, for example, functional plating 4 such as gold plating, tin plating, or tin-silver alloy plating is provided.
[0006]
The insulating substrate 1 has a tape shape that is long in one direction, for example, such as a polyimide tape, and a region AR4 used as a wiring board as shown in FIG. 9 is repeatedly provided.
[0007]
When manufacturing the double-sided wiring board, first, as shown in FIG. 12A, a first conductive film 2A 'is bonded to a first main surface 1A of an insulating substrate 1, and a second main surface of the insulating substrate 1 is formed. A second conductive film 2B 'is bonded to 1B, and an opening (blind via hole) BVH that reaches the second conductive film 2B' through the first conductive film 2A 'and the insulating substrate 1 is formed.
[0008]
At this time, the blind via hole BVH is formed, for example, by bonding a first conductor film 2A ′ such as a copper foil to the first main surface 1A of the insulating substrate 1 and forming a second conductor film on the second main surface 1B of the insulating substrate 1. After bonding the film 2B ', the film is formed by irradiating a laser beam such as a carbon dioxide gas laser from above the first conductor film 2A'.
[0009]
The blind via hole BVH is formed, for example, by bonding the first conductive film 2A ′ to the first main surface 1A of the insulating substrate 1 and forming a through hole by punching using a die (cutting die). Alternatively, the second conductive film 2B ′ may be bonded to the second main surface 1B of the insulating substrate 1. At this time, by bonding the second conductor film 2B ', the opening end of the through hole of the insulating substrate 1 is closed, and a blind via hole BVH is formed.
[0010]
Next, as shown in FIG. 12B, a wiring connection conductor 3 is formed in the blind via hole BVH and on the first conductive film 2A ′. At this time, the wiring connection conductor 3 is formed by, for example, electrolytic copper plating (for example, see Patent Document 1).
The inner wall of the BVH needs a conduction treatment by electroless copper plating or a palladium-based catalyst in the pretreatment step.
[0011]
At this time, the electrolytic copper plating is selectively formed in the blind via hole BVH, and a dedicated plating solution (for improving the flatness of the plating formed on the first conductive film 2A ′). Current density is 2 A / dm. 2 Do about.
[0012]
Further, at this time, for example, when the opening diameter of the blind via hole BVH is 60 μm and the depth is 50 μm, it is approximately about 50% to completely fill the blind via hole BVH with the wiring connection conductor 3 under the plating conditions. It takes 40 minutes. At this time, the plating formed on the first conductor film 2A 'increases by about 10 [mu] m.
[0013]
Next, as shown in FIG. 12C, unnecessary portions of the first conductive film 2A 'and the wiring connection conductor 3 on the first conductive film 2A' are removed to form the first wiring 2A. An unnecessary portion of the second conductor film 2B 'is removed to form a second wiring 2B.
[0014]
Thereafter, when functional plating 4 such as gold plating, tin plating, or tin-silver alloy plating is formed on the surfaces of the first wiring 2A (wiring connection conductor 3) and the second wiring 2B, as shown in FIG. Wiring board is obtained.
[0015]
The double-sided wiring board is used, for example, in an LGA type semiconductor device. For example, as shown in FIG. 13, a semiconductor chip 5 is provided on the surface of the wiring board on which the first wiring 2A is provided, and the first wiring is provided. 2A is electrically connected to the external electrode 501 of the semiconductor chip 5 by a connection conductor (bump) 6. An insulator 7 is provided between the wiring board and the semiconductor chip 5 to seal a connection between the first wiring 2A and the external electrode 501 of the semiconductor chip 5. At this time, the second wiring 2B is used as an external connection terminal (land) connected to a wiring (terminal) provided on a mounting board or the like for forming an electronic device (electronic module).
[0016]
[Patent Document]
JP-A-11-102937 (pages 3 to 5, FIG. 1)
[0017]
[Problems to be solved by the invention]
However, according to the conventional technique, when performing the copper electroplating for forming the wiring connection conductor 3, the current density is low, so that the time required for filling the blind via hole BVH with the copper plating becomes longer, and the production time increases. There was a problem of poor sex. Further, the productivity of the wiring board is poor, so that there is a problem that the manufacturing cost of the wiring board is increased.
[0018]
Further, the wiring connection conductor (blind via) 3 in the blind via hole BVH is preferably formed as thick as possible in order to prevent the insulating substrate 1 from being peeled off or cracked due to thermal expansion or the like and to be disconnected. However, when formed by a conventional method, the current density is low and the growth rate of plating is low. Therefore, when the copper plating in the blind via hole is thickened, as shown in FIG. The plating also becomes thicker. When the plating on the first conductor film 2A 'becomes thicker and the sum T2 of the plating thickness on the first conductor film 2A' and the plating on the first conductor film 2A 'becomes larger, when etching is performed, the etching residue or the like remains. Wiring shape defects are likely to occur. Therefore, there is a problem that miniaturization of the first wiring 2A becomes difficult.
[0019]
When the plating on the first conductor film 2A 'becomes thicker, the sum T2 of the plating thickness on the first conductor film 2A' and the plating on the first conductor film 2A ', and the second conductor film 2B' When the thickness of the first conductor film 2A ′ and the plating and the second conductor film 2B ′ are simultaneously etched because the difference in the thickness T3 becomes large, a shape defect occurs in the first wiring 2A or the second wiring 2B. Cheap. Therefore, it is necessary to polish the plating on the first conductive film 2A 'to make it thinner, or to form the first wiring 2A and the second wiring 2B separately, which lowers the productivity of the wiring board. There was a problem.
[0020]
An object of the present invention is to reduce the productivity of a wiring board in which a first wiring provided on a first main surface of an insulating substrate and a second wiring provided on a second main surface of the insulating substrate are connected by blind vias. It is to provide a technology that can be improved.
[0021]
Another object of the present invention is a wiring board in which a first wiring provided on a first main surface of an insulating substrate and a second wiring provided on a second main surface of the insulating substrate are connected by blind vias, An object of the present invention is to provide a technology capable of improving the connectivity of blind vias and facilitating miniaturization of wiring.
[0022]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0023]
[Means for Solving the Problems]
The outline of the invention disclosed in the present application is as follows.
[0024]
(1) A first conductive film is bonded to a first main surface of an insulating substrate, a second conductive film is bonded to a back surface (second main surface) of the first main surface of the insulating substrate, and the first conductive film is bonded to the first conductive film. A blind via hole forming step of forming an opening (hereinafter, referred to as a blind via hole) penetrating a film and the insulating substrate to reach the second conductive film, and wiring connection in the blind via hole and a surface of the first conductive film. Forming a conductor and electrically connecting the first conductor film to the second conductor film; and forming a first wiring by removing unnecessary portions of the first conductor film and the wiring connection conductor. Forming a second wiring by removing unnecessary portions of the second conductor film, wherein the wiring connection conductor forming step comprises: Electroplating with film as electrode (cathode) Accordingly, a first plating forming step of forming a first plating thinner than the thickness of the insulating substrate in the blind via hole, and forming the first conductor film or the first conductor film and the second conductor film as electrodes ( A second plating step of forming a second plating on the first conductor film and the first plating by electroplating as a cathode), wherein the first plating step comprises: This is a method for manufacturing a wiring board, wherein the current density is higher than the current density of the electroplating in the second plating forming step.
[0025]
According to the means (1), the wiring connection conductor forming step is divided into the first plating forming step and the second plating forming step, so that the electroplating is performed in a state where the current density is large halfway. Can be. In general, the thickness of electroplating is proportional to the current density. Therefore, by using the means (1), when electroplating is performed in a state where the current density is low from the beginning as in the conventional method for manufacturing a wiring board, In comparison, the wiring connection conductor can be formed in a short time. Therefore, the productivity of the wiring board is improved, and the manufacturing cost of the wiring board can be reduced.
[0026]
Further, in the first plating forming step, after forming the first plating in a state where the current density is high, the second plating is formed in the second plating forming step, so that the wiring connection conductor in the blind via hole is formed. While it is possible to increase the thickness of the (blind via), it is possible to prevent the wiring connection conductor (second plating) on the first conductor film from becoming thick. Therefore, the connectivity of the blind via can be improved, and the miniaturization of the first wiring can be facilitated.
[0027]
At this time, since the first plating is formed in a state where the current density is large, when the first plating is electrically connected to the first conductor film, the current density becomes unstable, There is a possibility that the flatness of the plating on the first conductor film is deteriorated. Therefore, it is preferable that the thickness of the first plating is smaller than the thickness of the insulating substrate so as not to be electrically connected to the first conductor film, and in particular, the thickness of the blind via hole is 分 の of the depth of the blind via hole. It is preferable that the thickness is about 1 to 1/2.
[0028]
(2) A first wiring is provided on a first main surface of the insulating substrate, and a second wiring is provided on a back surface (second main surface) of the first main surface of the insulating substrate. The second wiring is a wiring that is electrically connected to a wiring connection conductor provided in an opening (hereinafter, referred to as a blind via hole) that reaches the second wiring through the first wiring and the insulating substrate. A board, wherein the wiring connection conductor is provided on the second wiring exposed on the first main surface of the insulating substrate through the blind via hole, and a first plating thinner than a thickness of the insulating substrate; It is a wiring board made of the second plating provided on the first plating.
[0029]
According to the means (2), since the wiring connection conductor is made of the first plating and the second plating, the wiring connection conductor in the blind via hole can be thickened, while the first wiring Thickness of the upper plating (second plating) can be prevented. Therefore, the connection reliability between the first wiring and the second wiring can be improved, and the first wiring can be miniaturized.
[0030]
Further, the wiring board of the means of (2) is obtained by, for example, manufacturing using the means of (1). Therefore, the thickness of the first plating is, for example, about ３ to ２ of the depth of the blind via hole.
[0031]
(3) A first wiring is provided on a first main surface of the insulating substrate, and a second wiring is provided on a back surface (second main surface) of the first main surface of the insulating substrate. The second wiring is a wiring that is electrically connected to a wiring connection conductor provided in an opening (hereinafter, referred to as a blind via hole) that reaches the second wiring through the first wiring and the insulating substrate. A semiconductor device comprising: a board; and a semiconductor chip provided on the wiring board, wherein a first wiring or a second wiring of the wiring board and an external electrode of the semiconductor chip are electrically connected, The wiring connection conductor is provided on the second wiring exposed on the first main surface of the insulating substrate through the blind via hole, and on the first plating thinner than the thickness of the insulating substrate, and on the first plating. Semiconductor made of second plating provided It is a device.
[0032]
According to the means of (3), similarly to the means of (2), the thickness of the wiring connection conductor in the blind via hole can be increased, while plating (second plating) on the first wiring can be performed. Thickness can be prevented. Therefore, the connection reliability between the first wiring and the second wiring can be improved, and the first wiring can be miniaturized.
[0033]
Further, the wiring board provided in the semiconductor device of the above-mentioned means (3) can be obtained by, for example, manufacturing using the above-mentioned means (1). Therefore, the thickness of the first plating is, for example, about ３ to ２ of the depth of the blind via hole.
[0034]
Hereinafter, the present invention will be described in detail with embodiments (examples) with reference to the drawings.
[0035]
In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.
[0036]
BEST MODE FOR CARRYING OUT THE INVENTION
(Example)
1 to 3 are schematic views showing a schematic configuration of a wiring board according to one embodiment of the present invention. FIG. 1 is a plan view of the wiring board, FIG. 2 is an enlarged plan view of a region AR1 in FIG. FIG. 3 is a sectional view taken along line AA ′ of FIG.
[0037]
In FIG. 1, reference numeral 1 denotes an insulating substrate, 1A denotes a first main surface of the insulating substrate, 1B denotes a second main surface of the insulating substrate, 2A denotes a first wiring (first conductor pattern), and 2B denotes a second wiring (second conductor). (Pattern), 3A is a first plating, 3B is a second plating, 4 is a functional plating, and BVH is a blind via hole.
[0038]
As shown in FIGS. 1, 2, and 3, the wiring board of the present embodiment includes a first wiring (first conductor pattern) 2 </ b> A provided on a first main surface 1 </ b> A of an insulating substrate 1. This is a double-sided wiring board in which a second wiring (second conductor pattern) 2B is provided on a back surface (hereinafter, referred to as a second main surface) 1B of the first main surface 1A.
[0039]
As shown in FIG. 3, the first wiring 2A and the second wiring 2B pass through the first wiring 2A and the insulating substrate 1 to reach the second wiring 2B (hereinafter, referred to as blind). These are electrically connected by wiring connection conductors (hereinafter, referred to as blind vias) provided in the BVH. At this time, as shown in FIG. 3, the blind via includes a first plating 3A provided on the bottom surface of the blind via hole BVH, that is, on the second wiring 2B, and on the first plating 3A and the first plating 3A. The second plating 3B is provided on the wiring 2A. The first plating 3A and the second plating 3B are made of, for example, electrolytic copper plating.
[0040]
As shown in FIG. 3, functional plating 4 is provided on the surfaces of the first wiring 2A (second plating 3B) and the second wiring 2B. The functional plating 4 is, for example, plating having a function as a bonding material when mounting a semiconductor chip, and includes gold plating, tin plating, tin-silver alloy plating, or the like.
[0041]
The wiring board of the present embodiment is, for example, a wiring board used as an interposer of a semiconductor device such as an LGA (Land Grid Array), and is generally a tape-shaped insulating substrate that is long in one direction such as a polyimide tape. 1, an area AR2 used as a wiring board as shown in FIG. 1 is repeatedly provided.
[0042]
4 and 5 are schematic views for explaining a method of manufacturing a wiring board according to the present embodiment. FIG. 4A is a cross-sectional view of a step of forming a blind via hole, and FIG. FIG. 4C is a sectional view of a step of forming a second plating, and FIG. 5 is a sectional view of a step of forming a first wiring and a second wiring. 4A, 4B, and 4C, reference numeral 2A 'denotes a first conductive film, and 2B' denotes a second conductive film.
[0043]
Hereinafter, the method for manufacturing the wiring board of the present embodiment will be described with reference to FIGS.
[0044]
First, as shown in FIG. 4A, a first conductive film 2A 'is bonded to a first main surface 1A of an insulating substrate 1, and a second conductive film 2B is bonded to a second main surface 1B of the insulating substrate 1. At the same time, an opening (blind via hole) BVH that penetrates through the first conductive film 2A ′ and the insulating substrate 1 and reaches the second conductive film 2B ′ is formed.
[0045]
At this time, for example, after the first conductive film 2A ′ and the second conductive film 2B ′ are bonded to the insulating substrate 1, the blind via hole BVH is formed by a laser such as a carbon dioxide laser from above the first conductive film 2A ′. It is formed by irradiating light. Further, for example, after bonding the first conductive film 2A ′ to the insulating substrate 1 and making a through hole by punching using a die (cutting die), the first conductive film 2A ′ is formed on the second main surface 1B of the insulating substrate 1. The second conductor film 2B 'may be bonded so as to cover one opening end of the through hole.
[0046]
Next, as shown in FIG. 4B, a first plating 3A is formed in the blind via hole BVH. The first plating 3A is formed, for example, by electrolytic copper plating using the second conductor film 2B ′ as an electrode (cathode).
[0047]
At this time, since the second conductor film 2B 'is used as an electrode, plating does not grow on the first conductor film 2A', so that the first plating 3A can be formed with a large current density. For example, a current density of 20 A / dm 2 Degree.
[0048]
Also, at this time, if the first plating 3A grows and comes into contact with the first conductive film 2A ', the first conductive film 2A' also becomes an electrode, and the first conductive film 2A 'becomes unstable in current density. Plating is formed on the film 2A ', and the flatness of the first conductor film 2A' is deteriorated. Therefore, the first plating 3A is preferably formed to be thinner than the thickness T1 of the insulating substrate 1, for example, the depth of the blind via hole BVH, that is, the depth of the insulating substrate 1 and the first conductor film 2A '. The thickness should be about one third to one half of the sum of the thicknesses.
[0049]
From the above, for example, assuming that the opening diameter of the blind via hole BVH is 60 μm and the depth, in other words, the sum of the thicknesses of the insulating substrate 1 and the first conductive film 2A ′ is 50 μm, The first plating 3A preferably has a thickness of about 35 μm, and has a current density of 20 A / dm. 2 In this case, the first plating 3A can be formed in about 8 minutes.
[0050]
Next, as shown in FIG. 4C, a second plating 3B is formed on the first plating 3A in the blind via hole BVH and on the first conductor film 2A ′. The second plating 3B is formed by electrolytic copper plating similarly to the first plating 3A, but in order to improve the flatness of the plating formed on the first conductive film 2A ′, the current density is: For example, 2A / dm 2 About to do.
[0051]
At this time, since the first plating 3A has already been formed in the blind via hole BVH, a thickness of the second plating 3B on the first plating 3A of about 5 μm is sufficient. As shown in (c), even when the blind via hole BVH is completely formed, it can be formed in about 12 minutes.
[0052]
At this time, since the time required for forming the second plating 3B is short, it is possible to prevent the plating (second plating 3B) formed on the first conductive film 2A 'from becoming thick. Therefore, a difference between the sum T2 of the thickness of the first conductive film 2A 'and the thickness of the second plating 3B on the first conductive film 2A' and the thickness T3 of the second conductive film 2B 'can be reduced. .
[0053]
When the method for manufacturing a wiring board according to the present embodiment is used, the step of forming the wiring connection conductor (blind via) includes the step of forming the first plating 3A and the step of forming the second plating 3B. For example, steps such as a cleaning step are required, and the first plating 3A and the second plating 3B can be formed in about 25 to 30 minutes including the time taken in those steps. On the other hand, when the wiring connection conductor (via) 3 is formed in a state where the current density is low from the beginning as in the conventional method for manufacturing a wiring board, the blind via hole BVH has an opening diameter of 60 μm and a depth of 50 μm. In order to make the thickness of the wiring connection conductor 3 in the blind via hole BVH about 15 μm, it takes about 40 minutes only in the step of performing the electrolytic copper plating, and 50 minutes to 1 hour including the cleaning step. Take it. That is, by applying the method for manufacturing a wiring board of the present embodiment, the time used for forming the wiring connection conductor in the blind via hole BVH is reduced to about half, and the time required for manufacturing the wiring board is reduced. be able to.
[0054]
Next, as shown in FIG. 5, unnecessary portions of the first conductive film 2A ′ and the second plating 3B on the first conductive film 2A ′ are removed to form a first wiring 2A, and the second wiring 2A is formed. Unnecessary portions of the conductor film 2B 'are removed to form the second wiring 2B. At this time, the first wiring 2A is formed by removing unnecessary portions by etching. However, since the second plating 3B on the first conductor film 201 is thin, it is easy to miniaturize the first wiring 2A. Become.
[0055]
Thereafter, when the functional plating 4 is formed on the surface of the first wiring 2A and the surface of the second wiring 2B, a wiring board as shown in FIG. 3 is obtained. The functional plating 4 is formed by, for example, gold plating, tin plating, tin-silver alloy plating or the like based on gold plating or nickel plating.
[0056]
FIG. 6 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor device using the wiring board of the present embodiment. In FIG. 6, 5 is a semiconductor chip, 501 is an external electrode of the semiconductor chip, 6 is a connection conductor (bump), and 7 is an insulator.
[0057]
The wiring board of the present embodiment is used, for example, as an interposer of an LGA type semiconductor device. As shown in FIG. 6, a semiconductor chip 5 is provided on the surface of the wiring board on which the first wiring 2A is provided. One wiring 2A is electrically connected to the external electrode 501 of the semiconductor chip 5 by a connection conductor (bump) 6. An insulator 7 is provided between the wiring board and the semiconductor chip 5 to seal a connection between the first wiring 2A and the external electrode 501 of the semiconductor chip 5. At this time, the second wiring 2B is used as an external connection terminal (land) connected to a wiring (terminal) provided on a mounting board or the like for forming an electronic device (electronic module).
[0058]
As described above, according to the method of manufacturing a wiring board of the present embodiment, after forming the first plating 3A in a state where the current density is high, the current density is reduced and the second plating 3B is formed thin. This makes it possible to form the wiring board in a shorter time than in the conventional case where the wiring connection conductor (blind via) 3 is formed with a low current density from the beginning. Therefore, the productivity of the wiring board is improved, and the manufacturing cost of the wiring board can be reduced.
[0059]
In addition, the first plating 3A having a thickness smaller than the thickness T1 of the insulating substrate and about 1/3 to 1/2 of the depth of the blind via hole BVH is provided in the blind via hole BVH. By forming, even if the second plating 3B on the first plating 3A is thin, the connection reliability between the first wiring 2A and the second wiring 2B can be ensured. Further, when the second plating 3B on the first plating 3A is thin, the plating on the first wiring 2A (the first conductor film 2A ') can be made thin, so that the first wiring 2A can be miniaturized. Easy. That is, according to the method of manufacturing the wiring board of the present embodiment, the connection reliability between the first wiring 2A and the second wiring 2B can be improved, and the miniaturization of the first wiring 2A can be facilitated. .
In addition, in the conventional via filling method, it is necessary to form a conductive film such as an electroless copper plating film or a palladium-based catalyst on the inner wall of the BVH, which requires a complicated pretreatment step. Accordingly, it is necessary to form a conductive film, so that the pretreatment step can be greatly simplified.
[0060]
7 and 8 are schematic diagrams for explaining an application example of the wiring board of the embodiment, FIG. 7 is a cross-sectional view showing a schematic configuration of a semiconductor device using the wiring board, and FIG. It is an expanded sectional view of a board.
[0061]
Like the wiring board described in the embodiment, the first wiring 2A is provided on the first main surface 1A of the insulating substrate 1, and the second wiring 2B is provided on the second main surface 1B of the insulating substrate 1. As shown in FIG. 6, the double-sided wiring board is often used for an LGA type semiconductor device using the second wiring 2B as an external connection terminal. However, the wiring board described in the above embodiment is not limited to the LGA type semiconductor device, and can be used as an interposer of a semiconductor device such as a BGA (Ball Grid Array) and a CSP (Chip Size / Scale Package). When used as an interposer of the BGA type semiconductor device, as shown in FIG. 7, a ball-shaped external connection terminal 8 such as a tin-lead alloy (solder) may be provided on the second wiring 2B. .
[0062]
At this time, as shown in FIG. 8, on the side of the second main surface 1B of the insulating substrate 1, the area other than the area where the external connection terminals 8 are formed is protected by a solder protection film (solder resist) or the like. A membrane 9 is provided.
[0063]
As described above, the present invention has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. is there.
[0064]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0065]
(1) To improve the productivity of a wiring board in which a first wiring provided on a first main surface of an insulating substrate and a second wiring provided on a second main surface of the insulating substrate are connected by blind vias. Can be.
[0066]
(2) In the wiring board in which the first wiring provided on the first main surface of the insulating substrate and the second wiring provided on the second main surface of the insulating substrate are connected by blind vias, the connectivity of the blind vias And miniaturization of the wiring can be facilitated.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a schematic configuration of a wiring board according to one embodiment of the present invention.
FIG. 2 is a schematic diagram illustrating a schematic configuration of a wiring board according to the present embodiment, and is an enlarged plan view of a region AR1 in FIG. 1;
FIG. 3 is a schematic diagram showing a schematic configuration of a wiring board of the present embodiment, and is a cross-sectional view taken along line AA ′ of FIG.
4A and 4B are schematic views for explaining a method of manufacturing a wiring board according to the present embodiment. FIG. 4A is a cross-sectional view of a step of forming a blind via hole, and FIG. FIG. 4C is a cross-sectional view of a step of forming the second plating.
FIG. 5 is a schematic view for explaining the method of manufacturing the wiring board of the present embodiment, and is a cross-sectional view of a step of forming a first wiring and a second wiring.
FIG. 6 is a schematic sectional view showing a schematic configuration of a semiconductor device using the wiring board of the present embodiment.
FIG. 7 is a schematic diagram for explaining an application example of the wiring board of the embodiment, and is a cross-sectional view illustrating a schematic configuration of a semiconductor device using the wiring board.
FIG. 8 is a schematic diagram for explaining an application example of the wiring board of the embodiment, and is an enlarged sectional view of the wiring board.
FIG. 9 is a schematic plan view showing a schematic configuration of a conventional wiring board.
FIG. 10 is a schematic diagram showing a schematic configuration of a wiring board used in a conventional semiconductor device, and is an enlarged plan view of a region AR3 in FIG.
11 is a schematic diagram showing a schematic configuration of a wiring board used in a conventional semiconductor device, and is a cross-sectional view taken along line BB ′ of FIG.
12A and 12B are schematic views for explaining a conventional method for manufacturing a wiring board, in which FIG. 12A is a cross-sectional view of a step of forming a blind via hole, and FIG. 12B is a wiring connection conductor (blind via). FIG. 12C is a cross-sectional view of a step of forming a first wiring and a second wiring.
FIG. 13 is a schematic sectional view showing a schematic configuration of a conventional semiconductor device.
FIG. 14 is a schematic cross-sectional view for explaining a problem of a conventional wiring board.
[Explanation of symbols]
1 insulating substrate
1A First principal surface of insulating substrate
1B Second principal surface of insulating substrate
2 First wiring
2A First wiring
2A 'First conductor film
2B Second wiring
2B 'Second conductor film
3 wiring connection conductor (blind via)
3A First plating
3B 2nd plating
4 Functional plating
5 Semiconductor chip
501 External electrode of semiconductor chip
6. Connection conductor (bump)
7 Insulator
8 External connection terminal
9 Protective film
BVH blind beer hall

Claims (3)

絶縁基板の第１主面に第１導体膜を接着し、前記絶縁基板の第１主面の裏面（第２主面）に第２導体膜を接着するとともに、前記第１導体膜及び前記絶縁基板を貫通して前記第２導体膜に達する開口部（以下、ブラインドビアホールと称する）を形成するブラインドビアホール形成工程と、前記ブラインドビアホール内および前記第１導体膜の表面に配線接続導体を形成して前記第１導体膜と前記第２導体膜を電気的に接続する配線接続導体形成工程と、前記第１導体膜及び前記配線接続導体の不要な部分を除去して第１配線を形成し、前記第２導体膜の不要な部分を除去して第２配線を形成する配線形成工程とを備える配線板の製造方法であって、
前記配線接続導体形成工程は、
前記第２導体膜を電極（陰極）とした電気めっきにより、前記ブラインドビアホール内に、前記絶縁基板の厚さよりも薄い第１めっきを形成する第１めっき形成工程と、
前記第１導体膜、あるいは前記第１導体膜及び前記第２導体膜を電極（陰極）とした電気めっきにより、前記第１導体膜及び前記第１めっき上に第２めっきを形成する第２めっき形成工程とを備え、
前記第１めっき形成工程は、電気めっきの電流密度を、前記第２めっき形成工程の電気めっきの電流密度よりも高くして行うことを特徴とする配線板の製造方法。A first conductive film is bonded to a first main surface of an insulating substrate, a second conductive film is bonded to a back surface (second main surface) of the first main surface of the insulating substrate, and the first conductive film and the insulating film are bonded to each other. A blind via hole forming step of forming an opening (hereinafter, referred to as a blind via hole) penetrating a substrate and reaching the second conductive film; and forming a wiring connection conductor in the blind via hole and on the surface of the first conductive film. Forming a wiring connection conductor for electrically connecting the first conductor film and the second conductor film by removing unnecessary portions of the first conductor film and the wiring connection conductor to form a first wiring; Forming a second wiring by removing an unnecessary portion of the second conductor film, a wiring forming method comprising:
The wiring connection conductor forming step,
A first plating forming step of forming a first plating thinner than the thickness of the insulating substrate in the blind via hole by electroplating using the second conductor film as an electrode (cathode);
A second plating for forming a second plating on the first conductor film and the first plating by electroplating using the first conductor film or the first conductor film and the second conductor film as electrodes (cathodes); Forming step,
The method for manufacturing a wiring board, wherein the first plating forming step is performed by setting a current density of the electroplating higher than a current density of the electroplating of the second plating forming step. 絶縁基板の第１主面に第１配線が設けられ、前記絶縁基板の第１主面の裏面（第２主面）に第２配線が設けられており、前記第１配線と前記第２配線とは、前記第１配線及び前記絶縁基板を貫通して前記第２配線に達する開口部（以下、ブラインドビアホールと称する）に設けられた配線接続導体により電気的に接続されている配線板であって、
前記配線接続導体は、前記ブラインドビアホールを通して前記絶縁基板の第１主面に露出する前記第２配線の上に設けられ、且つ前記絶縁基板の厚さよりも薄い第１めっきと、前記第１めっき上に設けられた第２めっきからなることを特徴とする配線板。A first wiring is provided on a first main surface of the insulating substrate, and a second wiring is provided on a back surface (second main surface) of the first main surface of the insulating substrate, and the first wiring and the second wiring are provided. Is a wiring board that is electrically connected to a wiring connection conductor provided in an opening (hereinafter, referred to as a blind via hole) penetrating the first wiring and the insulating substrate and reaching the second wiring. hand,
The wiring connection conductor is provided on the second wiring exposed on the first main surface of the insulating substrate through the blind via hole, and the first plating is thinner than the thickness of the insulating substrate; A wiring board comprising the second plating provided on the wiring board. 絶縁基板の第１主面に第１配線が設けられ、前記絶縁基板の第１主面の裏面（第２主面）に第２配線が設けられており、前記第１配線と前記第２配線とは、前記第１配線及び前記絶縁基板を貫通して前記第２配線に達する開口部（以下、ブラインドビアホールと称する）に設けられた配線接続導体により電気的に接続されている配線板と、前記配線板上に設けられた半導体チップとを有し、前記配線板の第１配線もしくは第２配線と前記半導体チップの外部電極とが電気的に接続された半導体装置であって、
前記配線接続導体は、前記ブラインドビアホールを通して前記絶縁基板の第１主面に露出する前記第２配線の上に設けられ、且つ前記絶縁基板の厚さよりも薄い第１めっきと、前記第１めっき上に設けられた第２めっきからなることを特徴とする半導体装置。A first wiring is provided on a first main surface of the insulating substrate, and a second wiring is provided on a back surface (second main surface) of the first main surface of the insulating substrate, and the first wiring and the second wiring are provided. Means a wiring board electrically connected by a wiring connection conductor provided in an opening (hereinafter, referred to as a blind via hole) reaching the second wiring through the first wiring and the insulating substrate; A semiconductor device comprising: a semiconductor chip provided on the wiring board, wherein a first wiring or a second wiring of the wiring board and an external electrode of the semiconductor chip are electrically connected,
The wiring connection conductor is provided on the second wiring exposed on the first main surface of the insulating substrate through the blind via hole, and the first plating is thinner than the thickness of the insulating substrate; A semiconductor device comprising a second plating provided on a semiconductor device.
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JP2006114787A (en) * 2004-10-15 2006-04-27 Sumitomo Bakelite Co Ltd Manufacturing method of circuit board
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