JP2005217052A - Wiring board and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the etching time needs to be shortened in the semi-additive method, capable of processing the width of a wiring conductor or a gap between wiring conductors to be ≤20 μm, because the complete removal of a layer formed by electroless deposition on the grained bottom floor in an insulating resin is a time-consuming process wherein wiring conductor delamination occurs due to selective etching of the layer formed by electroless deposition for wiring conductor formation. <P>SOLUTION: The wiring board 17 comprises an insulating layer 9 which at least contains a resin, wiring conductors 15 formed on the main surfaces of the insulating layer 9, and a via 13 penetrating through the insulating layer 9 for connecting the wiring conductors 15 separated from each other by the insulating layer 9. The ridgeline of the insulating layer 9 in the vertical cross sectional view of the wiring board 17 consists of discontinuous linear sections 9a and irregular sections 9b. In each unit length of the main surface of the insulating layer 9, the total length of the linear sections 9a accounts for 20-70%. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention provides an insulating layer containing at least a resin, a wiring conductor formed on a main surface of the insulating layer, and a via that penetrates the insulating layer and connects the wiring conductor separated by the insulating layer It is related with the wiring board which comprises these.

  In general, current electronic devices are required to be small, thin, lightweight, high performance, high functionality, high quality, and high reliability, as represented by mobile communication devices. Electronic devices to be used are also required to be small and high density. Therefore, the wiring board constituting the electronic device is also required to be small, thin, and multi-terminal, and in order to realize it, the width of the wiring conductor such as the signal conductor is narrowed and the interval is narrowed. High-density wiring is achieved by increasing the number of wiring conductors.

  There are subtractive methods, semi-additive methods, and full-active methods as methods for forming such wiring conductors, but the subtractive method is difficult to form fine wiring conductors. Since the wiring conductor is formed only by the plating layer, there is a problem that it takes a long time to form the wiring conductor. Therefore, a semi-additive method is generally used as a method for forming the wiring conductor.

  The semi-additive method in the build-up board is a process of laminating an insulating resin on a printed wiring board and then curing, and a process of immersing the surface of the insulating resin in a roughening solution such as a permanganate aqueous solution for a predetermined time and roughening. A step of attaching a palladium catalyst for electroless copper plating to the upper surface, a step of depositing an electroless plating layer on the upper surface of the insulating resin to which the palladium catalyst is attached, and a plating resist layer on the upper surface of the electroless plating layer. After laminating or coating the film, this film is exposed and developed to form an opening in the pattern shape of the wiring conductor for depositing the electrolytic plating layer on the upper surface of the electroless plating layer in the plating resist layer A step of depositing an electrolytic plating layer of about 10 to 30 μm on the upper surface of the electroless plating layer in the opening, and a step from the upper surface of the electroless plating layer. A wiring conductor by sequentially performing a step of stripping the resist layer and a step of removing the electroless plating layer and the palladium catalyst exposed by stripping the plating resist layer using an etching solution of sulfuric acid or chlorine based aqueous solution. It is a method of forming. In this method, when the electroless plating layer and the palladium catalyst are removed, the upper surface and the side surface of the electrolytic plating layer are simultaneously etched.

  Despite the fact that the width of wiring conductors and the spacing between wiring conductors have become narrower than 20 μm in recent wiring boards, the roughened surface of the insulating resin surface is deep, so the entire roughened surface of the insulating resin surface In order to form a sufficient electroless plating layer with good throwing power, the thickness of the electroless plating layer was required to be 1 μm or more, and the thickness variation was large. However, since it takes a longer etching time to completely remove the thickness of the electroless plating layer formed at a deeply roughened position, among the electroless plating layer and the electrolytic plating layer constituting the wiring conductor, The electroless plating layer is selectively etched, and in the electroless plating layer etching process and the cleaning process, the etching solution or the cleaning liquid enters the stepped portion generated by the selective etching of the electroless plating layer, and the wiring conductor When the wire is lifted, the wiring conductor is peeled off, resulting in a disconnection.

  On the other hand, when etching is insufficient, the electroless plating layer or palladium catalyst formed in the deep surface of the roughened surface cannot be completely removed, and the direction of the wiring conductor adjacent to the electroless plating layer As a result, there is a problem that an electric short circuit occurs between adjacent wiring conductors.

As a countermeasure for such a problem, when removing the electroless plating layer and the palladium catalyst using an etching solution of sulfuric acid or chlorine aqueous solution, the electroless plating layer and the electroless plating layer constituting the wiring conductor are electroless. Etching is stopped before the plating layer is selectively etched, and the electroless plating layer residue and the palladium catalyst remaining between the wiring conductors are removed with chromic acid (see Patent Document 1), A proposal has been made to remove the residue of the electroless plating layer remaining between the wiring conductors and the palladium catalyst by removing part of the surface layer portion (see Patent Document 2).
JP 2000-294926 A JP 2000-208936 A

  However, in the method of removing the electroless plating layer residue and the palladium catalyst remaining between the wiring conductors of Patent Document 1, it is difficult to control the etching amount of the electroless plating layer and the palladium catalyst, The problem is that an acid residue remains. Further, in the method of removing a part of the surface layer of the insulating substrate of Patent Document 2 and simultaneously removing the electroless plating layer remaining between the wiring conductors and the palladium catalyst, interlayer insulation due to the thinning of the insulating substrate. There has been a problem that the reliability is reduced and a part of the insulating substrate under the wiring conductor is removed, and the wiring conductor is peeled off. If the etching time of the wiring conductor is adjusted so that the wiring conductor does not peel off, residues cannot be completely removed between the wiring conductors, resulting in a problem that the insulation resistance value after long-term use decreases.

  The present invention has been completed in view of the problems of the prior art, and provides a wiring board that maintains electrical insulation between wiring conductors and is excellent in bonding reliability between the wiring conductor and the insulating board. With the goal.

  The wiring board of the present invention includes an insulating layer containing at least a resin, a wiring conductor formed on a main surface of the insulating layer, and a wiring conductor penetrating the insulating layer and separated by the insulating layer. A wiring board comprising vias to be connected, wherein a ridge line of the insulating layer at a cut surface when the wiring board is cut vertically is constituted by a discontinuous straight line portion and an uneven portion; The sum of the lengths of the straight portions per unit length of the surface is 20 to 70%.

  In the wiring board of the present invention, it is desirable that the maximum depth of the recess formed in the main surface of the insulating layer is 3 μm or less.

  In the wiring board of the present invention, the ratio of the roughened surface area of the insulating layer to the fixed simple area on the main surface of the insulating layer is preferably 1.1 to 2.50.

  In the wiring board of the present invention, the insulating layer is preferably made of at least a resin and an inorganic filler or a resin filler.

  In the wiring board of the present invention, an electroless plating layer and an electrolytic plating layer are sequentially formed on the main surface of the insulating layer to form a wiring conductor, and the thickness of the electroless plating layer is 0. It is desirable that the thickness is 1 to 2 μm, and the thickness of the electrolytic plating layer is 5 to 30 μm.

  Moreover, as for the wiring board of this invention, it is desirable for the surface roughness of an electroplating layer to be Ra = 0.4 micrometer or less.

  Further, the method for manufacturing a wiring board according to the present invention includes a pressing step of flattening the insulating layer main surface by bringing a press plate into contact with at least one main surface of the insulating layer containing at least a resin and applying heat and pressure. And a roughening step of forming a discontinuous straight line portion and a concavo-convex portion on the planarized main surface of the insulating layer.

  In the method for manufacturing a wiring board according to the present invention, it is desirable that the main surface of the insulating layer is roughened using a roughening solution in the roughening step.

  In the method for manufacturing a wiring board according to the present invention, a through hole forming step for forming a through hole in the insulating layer is provided between the pressing step and the roughening step, and the through hole is penetrated by a plating method after the roughening step. It is desirable to include a conductor forming step of forming a conductor and forming a wiring conductor on the main surface of the insulating layer.

  In the method for manufacturing a wiring board of the present invention, it is desirable to sequentially form an electroless plating layer and an electrolytic plating layer on the main surface of the insulating layer in the conductor forming step.

  By using such a wiring board and its manufacturing method, the time required for removing the electroless plating layer can be shortened, so that the peeling of the wiring conductor due to selective etching of the electroless plating layer can be prevented. In addition, since there is no residue between the wiring conductors, it is possible to prevent a decrease in insulation reliability.

  In the present invention, when the wiring board is cut vertically, the ridge line of the insulating layer at the cut surface is constituted by a discontinuous linear portion and an uneven portion, and the main surface of the insulating layer Since the sum of the lengths of the straight portions per unit length is set to 20 to 70%, the electroless plating layer is formed well around the starting point of the straight portions good per electroless plating solution. Therefore, the electroless plating layer can be sufficiently formed even in the deepest portion of the roughened dent of the insulating resin even with the thin electroless plating layer. And since the electroless-plating layer thickness can be made thinner than before, the formation time of an electroless-plating layer can be shortened and the etching time at the time of electroless-plating layer removal can be shortened. Moreover, the thickness of the electroless plating layer inferior in chemical durability for forming the wiring conductor can be reduced, and the electroless plating layer can be selectively etched and prevented from peeling off the wiring conductor.

  In addition, by setting the maximum depth of the recess formed in the main surface of the insulating layer to 3 μm or less, the etching time of the electroless plating layer can be made more uniform, and there is no need to allow extra etching time. Etching time can be further shortened.

  Moreover, by setting the ratio of the surface area of the insulating layer to the constant simple area on the main surface of the insulating layer to 1.1 to 2.50, the shape of the dent can be obtained even when the depth of the dent formed on the main surface of the insulating layer is about 3 μm. The problem that it takes a long time to remove the electroless copper plating layer can be eliminated and the etching time can be shortened.

  In addition, the wiring board of the present invention is such that the insulating layer is formed of at least a resin and an inorganic filler or a resin filler, and when the insulating layer is roughened with a roughening liquid, the inorganic filler or the organic filler is separated. Thus, a good roughened surface can be formed. Furthermore, a stable roughened surface can be formed by appropriately adjusting the particle size and volume% of the inorganic filler or resin filler contained in the resin.

  Further, by setting the thickness of the electroless plating layer constituting the wiring conductor to 0.1 to 2 μm and the thickness of the electrolytic plating layer to 5 to 30 μm, the chemical durability is low and the electrical resistance is relatively low. By thickening the electrolytic plating layer with higher chemical durability and relatively lower electrical resistance than the high electroless plating layer, selective etching of the electroless plating layer can be suppressed, and the electrolytic plating layer Stable conduction reliability can be ensured.

  In addition, by setting the surface roughness of the electrolytic plating layer to Ra = 0.4 μm or less, transmission loss due to the skin effect can be suppressed, so that a wiring layer having excellent electrical characteristics can be formed.

  Further, in the method for manufacturing a wiring board according to the present invention, a press plate is brought into contact with at least one main surface of the insulating layer and heated and pressed to flatten the insulating layer main surface, and the flattened insulation. Etching is performed on parallel parts substantially parallel to the main surface of the insulating layer without lowering the adhesion between the insulating layers by providing a roughening step for forming a discontinuous linear part and uneven part on the main surface of the layer. Since the liquid per area is improved, the thickness of the electroless plating layer can be reduced, the formation time of the electroless plating layer can be shortened, and the etching time of the electroless plating layer can be shortened. it can.

  Also, by roughening the main surface of the insulating layer using a roughening solution in the roughening step, when the inorganic filler or organic filler is contained in the insulating layer, the inorganic filler or organic filler is efficiently degrained. It is possible to increase the adhesion between the main surface of the insulating layer and the wiring conductor and between the insulating layers.

  Also, a through hole forming step for forming a through hole in the insulating layer is provided between the pressing step and the roughening step, a through conductor is formed in the through hole by a plating method after the roughening step, and wiring is provided on the main surface of the insulating layer. By providing the conductor forming step for forming the conductor, the inner wall of the through hole can be roughened, and the adhesion between the through conductor and the inner wall of the through hole can be increased.

  In addition, since the electroless plating layer and the electrolytic plating layer were sequentially formed on the main surface of the insulating layer in the conductor formation process, the conductor was not formed only with the electroless plating layer with a slow plating layer formation rate, and most of the conductor was plated. Conductor processing time can be shortened because the electroplating layer can be formed with a high layer formation rate.

  As shown in FIG. 1A, for example, the wiring board of the present invention includes a core substrate 1 containing glass cloth and a resin, a through hole 3 formed through the core substrate 1, and a through-hole. A through-hole conductor 5 formed in the hole 3, a core wiring layer 7 formed on both surfaces of the core substrate 1, an insulating layer 9 formed on the main surface of the core substrate 1, and the insulating layer 9 are penetrated. The formed through hole 11, the via conductor 13 formed in the through hole 11, and the wiring conductor 15 formed on the main surface of the insulating layer 9 are configured.

  In such a wiring substrate, the core substrate 1 and the insulating layer 9 are composed of the core wiring layer 7 and the wiring conductor 15 arranged so as to sandwich each of the core substrate 1 and the insulating layer 9, and the through-hole conductor 5 and the via conductor provided so as to penetrate each of them. 13 and has a function of electrically insulating.

  The core wiring layer 7, the wiring conductor 15, the through-hole conductor 5, and the via conductor 13 are arbitrarily connected to each other to form a wiring circuit.

  In the example of FIG. 1A, the wiring substrate 17 is formed of a core substrate 1 having a plate-like core body and an insulating layer 9 deposited on the surface. The core body of the core substrate 1 has a function of preventing the wiring substrate 17 from warping, has a thickness of about 0.3 to 1.5 mm, and an epoxy resin or bismaleimide triazine on a glass cloth in which glass fibers are woven vertically and horizontally. The insulating layer 9 is impregnated with a thermosetting resin such as a resin, has a function as a support for the wiring conductor 15, has a thickness of 10 to 80 μm, and is made of an epoxy resin or a modified polyphenylene ether resin. It consists of a thermosetting resin.

  A wiring conductor 15 is formed on the surface of the insulating layer 9. As shown in FIG. 1B, the wiring conductor 15 is formed by plating, and has an electroless plating thickness of 2 μm or less and 0.1 μm or more, optimally a thickness of 1 μm or less and 0.1 μm or more. It is desirable to form the layer 15a and the electrolytic plating layer 15b having a thickness of 5 μm or more, and optimally 15 μm or more. The wiring conductor 15 has a function as a conductive path that electrically connects each electrode of an electronic component such as a semiconductor element mounted on the wiring board 17 to an external electric circuit (not shown).

  In the wiring board 17 of the present invention, the ridge line formed by the cross section of the insulating layer 9 and the main surface of the insulating layer 9 is composed of the non-continuous linear portion 9a and the uneven portion 9b. It is important that the sum of the lengths of the straight portions 9a per unit length is 20 to 70%.

  According to the wiring board 17 of the present invention, since the insulating layer 9 has the above-described configuration, the electroless plating layer 15a is well-rounded starting from the straight portion 9a of the insulating layer 9 that is good per solution of the electroless plating solution. Therefore, even if the electroless plating layer 15a is formed relatively thin, the electroless plating layer 15a is sufficiently formed even in the deepest portion of the uneven portion 9b. Therefore, the thickness of the electroless plating layer 15a can be made thinner than before, so that the proportion of the electrolytic plating layer 15b having a low electric resistance in the wiring conductor 15 is increased, and the low-resistance wiring conductor 15 can be formed. Further, since the thickness of the electroless plating layer 15a inferior in chemical durability is reduced, the reliability of the wiring board 17 can be improved. Further, in the manufacturing process, since the thickness of the electroless plating layer 15a having a lower formation speed than the electrolytic plating layer 15b can be reduced, the formation time of the wiring conductor 15 can be shortened, and the electroless plating layer 15a. The etching time can be shortened also at the time of removal.

  In the wiring board 17 of the present invention, as described above, the straight portion 9a and the uneven portion 9b of the main surface of the insulating layer 9 are formed on the ridgeline formed by the cross section of the insulating layer 9 and the main surface of the insulating layer 9. Although it is important that the sum of the lengths of the straight portions 9a per unit length of the main surface of the insulating layer 9 is 20 to 70%, a method for manufacturing the wiring board 17 having such a structure is conventionally known. This will be explained in comparison with the construction method.

  In the conventional method, as shown in FIG. 6A, an insulating layer 29 is formed by laminating a B-stage insulating resin on a plate-like core substrate 21 and then curing.

  Next, as shown in FIG. 6B, through holes 33 are formed in the insulating layer 29 by a carbon dioxide laser or a YAG laser.

  Next, as shown in FIG. 6C, the surface of the insulating layer 29 is roughened with an aqueous solution of a permanganate solution, and an electroless plating layer and an electrolytic plating layer are sequentially formed on the main surface of the insulating layer 29. .

  In such a conventional manufacturing method, only the non-parallel portion 29 b that is non-parallel to the main surface of the insulating layer 29 is formed on the main surface of the insulating layer 29.

  On the other hand, in the present invention, as shown in FIG. 2A, after laminating a sheet of glass cloth in which glass cloth fibers are woven vertically and horizontally, impregnated with a thermosetting resin such as epoxy resin or bismaleidotriazine resin. Insulation having a thickness of 20 to 60 μm made of thermosetting properties such as a B-stage epoxy resin or a modified polyphenylene ether resin on a plate-like core substrate 1 having a thickness of 0.3 to 1.5 mm produced by thermosetting After laminating the resin, as shown in FIG. 2 (b), pressing is performed under the conditions of 50 to 170 ° C., 10 to 180 seconds, and 0.3 to 1 MPa using a mold 35 having a flat main surface. Do and cure. At this time, the main surface of the insulating layer 9 on the side in contact with the mold 35 is a rough surface in the conventional manufacturing method, but according to the manufacturing method of the present invention, a pressurizing step by a press is provided. As a result, the main surface of the insulating layer 9 is flattened, and when the insulating substrate is cut vertically, the straight portion 9a and the concavo-convex portion 9b can be formed on the ridgeline of the insulating layer on the cut surface.

  Further, as shown in FIG. 2 (c), through holes 13 are formed in the insulating layer 9 by a carbon dioxide laser or YAG laser, and the surface of the insulating layer 9 is heated to 40 to 60 ° C. as shown in FIG. 3 (d). By immersing in a roughening solution such as an aqueous solution of permanganate for 5 to 15 minutes and roughening so that the roughening recess on the surface has a maximum depth of 3 μm or less, the main surface of the insulating layer 9 is A straight line portion 9a and an uneven portion 9b are formed.

  Next, a palladium catalyst is formed on the surface of the insulating layer 9 by being immersed in an aqueous solution of a palladium catalyst for electroless plating at 20 to 40 ° C. for 1 to 10 minutes. In addition, since it is complicated, the palladium catalyst A is not illustrated.

  Next, as shown in FIG. 3 (e), the laminated body of the core substrate 1 and the insulating layer 9 on which the palladium catalyst is formed is 55 to 65 ° C. made of copper sulfate, rossel salt, formalin, EDTA sodium salt, stabilizer, and the like. Is immersed in the electroless plating solution for about 10 to 30 minutes to deposit an electroless plating layer 15a of about 0.3 to 1.0 μm on the surface of the insulating layer 9, and then as shown in FIG. The plating resist layer 16 is formed on the electroless plating layer 15a. The plating resist layer 16 has a thickness of 15 to 50 μm. For example, the material is made of a photosensitive resin, and is deposited by laminating.

  Thereafter, as shown in FIG. 4G, an opening 18 is formed by exposure and development.

Thereafter, as shown in FIG. 4 (h), while applying an electric current of 3 to 5 A / dm ² to the electrolytic copper plating solution composed of sulfuric acid, copper sulfate pentahydrate, chlorine, brightener, etc., for 1 to 3 hours. The electrolytic plating layer 15b is formed in the opening 18 by dipping.

  Thereafter, as shown in FIG. 5 (i), the plating resist layer 16 was removed with a sodium hydroxide aqueous solution at 45 to 50 ° C., and the plating resist layer 16 was peeled off as shown in FIG. 5 (j). The electroless plating layer 15a exposed by etching is removed by etching with a sulfuric acid aqueous solution such as sulfuric acid / hydrogen peroxide solution or copper sulfate at 25 to 30 ° C.

  Next, the palladium catalyst A (not shown) exposed by removing the electroless plating layer 15a is immersed in a cyanic aqueous solution such as nickel potassium cyanide or potassium cyanide aqueous solution at about 25 to 30 ° C. for about 10 to 30 minutes. Etching is removed, and the surface of the wiring conductor 15 is roughened with a roughening agent mainly composed of formic acid or the like (not shown).

  Furthermore, if necessary, the wiring board 17 of the present invention can be manufactured by providing another insulating layer 9 and another wiring conductor 15 on the main surfaces of the insulating layer 9 and the wiring conductor 15.

  In addition, the measurement of the linear part 9a where the ridgeline of an insulating layer is linear, and the uneven | corrugated | grooved part 9b is carried out with the lens of 3000 times on a monitor using the laser measuring machine of an ultra-deep shape measuring microscope (Keyence VK-8500 etc.). The surface roughness of a certain length (at least 1 mm) was measured, and the data was subjected to image processing to calculate the ratio between the straight line portion and the roughened and deepened portion. In the profile after image processing shown in FIG. 7, the straight line portion 9 a defines a portion included within a range of 0.5 μm above and below the straight line as a straight line portion 9 a when the straight line portions are connected by a straight line. The other portion is defined as the uneven portion 9b.

  When the above apparatus is not used, the same analysis may be performed by enlarging the image to 3000 times using a scanning electron microscope (SEM), taking an SEM photograph, and the like.

  In the present invention, the depth of the concavo-convex portion 9b is preferably 3 μm or less, so that it is possible to reduce the retention of the etching solution in the recess and to reduce the fluctuation of the etching time. it can.

  In addition, by setting the ratio of the surface area of the insulating layer 9 to the constant simple area on the main surface of the insulating layer 9 in the range of 1.1 to 2.50, the shape of the uneven portion 9b has a diameter inside than the opening. The problem that it takes a long time to remove the electroless copper plating layer 15a due to the large bowl shape can be eliminated, and the etching time can be shortened.

  Further, the wiring conductor 15 is formed by a plating method and has an electroless plating layer 15a having a thickness of 0.1 μm or more and 2 μm or less, optimally 0.3 μm or more and 1 μm or less, and an optimal thickness of 5 μm or more. Is preferably formed from an electroplating layer 15b of 15 μm or more. Furthermore, the surface roughness of the electrolytic plating layer 15b forming the wiring conductor 15 is preferably Ra = 0.4 μm or less, and most preferably Ra = 0.2 μm or less.

The wiring board 17 of the present invention and the manufacturing method of the wiring board 17 of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. In the above-described example, the insulating layer 9 is laminated on the upper surface of the core substrate 1 and the wiring conductor 15 is formed on the insulating layer 9. However, the insulating layer 9 is laminated on both upper and lower surfaces of the core substrate 1, and the wiring conductor is formed on both surfaces. 15 may be formed. Further, the wiring conductors 15 formed on both surfaces may be electrically connected by through conductors formed inside the insulating substrate 1. Furthermore, in the above-described example, the insulating substrate 1 is formed by laminating the insulating layer 9 on the core substrate 1, but the insulating substrate 1 may be configured by only the core substrate 1. Further, it goes without saying that the ridge line of the insulating layer can also form the straight portion 9a and the concavo-convex portion 9b on the main surface of the core substrate 1 by the same manufacturing method. Also, the manufacturing method of the wiring substrate 17 of the present invention is also described above. The present invention is not limited to an exemplary embodiment, and various modifications and improvements can be made without departing from the scope of the present invention.

  In order to evaluate the wiring board and the manufacturing method of the wiring board of the present invention, samples were prepared and the following evaluation was performed.

(Production of wiring board)
(1) Four 200 μm-thick prepregs impregnated with 50% by volume of bismaleimide triazine resin are laminated on a glass cloth in which glass fibers are woven vertically and horizontally, and bonded with a pressure of 5 MPa at 200 ° C. The core substrate was produced by heating for 2 hours to complete curing.

(2) Then, a sheet made of an epoxy resin formed by employing a conventionally known doctor blade method was laminated on the surface of the core substrate and temporarily cured, and an insulating layer was provided on the main surface of the core substrate.
(3) Subsequently, the laminated body of the core substrate and the insulating layer was heated and pressed from both sides with a hot press machine at 100 ° C. for 30 seconds and the pressure shown in Table 1, and further heated at 170 ° C. for 2 hours. The insulating substrate 1 was produced by thermosetting.

  (4) Further, after forming a through hole in the insulating layer with a carbon dioxide gas laser, the insulating substrate is immersed in a roughening solution such as a permanganate aqueous solution for a predetermined time to roughen the surface to the roughness shown in Table 1, It was immersed in an aqueous solution of a palladium catalyst for electroless copper plating at 30 ° C. for 5 minutes to adhere the palladium catalyst to the surface.

  (5) Next, the surface of the insulating substrate is immersed in an electroless copper plating solution at 60 ° C. made of copper sulfate, Rossell salt, formalin, EDTA sodium salt, stabilizer, etc., and the immersion time is adjusted as shown in Table 1. The initial electroless copper plating layer thickness shown was used.

  (6) A 15 μm width for depositing an electrolytic copper plating layer on the electroless copper plating layer by applying a photoresist which is an anti-plating resin layer, mainly composed of an acrylic resin, by exposure and development An opening for forming a conductor pattern was formed.

  (7) Furthermore, a part of the electroless copper plating layer was removed by adjusting the etching rate with a 30 ° C. aqueous sulfuric acid solution.

(8) Next, by immersing in an electrolytic copper plating solution composed of sulfuric acid, copper sulfate pentahydrate, chlorine, brightener, etc. while applying a current of 3 A / dm ² for a predetermined time, electrolytic copper is formed in the opening. The plating layer was formed with a predetermined thickness.

  (9) Thereafter, the plating-resistant resin layer is removed with sodium hydroxide, and the exposed electroless copper plating layer is removed with an aqueous sulfuric acid solution by adjusting the etching rate.

(10) Then, a solder resist layer made of an acrylic-modified epoxy resin having a thickness of 20 μm and having openings for measuring insulation resistance and conduction resistance on the surface was formed to obtain a wiring board.

From Table 1,
The ridgeline of the insulating layer at the cut surface when the wiring board that is outside the scope of the present invention is cut vertically is composed of a straight portion and an uneven portion, and the length of the straight portion per unit length of the main surface of the insulating layer Sample No. 5 is less than 20%, and the ratio of the roughened surface area of the insulating layer to the fixed simple area is larger than 2.5. 1, the insulation resistance value after standing unsaturated PCT becomes 10 ⁵ or less, without insulation between wires maintained, further roughened shape had become Takotsubogata. The sum of the lengths of the straight portions per unit length of the main surface of the insulating layer is more than 70% and 72%, and the ratio of the roughened surface area of the insulating layer to a certain simple area is smaller than 1.1. No. 5 had a poor adhesion due to delamination at the third time in the solder heat resistance 260 ° C. dipping repeated test, and did not function as a wiring board.

On the other hand, the ridgeline formed by the cross section of the insulating layer of the present invention and the main surface of the insulating layer is composed of a straight portion and an uneven portion, and the sum of the lengths of the straight portions per unit length of the main surface of the insulating layer is Sample No. 20-70%. 2 to 4, the insulation resistance is 10 ⁸ Ω or more, and it can be seen that even when the solder heat resistance 260 ° C. dipping test is repeated 10 times or more, no delamination is observed and good characteristics are exhibited.

However, the sample No. No. 2 in which the maximum depth of the recess formed in the main surface of the insulating layer is larger than 3 μm. Insulation resistance value after unsaturated PCT in 6 becomes slightly high as 10 ^6.

(A) is sectional drawing which shows the wiring board of this invention, (b) is a principal part enlarged view of the wiring board of this invention. It is process drawing explaining the manufacturing method of the wiring board of this invention. It is process drawing explaining the manufacturing method of the wiring board of this invention. It is process drawing explaining the manufacturing method of the wiring board of this invention. It is process drawing explaining the manufacturing method of the wiring board of this invention. It is process drawing explaining the manufacturing method of the conventional wiring board. It is an example of the profile which measured the ridgeline of the insulating layer of the wiring board of this invention using the ultra-deep shape measuring microscope.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 .... Insulating substrate 9 ... Insulating layer 9a ... Straight line part 9b ... Uneven part 15 ...... Wiring conductor 15a ... Electroless Plating layer 15b ... Electrolytic plating layer

Claims (10)

An insulating layer containing at least a resin; a wiring conductor formed on a main surface of the insulating layer; and a via that penetrates the insulating layer and connects the wiring conductor separated by the insulating layer. The ridge line of the insulating layer at the cut surface when the wiring substrate is cut vertically is composed of a discontinuous linear portion and an uneven portion, and the unit length per unit length of the insulating layer main surface. The wiring board, wherein the sum of the lengths of the straight portions is 20 to 70%. The wiring board according to claim 1, wherein the maximum depth of the recess formed in the main surface of the insulating layer is 3 μm or less. The wiring board according to claim 1, wherein the ratio of the roughened surface area of the insulating layer to the fixed simple area on the main surface of the insulating layer is 1.1 to 2.50. The wiring board according to claim 1, wherein the insulating layer comprises at least a resin and an inorganic filler or a resin filler. An electroless plating layer and an electroplating layer are sequentially formed on the main surface of the insulating layer to form a wiring conductor, and the electroless plating layer has a thickness of 0.1 to 2 μm. The wiring board according to claim 1, wherein the layer has a thickness of 5 to 30 μm. The wiring board according to claim 5, wherein the surface roughness of the electrolytic plating layer is Ra = 0.4 μm or less. At least one main surface of the insulating layer containing a resin is brought into contact with a press plate and heated and pressed to flatten the insulating layer main surface, and to the flattened insulating layer main surface, A method of manufacturing a wiring board, comprising: a roughening step of forming a discontinuous straight line part and an uneven part. The method for manufacturing a wiring board according to claim 7, wherein in the roughening step, the main surface of the insulating layer is roughened using a roughening solution. A through hole forming step for forming a through hole in the insulating layer is provided between the pressing step and the roughening step, a through conductor is formed in the through hole by a plating method after the roughening step, and a wiring conductor is formed on the main surface of the insulating layer. A method of manufacturing a wiring board according to claim 7, further comprising: a conductor forming step of forming a conductor. 10. The method for manufacturing a wiring board according to claim 7, wherein an electroless plating layer and an electrolytic plating layer are sequentially formed on the main surface of the insulating layer in the conductor forming step.

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