JP4328195B2 - WIRING BOARD, MANUFACTURING METHOD THEREOF, AND ELECTRIC DEVICE - Google Patents

Description

  The present invention connects an insulating layer containing at least a resin, a wiring conductor layer formed on the surface of the insulating layer, and a wiring conductor layer penetrating the insulating layer and separated by the insulating layer. The present invention relates to a wiring board having vias, a manufacturing method thereof, and an electric device.

  In general, current electronic devices are required to be small, thin, lightweight, high performance, high functionality, high quality, and high reliability, as represented by mobile communication devices. Electronic devices to be used are also required to be small and high density. Therefore, the wiring board constituting the electronic device is also required to be small, thin, and multi-terminal, and in order to realize it, the width of the wiring conductor such as the signal conductor is narrowed and the interval is narrowed. High-density wiring is achieved by increasing the number of wiring conductors.

  There are subtractive, semi-additive, and full additive methods as methods for forming such wiring conductors. However, the subtractive method is difficult to form fine wiring conductors. Since the wiring conductor is formed only by plating, there is a problem that it takes a long time to form the wiring conductor. Therefore, a semi-additive method is generally used as a method for forming the wiring conductor.

  The semi-additive method in the build-up board is a process of laminating an insulating resin on a printed wiring board and then curing, and a process of immersing the surface of the insulating resin in a roughening solution such as a permanganate aqueous solution for a predetermined time and roughening. A step of attaching a palladium catalyst for electroless copper plating to the upper surface, a step of depositing an electroless plating layer on the upper surface of the insulating resin to which the palladium catalyst is attached, and a plating resist layer on the upper surface of the electroless plating layer. After laminating or coating the film, the film is exposed and developed to form a pattern shape opening of the wiring conductor for depositing the electrolytic plating layer on the upper surface of the electroless plating layer in the plating resist layer A step of depositing an electrolytic plating layer of about 10 to 30 μm on the upper surface of the electroless plating layer in the opening, and a step from the upper surface of the electroless plating layer. A wiring conductor by sequentially performing a step of stripping the resist layer and a step of removing the electroless plating layer and the palladium catalyst exposed by stripping the plating resist layer using an etching solution of sulfuric acid or chlorine based aqueous solution. It is a method of forming. In this method, when the electroless plating layer and the palladium catalyst are removed, the upper surface and the side surface of the electrolytic plating layer are simultaneously etched.

  In recent wiring boards, although the width of the wiring conductor and the interval between the wiring conductors are narrower than 20 μm, the roughened surface of the insulating resin surface is deep, so the entire roughened surface of the insulating resin surface In addition, in order to form the electroless plating, the thickness of the electroless plating is required to be 1 μm or more, and the thickness variation is large. In addition, since the etching time takes longer to completely remove the electroless plating formed at a deeply roughened position, among the electroless plating layer and the electrolytic plating layer constituting the wiring conductor, in particular, the electroless plating The layer is selectively etched, and in the electroless plating layer etching step and the cleaning step, the etching solution or the cleaning solution enters the stepped portion generated by the selective etching of the electroless plating layer, and the wiring conductor is lifted. As a result, there is a problem that the wiring conductor is peeled off and disconnected.

  On the other hand, when etching is insufficient, the electroless plating layer or palladium catalyst formed in the deep surface of the roughened surface cannot be completely removed, and the direction of the wiring conductor adjacent to the electroless plating layer As a result, there is a problem that an electric short circuit occurs between adjacent wiring conductors.

  As a countermeasure for such a problem, when removing the electroless plating layer and the palladium catalyst using an etching solution of sulfuric acid or chlorine aqueous solution, the electroless plating layer and the electroless plating layer constituting the wiring conductor are electroless. Etching is stopped before the plating layer is selectively etched, and the electroless plating layer residue and the palladium catalyst remaining between the wiring conductors are removed with chromic acid (see Patent Document 1), A proposal has been made to remove the residue of the electroless plating layer remaining between the wiring conductors and the palladium catalyst by removing part of the surface layer portion (see Patent Document 2).

  However, in the method of removing the electroless plating layer residue and the palladium catalyst remaining between the wiring conductors of Patent Document 1, it is difficult to control the etching amount of the electroless plating layer and the palladium catalyst, The problem is that an acid residue remains. Further, in the method of removing a part of the surface layer of the insulating substrate of Patent Document 2 and simultaneously removing the electroless plating layer remaining between the wiring conductors and the palladium catalyst, interlayer insulation due to the thinning of the insulating substrate. There has been a problem that the reliability is reduced and a part of the insulating substrate under the wiring conductor is removed, and the wiring conductor is peeled off. If the etching time of the wiring conductor is adjusted so that the wiring conductor does not peel off, residues cannot be completely removed between the wiring conductors, resulting in a problem that the insulation resistance value after long-term use decreases.

  In order to solve such a problem, a technique for forming an electroless plating layer thinly and uniformly, or a technique for forming a base metal layer that is more chemically durable than the electroless plating layer is required. Yes.

  However, thinning the electroless plating layer is limited in terms of the ability to attach the insulating resin to the plating as described above, and as a method for forming a thin metal layer more uniformly, sputtering or vacuum evaporation is possible. It has been proposed to form a deposited metal layer of 0.1 μm or less on the insulating resin layer using a method such as ion plating. (See Patent Document 3).

Since the formation of the metal layer by electroless plating is affected by changes in the concentration of the processing solution and variations in the roughened state of the surface of the insulating layer, the thickness of the formed metal layer is uniformly formed with a thickness of 0.3 μm or less. It is difficult. In comparison, the formation of a metal layer by sputtering or the like is less susceptible to the influence of changes in processing conditions because of vapor deposition in vacuum, and coarse particles are not formed unlike electroless plating. Therefore, a metal layer having a thickness of 0.1 μm or less can be stably formed on the surface of the insulating resin.
JP 2000-294926 A JP 2000-208936 A Japanese Patent Laid-Open No. 11-289164

  However, if a vapor deposition metal layer is used instead of the electroless plating layer, a wiring with a width of 30 μm or less and a width of 15 μm or less can be formed relatively easily. It is difficult to completely cover the wall surface of the through-hole formed vertically with a vapor-deposited metal layer, and there is a problem in that the reliability of conduction resistance is lowered due to partial thinning of the electrolytic plating layer formed on it. It has become. On the other hand, if the sputtering time is increased in order to sufficiently thicken the deposited metal layer on the wall surface of the through hole, the deposited metal layer on the insulating layer surface becomes thicker and a longer etching time is required. Since etching becomes large, there has been a problem that the wiring conductor is peeled off and the reliability of conduction resistance is lowered.

  The present invention has been completed in view of the problems of the prior art, and provides a wiring board and an electrical device that maintain electrical insulation between wiring conductors and are excellent in bonding reliability between the wiring conductor and the insulating board. The purpose is to provide.

  The wiring board of the present invention comprises an insulating layer containing at least a resin, a wiring conductor layer formed on the surface of the insulating layer, and a wiring conductor layer that penetrates the insulating layer and is separated by the insulating layer. A via conductor layer to be connected, and the wiring conductor layer is formed by sequentially forming a deposited metal layer and an electrolytic plating layer on the main surface of the insulating layer, and the via conductor layer is formed on the insulating layer. A vapor-deposited metal layer, an electroless copper plating layer, and an electrolytic plating layer are sequentially formed in the formed through holes.

  Moreover, as for the wiring board of this invention, it is desirable for the thickness of a vapor deposition metal layer to be 0.1 micrometer or less.

  Moreover, as for the wiring board of this invention, it is desirable for the thickness of an electroless-plating layer to be 0.1-2 micrometers.

  In the wiring board of the present invention, it is desirable that the thickness of the electrolytic plating layer forming the wiring conductor layer is 5 μm or more.

  In the wiring board of the present invention, it is desirable that the surface roughness of the electrolytic plating layer is Ra = 0.4 μm or less.

  In the wiring board of the present invention, it is desirable that the maximum depth of the recess formed in the main surface of the insulating layer is 3 μm or less.

  In the wiring board of the present invention, the thickness of the insulating layer is desirably 50 μm or less.

  In the wiring board of the present invention, the insulating layer is preferably made of at least a resin and an inorganic filler or a resin filler.

  The electric device of the present invention is characterized in that an electric element is mounted on the main surface of the wiring board described above.

  The method for manufacturing a wiring board according to the present invention includes a step of forming a through hole in an insulating layer containing at least a resin, a step of forming a vapor deposition metal layer on the main surface of the insulating layer and the through hole, and the through hole only. And a step of forming an electroplating layer and a step of forming an electroplating layer on the main surface of the insulating layer and the through hole.

  In the present invention, the via conductor layer is formed by sequentially forming a vapor-deposited metal layer, an electroless plating layer, and an electrolytic plating layer in the through-hole formed in the insulating layer, so that it is difficult to form the vapor-deposited metal layer. However, the deposited metal layer and the electroless plating layer sufficiently form the base metal layer for forming the electroplating layer, so that it is possible to form the electroplating layer without a shortage and poor conduction of the via conductor. Thus, conduction reliability can be improved. In addition, in the wiring conductor layer formed on the main surface of the insulating layer, there is no electroless plating that is inferior in chemical durability compared to the vapor-deposited metal layer or the electroless plating layer. Even if various chemical treatments are performed in the manufacturing process, it is possible to suppress peeling of the wiring conductor, poor conduction, and lowering of the conduction resistance, resulting in a highly reliable wiring board.

  Moreover, the formation time of the wiring conductor layer can be further shortened and the manufacturing time of the wiring board can be shortened by setting the thickness of the vapor-deposited metal layer, which is slower than the electrolytic plating layer, to 0.1 μm or less. Therefore, an inexpensive wiring board can be provided.

  Moreover, the base of an electroplating layer can fully be formed because the thickness of an electroless-plating layer shall be 0.1 micrometer or more. Further, the resistance of the via conductor can be reduced by setting the thickness of the electroless plating layer having a higher conduction resistance than that of the vapor-deposited metal layer or the electrolytic plating layer to 2 μm or less.

  Moreover, the conduction resistance of a wiring conductor layer can be made small by making the thickness of the electroplating layer with a low conduction resistance into 5 micrometers or more.

  In addition, by setting the surface roughness of the electrolytic plating layer to Ra = 0.4 μm or less, transmission loss due to the skin effect can be suppressed, so that a wiring layer having excellent electrical characteristics can be formed.

  In addition, by setting the maximum depth of the recess formed in the main surface of the insulating layer to 3 μm or less, for example, even if it is a process that requires etching of the deposited metal layer or the electrolytic plating layer, the etching time can be shortened. Therefore, it is not necessary to allow extra etching time, and the manufacturing time of the wiring board can be shortened.

  In addition, the deposited metal layer is generally difficult to form on a vertical surface such as a through-hole, but the deposited metal layer can be easily formed by setting the thickness of the insulating layer to 50 μm or less. Can do.

  In addition, when the insulating layer is formed by containing a resin and an inorganic filler or a resin filler, the inorganic filler or the organic filler is degranulated in the roughening treatment step using the roughening liquid of the insulating layer, and a good roughened surface is obtained. Can be formed. Furthermore, a stable roughened surface can be formed by appropriately adjusting the particle size and volume% of the inorganic filler or resin filler.

  Then, by mounting an electric element such as a semiconductor element on the main surface of the wiring board described above, an electric device having excellent reliability can be obtained.

  In the method for manufacturing a wiring board according to the present invention, a step of forming a through hole in an insulating layer containing at least a resin, a step of forming a deposited metal layer on the main surface of the insulating layer and the through hole, and only the through hole Since the step of forming the electroless plating layer and the step of forming the electroplating layer on the insulating layer main surface and the through-hole, the wiring conductor layer does not have an electroless plating layer with low chemical durability, Peeling of the wiring conductor layer can be prevented, and since there is no residue between the wiring conductors, a decrease in insulation reliability can also be prevented. In addition, since the electroless copper plating layer is formed on the through conductor on the wall surface of the through hole where the formation of the deposited metal layer is likely to be insufficient, the electrolytic plating layer can be formed with a sufficient thickness. A decrease in conduction reliability can also be prevented.

  As shown in FIG. 1, for example, the wiring board of the present invention includes a core substrate 1 containing glass cloth and resin, a through hole 3 formed through the core substrate 1, and a through hole 3. The through-hole conductor 5 formed on the core substrate 1, the core wiring layer 7 formed on both surfaces of the core substrate 1, the insulating layer 9 formed on the main surface of the core substrate 1, and the insulating layer 9. The through hole 11, the via conductor 13 formed in the through hole 11, and the wiring conductor layer 15 formed on the main surface of the insulating layer 9 are configured.

  In such a wiring substrate, the core substrate 1 and the insulating layer 9 are composed of the core wiring layer 7 and the wiring conductor layer 15 arranged so as to sandwich the core substrate 1 and the insulating layer 9, the through-hole conductor 5 provided through each of the core substrate 1 and the insulating layer 9, The conductor 13 is supported and electrically insulated.

  The core wiring layer 7, the wiring conductor layer 15, the through-hole conductor 5, and the via conductor 13 are arbitrarily connected to form a wiring circuit.

  In the example of FIG. 1, the wiring substrate 17 is formed of a core substrate 1 having a plate-shaped core and an insulating layer 9 attached to the surface. The core body of the core substrate 1 has a function of preventing the wiring substrate 17 from warping, has a thickness of about 0.3 to 1.5 mm, and an epoxy resin or bismaleimide triazine on a glass cloth in which glass fibers are woven vertically and horizontally. Insulating layer 9 is impregnated with a thermosetting resin such as resin, and insulating layer 9 has a function as a support for wiring conductor layer 15, has a thickness of 10 to 80 μm, epoxy resin, modified polyphenylene ether resin, etc. It consists of a thermosetting resin.

  As shown in the enlarged view of the main part in FIG. 2, the via conductor 13 includes a vapor-deposited metal layer 13 a formed by sputtering or the like on the main surface of the insulating layer 9, and an electrolytic plating layer formed by plating. 13c are sequentially formed, and in the through hole 11, a deposited metal layer 13a formed by a sputtering method, an electroless plating layer 13b and an electrolytic plating layer 13c formed by a plating method are formed. Sequentially formed.

  Further, the wiring conductor layer 15 can be formed together with the via conductor 13. For example, in the example of FIG. 2, a vapor-deposited metal layer 15 a formed by a sputtering method or the like, an electrolytic plating layer 15 b formed by a plating method, It is composed of

  According to the wiring board 17 of the present invention, the electroless plating layer 13c is further formed by forming the electroless plating layer 13b in addition to the vapor deposition metal layer 13a even in the through hole 11 in which the formation of the vapor deposition metal layer 13a is difficult. The base metal layer can be sufficiently formed, the conduction failure of the via conductor 13 can be eliminated, and the conduction reliability can be improved. In addition, since there is no electroless plating layer inferior in chemical durability in the wiring conductor layer 15, peeling of the wiring conductor layer 15 can be prevented by etching or the like, and conduction failure and reduction in conduction resistance can be eliminated.

  The metal vapor deposition layers 13a and 15a can be formed by a sputtering method or the like, and it is preferable that Cu is a main component. The thickness is preferably 0.1 μm or less from the viewpoint of shortening the manufacturing time, and more preferably 0.08 μm or less.

  In addition, by setting the thickness of the electroless plating layer 13b to 0.1 μm or more, a sufficient base metal layer can be formed, and by setting the thickness to 0.3 μm or more, the metal deposition layer 13a is temporarily Even if there is an uncoated portion, the base metal layer can be formed reliably.

  Further, since the growth rate of the electroless plating layer 13b is slower than that of the electrolytic plating layer 13c, it is preferably 2 μm or less, and more preferably 1.5 μm or less from the viewpoint of shortening the manufacturing time.

  Moreover, the resistance value of the wiring conductor layer 15 can be made small by making the thickness of the electroplating layer 15b with small electric resistance into 5 micrometers or more. In particular, it is desirable that the thickness be 8 μm or more, and further 10 μm or more.

  Further, by setting the surface roughness of the electrolytic plating layers 13c and 15b to Ra = 0.4 μm or less, and further 0.2 μm or less, signal loss due to surface effects can be reduced even if a high-frequency signal is applied. it can.

  When the metal layer once formed on the main surface of the insulating layer 9 needs to be removed, the maximum depth of the recess on the main surface of the insulating layer is set to 3 μm or less, and further to 1 μm or less, thereby removing the metal layer. The time required can be shortened.

  Moreover, the vapor deposition metal layer 13a can be easily formed by making the thickness of the insulating layer 9 50 μm or less, and it is particularly desirable that the thickness be 35 μm or less.

  Next, the manufacturing method of this invention is demonstrated using Fig.3 (a)-FIG.6 (k).

  First, as shown in FIG. 3A, an insulating layer 9 having a thickness of 20 to 60 μm made of thermosetting material such as epoxy resin or modified polyphenylene ether resin is formed on the upper surface of the core substrate 1 having the core wiring layer 7. Stick and harden.

  Next, as shown in FIG. 3B, through holes 11 are formed in the insulating layer 9 by a carbon dioxide laser or a YAG laser.

  Next, as shown in FIG. 3C, the deposited metal layers 13a and 15a are formed on the inside of the through hole 11 and the main surface of the insulating layer 9 by any one of sputtering, vacuum deposition, and ion plating. To do.

  Next, as shown in FIG. 4D, a resist layer 19 is formed on the main surface of the insulating layer 9 covered with the vapor-deposited metal layer 15a by a method such as laminating or coating.

  Thereafter, as shown in FIG. 4E, an opening 19a is formed by exposure and development.

  Next, as shown in FIG. 4 (f), it is immersed in an electroless plating solution of copper sulfate, Rossell salt, formalin, EDTA sodium salt, stabilizer, etc. for about 30 minutes and exposed from the opening 19 The electroless plating layer 13b was deposited on the surface of the deposited metal layer 13a, and the resist layer 19 remaining in the 30 ° C. sodium hydroxide aqueous solution was removed.

  Next, as shown in FIG. 5G, a resist layer 21 is again formed on the main surface of the metal vapor-deposited layer 15a formed on the main surface of the insulating layer 9 by a method such as laminating and coating. As shown in h), the opening 21a was formed by exposure and development.

Next, as shown in FIG. 5 (i), by dipping for several hours while applying a current of 3 A / dm ^{2 in} an electrolytic copper plating solution composed of sulfuric acid, copper sulfate pentahydrate, chlorine, brightener, and the like. Electrolytic plating layers 13c and 15b were formed.

  Next, as shown in FIG. 6J, the plating resist layer 21 remaining in the 50 ° C. aqueous sodium hydroxide solution was removed.

  Next, as shown in FIG. 6 (k), the metal vapor-deposited layer 13a exposed by removing the resist layer 21 is removed by etching with a sulfuric acid aqueous solution such as sulfuric acid / hydrogen peroxide solution or copper sulfate at 25 ° C. To do.

  Furthermore, if necessary, another insulating layer 9 can be laminated, and the steps of FIGS. 3B to 6K can be repeated to produce the required number of wiring boards 17.

  According to such a manufacturing method of the present invention, the wiring board 17 of the present invention can be easily manufactured.

  And the electrical device of this invention excellent in reliability can be provided by mounting an electrical element via the solder | pewter etc. on the main surface of the wiring board 17 of this invention demonstrated above.

  Note that the wiring board 17 of the present invention is not limited to the above-described embodiment, and various modifications are possible within a range that does not depart from the gist of the invention. For example, in the above-described example, the insulating layer 9 is replaced with the core board. The wiring conductor layer 15 is formed on the main surface of the insulating layer 9, but the insulating layer 9 is stacked on both upper and lower surfaces of the core substrate 1, and the wiring conductor layer 15 is formed on both surfaces. Good. Further, the wiring conductor layers 15 formed on both surfaces may be electrically connected by the through conductors 5 formed inside the core substrate 1.

  Further, instead of the core substrate 1, for example, an insulating layer made of a liquid crystal polymer or the like may be used.

  Also, the method for manufacturing the wiring board 17 of the present invention is not limited to the above-described embodiment, and various modifications and improvements can be made without departing from the scope of the present invention. There is no problem.

(Example 1 Production of wiring board)
(1) Four 200 μm thick prepregs impregnated with 50% by volume of bismaleimide triazine resin are laminated on a glass cloth in which glass fibers are woven vertically and horizontally, and copper foil is laminated on the surface. After pressure bonding at a pressure of 5 MPa and heating at 200 ° C. for 2 hours to complete curing, the copper foil on the surface was processed by a subtractive method or the like to form a wiring conductor to produce a core substrate.

(2) And, while laminating sheets of the thickness shown in Tables 1 and 2 made of an epoxy resin formed by adopting a conventionally well-known doctor blade method on the core substrate, and applying a pressure of 1 MPa at 130 ° C., Temporarily cured.

(3) Subsequently, an insulating layer made of a temporarily cured epoxy resin is laminated on the core substrate, and heated and pressed from both sides at 100 ° C. for 30 seconds and 0.3 MPa by a hot press machine. Heated for hours and cured.

(4) Furthermore, a 50 μm diameter through hole was formed in the insulating layer formed on the main surface of the core substrate by a YAG laser.

(5) Next, a deposited metal layer having a thickness shown in Tables 1 and 2 was formed on the main surface of the insulating layer and the through hole by copper sputtering.

(6) Then, a photoresist mainly composed of an acrylic resin as a plating resist layer is deposited on the deposited metal layer formed on the main surface of the insulating layer, and an electroless copper plating layer is formed in the through hole by exposure and development. An opening for depositing was formed.

(7) Further, the deposited metal formed in the through-hole by dipping in an electroless copper plating solution of 60 ° C composed of copper sulfate, Rossel salt, formalin, EDTA sodium salt, stabilizer, etc. and adjusting the dipping time An electroless copper plating layer having the thickness shown in Tables 1 and 2 was formed on the surface of the layer 13a.

(8) Thereafter, the plating resist layer is removed with sodium hydroxide, and a plating resist layer mainly composed of an acrylic resin is applied again, and an electrolytic copper plating layer for the wiring conductor layer and the via conductor is formed by exposure and development. An opening was formed.

(9) Next, the electrode is immersed in an electrolytic copper plating solution made of sulfuric acid, copper sulfate pentahydrate, chlorine, brightener, etc. while applying a current of 3 A / dm ² for a predetermined time. An electrolytic copper plating layer having a thickness shown in 1 and 2 was formed, and a via conductor and a wiring conductor layer were formed.

(10) Thereafter, the plating resist layer was removed with sodium hydroxide, and the exposed vapor-deposited metal layer was removed with an aqueous sulfuric acid solution by adjusting the etching rate according to the thickness of the electroless copper plating layer.

(11) Then, a solder resist layer made of an acrylic-modified epoxy resin having a thickness of 20 μm and having openings for measuring insulation resistance and conduction resistance is formed on the surfaces of the insulating layer, the via conductor, and the wiring conductor layer to obtain a wiring board. .

(Preparation of wiring board of Comparative Example 1)
(1) Laminate four prepregs with a thickness of 200 μm impregnated with 50% by volume of bismaleimide triazine resin on a glass cloth woven glass fiber vertically and horizontally, and further laminate a copper foil on the surface, After pressure-bonding at a pressure of 5 MPa and heating at 200 ° C. for 2 hours to completely cure, a wiring conductor was processed on the surface copper foil by a subtractive method or the like to produce a core substrate.

(2) And the sheet | seat which consists of an epoxy resin formed by employ | adopting the conventionally well-known doctor blade method was laminated | stacked on the core body surface, and these were temporarily hardened at 130 degreeC and the pressure of 1 MPa.

(3) Subsequently, the core on which the sheet made of the temporarily cured epoxy resin is laminated is heated and pressed from both sides at 100 ° C. for 30 seconds and 0.3 MPa by a hot press machine, and further heated at 170 ° C. for 2 hours. And heat cured.

(4) Further, a through hole having a diameter of 50 μm was formed in the insulating layer by a YAG laser.

(5) Next, the surface of the insulating layer is immersed in an electroless copper plating solution at 60 ° C. made of copper sulfate, Rossell salt, formalin, EDTA sodium salt, stabilizer, etc., and the immersion time is adjusted as shown in Table 1. A thick electroless copper plating layer was formed.

(6) Next, a plating resist layer composed mainly of an acrylic resin was deposited, and an opening for forming a conductor pattern for depositing the electrolytic copper plating layer was formed by exposure and development.

(7) Next, each electrode is immersed in an electrolytic copper plating solution composed of sulfuric acid, copper sulfate pentahydrate, chlorine, brightener, etc. while applying a current of 3 A / dm ² for a predetermined period of time. The electrolytic copper plating layer was formed with a predetermined thickness.

(8) Thereafter, the plating resist layer was removed with sodium hydroxide, and the exposed electroless copper plating layer was removed by adjusting the etching rate using a sulfuric acid aqueous solution.

(9) Then, a solder resist layer made of an acrylic-modified epoxy resin having a thickness of 20 μm having openings for measuring insulation resistance and conduction resistance on the surface was formed to obtain a wiring board of Comparative Example 1.

(Preparation of wiring board of Comparative Example 2)
(1) Laminate four prepregs with a thickness of 200 μm impregnated with 50% by volume of bismaleimide triazine resin on a glass cloth woven glass fiber vertically and horizontally, and further laminate a copper foil on the surface, After pressure-bonding at a pressure of 5 MPa and heating at 200 ° C. for 2 hours to completely cure, a wiring conductor was processed on the surface copper foil by a subtractive method or the like to produce a core substrate.

(2) And the sheet | seat which consists of an epoxy resin formed by employ | adopting the conventionally well-known doctor blade method was laminated | stacked on the core body surface, and these were temporarily hardened at 130 degreeC and the pressure of 1 MPa.

(3) Subsequently, the core on which the sheet made of the temporarily cured epoxy resin is laminated is heated and pressed from both sides at 100 ° C. for 30 seconds and 0.3 MPa by a hot press machine, and further heated at 170 ° C. for 2 hours. And heat cured.

(4) Furthermore, a through hole having a diameter of 50 μm was formed in the insulating layer 9 by a YAG laser.

(5) Next, a deposited metal layer having a thickness shown in Table 1 was formed on the surface of the insulating layer by copper sputtering.

(6) Next, a plating resist layer composed mainly of an acrylic resin was deposited, and an opening for forming a conductor pattern for depositing the electrolytic copper plating layer was formed by exposure and development.

(7) Next, each electrode is immersed in an electrolytic copper plating solution composed of sulfuric acid, copper sulfate pentahydrate, chlorine, brightener, etc. while applying a current of 3 A / dm ² for a predetermined period of time. The electrolytic copper plating layer was formed with a predetermined thickness.

(8) Thereafter, the plating resist layer was removed with sodium hydroxide, and the exposed vapor-deposited metal layer was removed by adjusting the etching rate using an aqueous sulfuric acid solution.

(9) Then, a solder resist layer made of an acrylic-modified epoxy resin having a thickness of 20 μm and having openings for measuring insulation resistance / conducting resistance on the surface was formed to obtain a wiring board of Comparative Example 2.

In addition, the test board for evaluating connection reliability includes a chain formed by upper and lower two-layer wiring conductors located inside the core board and through-holes electrically connecting both of them. did. The connection reliability is evaluated by a temperature cycle test TCT in which a sample is 30 minutes at a temperature of −55 ° C. and a cycle of 30 minutes at a temperature of 125 ° C., and a high temperature pressurization test PCT at 121 ° C. and 100% RH. The TCT was evaluated after 1000 cycles, and the PCT was measured by measuring the conduction resistance and insulation resistance of the via chain after 168 hours, and comparing the rate of change in conduction resistance and the insulation resistance value before and after the test.

  From Table 1, Sample No. in which a via conductor outside the scope of the present invention is not formed of a vapor-deposited metal layer, an electroless metal layer, or an electrolytic metal layer. Among Samples 2 and 3, Sample No. 1 was Comparative Example 1 in which only the electroless plating layer was formed as the base metal of the electrolytic plating layer. In No. 2, 0.3 μm of the electroless plating layer was insufficient, and the formation of the electroplating layer was insufficient, resulting in an open failure after the temperature cycle test, and the continuity could not be maintained.

  Further, Sample No. 2 which is Comparative Example 2 in which only the vapor deposition metal layer was formed as the base metal of the electrolytic plating layer. In No. 3, the increase in conduction resistance after the temperature cycle test reached 25%, and the continuity could not be maintained.

On the other hand, sample No. 1 of the present invention in which a deposited metal layer and an electroless plating layer were sequentially formed as the base metal of the electrolytic plating layer. In No. 1, the increase in conduction resistance was only 4%, and the insulation resistance value was 10 ⁸ Ω, indicating excellent reliability.

  From Table 2, the sample No. 1 in which the thickness of the deposited metal layer forming the wiring conductor layer is 0.1 μm. In sample 4, sample no. The increase in the conduction resistance is almost the same as that of Sample No. 1, but the deposited metal layer is thicker. In No. 5, it took time to etch the deposited metal layer, so that the electrolytic plating layer portion was thinned, and the conduction resistance was slightly increased.

  Further, sample No. 1 in which the thickness of the electroless plating layer forming the via conductor layer was changed. Among sample Nos. 6 to 10, the thickness of the electroless plating layer is less than 0.1 μm. In No. 6, the electroplating layer was partially insufficiently formed, so that the rate of change in conduction resistance was 12%, which was slightly higher.

  In addition, the sample No. in which the thickness of the electroless plating layer is larger than 2 μm. In No. 10, the ratio of electrolytic plating with a small increase in conduction resistance was lower than electroless plating with a large increase in conduction resistance due to the temperature cycle, so the rate of change in conduction resistance was 11%, which was slightly higher. In comparison with these samples, the thickness of the electroless plating layer forming the via conductor layer is 0.1 to 2 μm. 7, 8, and 9, the favorable change rate of the conductive resistance is 9% or less, and it can be seen that it has high reliability.

  In addition, the sample No. 1 in which the thickness of the electrolytic plating layer constituting the wiring conductor layer is smaller than 5 μm. In No. 11, since the thickness of the electrolytic plating layer with respect to the deposited metal layer was reduced, a slight increase in conduction resistance was observed in the temperature cycle test. On the other hand, Sample No. with an electrolytic plating layer thickness of 5 μm. In No. 12, no problem occurred in the conduction resistance.

  In addition, the sample No. 2 in which the maximum depth of the recess formed in the main surface of the insulating layer exceeds 3 μm and is 4 μm. In No. 13, the etching time was long to completely etch the deposited metal layer formed on the bottom of the recess exceeding 3 μm, and the wiring conductor was thinned. Therefore, the conduction resistance increased in the temperature cycle, or the deposition was deposited on the bottom of the recess. There was a slight decrease in insulation resistance in the unsaturated PCT test due to a slight metal layer remaining. On the other hand, Sample No. whose maximum depth of the dent is 3 μm or less. No increase in conduction resistance due to the temperature cycle or decrease in insulation resistance due to the unsaturated PCT test was observed in No. 14.

  In addition, Sample No. with an insulating layer thickness of 50 μm No. 15 was the same as that when the thickness of the insulating layer was 35 μm after the temperature cycle. In No. 16, the change rate of the conduction resistance after the temperature cycle was 12%, and the conduction resistance slightly increased.

It is sectional drawing which shows an example of embodiment of the wiring board of this invention. It is a principal part expanded sectional view which shows an example of embodiment of the wiring board of this invention. It is a principal part expanded sectional view which shows the manufacturing process of the wiring board of the wiring board of this invention. It is a principal part expanded sectional view which shows the manufacturing process of the wiring board of the wiring board of this invention. It is a principal part expanded sectional view which shows the manufacturing process of the wiring board of the wiring board of this invention. It is a principal part expanded sectional view which shows the manufacturing process of the wiring board of the wiring board of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Core substrate 5 ... Through-hole conductor 7 ... Core wiring layer 11 ... Through-hole 13 ... Via conductor 13a ... ... Vapor deposition metal layer 13b ... Electroless plating layer 13c ... Electroplating layer 15 ... Wiring conductor layer 15a ... Vapor deposition metal layer 15b ... Electrolytic plating layer 17... Wiring board 19... Electroless plating resist layer in via portion 21... Electrolytic plating resist layer in via portion and wiring conductor portion

Claims (10)

An insulating layer containing at least a resin; a wiring conductor layer formed on a surface of the insulating layer; and a via conductor layer connecting the wiring conductor layer penetrating the insulating layer and separated by the insulating layer; The wiring conductor layer is formed by sequentially forming a vapor-deposited metal layer and an electrolytic plating layer on the main surface of the insulating layer, and the via conductor layer is sequentially formed in the through-hole formed in the insulating layer. A wiring board comprising a vapor-deposited metal layer, an electroless copper plating layer, and an electrolytic plating layer. The wiring board according to claim 1, wherein the vapor-deposited metal layer has a thickness of 0.1 μm or less. The wiring board according to claim 1, wherein the electroless plating layer has a thickness of 0.1 to 2 μm. 4. The wiring board according to claim 1, wherein the thickness of the electrolytic plating layer forming the wiring conductor layer is 5 μm or more. 5. The wiring board according to claim 1, wherein the surface roughness of the electrolytic plating layer is Ra = 0.4 μm or less. The wiring board according to claim 1, wherein the maximum depth of the recess formed in the main surface of the insulating layer is 3 μm or less. The wiring board according to claim 1, wherein the insulating layer has a thickness of 50 μm or less. The wiring board according to claim 1, wherein the insulating layer comprises at least a resin and an inorganic filler or a resin filler. An electrical device comprising an electrical element mounted on the main surface of the wiring board according to claim 1. A step of forming a through hole in an insulating layer containing at least a resin, a step of forming a deposited metal layer on the main surface of the insulating layer and the through hole, a step of forming an electroless plating layer only on the through hole, and insulation And a step of forming an electrolytic plating layer on the layer main surface and the through hole.

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