JP2010205801A - Method of manufacturing wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board having high electric connection reliability between a lower-layer wiring conductive layer and an upper-layer wiring conductive layer via a via hole. <P>SOLUTION: A method of manufacturing a wiring board includes processes for stacking an upper-layer insulating layer 3 on a lower-layer insulating layer 1 where a lower-layer wiring conductor 2 is formed, forming a via hole 4 on the upper-layer insulating layer 3, performing desmear treatment of the surface of the upper-layer insulating layer 3 including the inside of the via hole 4, performing soft etching to the surface of the lower-layer wiring conductor 2 exposed to a bottom surface of the via hole 4 so that a gap V is formed between the lower-layer wiring conductor 2 and a lower surface of the upper-layer insulating layer 3 on an upper layer around the via hole 4, performing cleaner conditioner treatment to the surface of the upper-layer insulating layer 3 and the inside of the via hole 4, adsorbing a catalyst for electroless plating onto the surface of the upper-layer insulating layer 3, depositing an electroless plating layer 5 on the surface of the upper-layer insulating layer 3, and depositing an electroless plating layer 7 onto the surface of the electroless plating layer 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a wiring board.

  2. Description of the Related Art Conventionally, a wiring board formed by a build-up method is known as an organic material-based multilayer wiring board for mounting a semiconductor element such as a semiconductor integrated circuit element. This wiring board is formed by alternately laminating insulating layers and wiring conductors in multiple layers, and is laminated on the lower wiring conductor formed on the lower insulating layer and on the lower insulating layer and the lower wiring conductor. The upper wiring conductor formed on the upper insulating layer thus formed is attached to a via hole provided in the upper insulating layer with the lower wiring conductor bottom, and a part of the upper wiring conductor is deposited. It is connected by.

Such a wiring board is manufactured as follows. First, a lower wiring conductor is formed in a predetermined pattern on a lower insulating layer. As the lower insulating layer, a glass fiber reinforced resin layer obtained by impregnating a glass fiber base material with a thermosetting resin or a filler-containing resin layer obtained by dispersing an inorganic insulating filler such as silica in a thermosetting resin Are preferably used. Further, as the lower wiring conductor, a copper foil or a copper plating layer is preferably used.

  Next, an upper insulating layer is laminated on the lower insulating layer and the lower wiring layer. As the upper insulating layer, a glass fiber reinforced resin layer obtained by impregnating a glass fiber base material with a thermosetting resin or a filler-containing resin layer obtained by dispersing an inorganic insulating filler such as silica in a thermosetting resin is suitable. Used for.

  Next, a via hole whose bottom surface is the lower conductor layer is formed at a predetermined position of the upper insulating layer. For the formation of the via hole, a laser processing method using a carbon dioxide laser or a YAG laser is preferably used.

  Next, a desmear process is performed in order to roughen the surface of the upper resin layer and remove the resin residue remaining in the via hole. The desmear treatment is performed by a potassium permanganate treatment after the swelling treatment and finally a reduction treatment.

  Next, cleaner conditioner treatment is performed on the surface of the upper insulating layer and in the via hole. As a result, dirt on the surface of the upper insulating layer and the via hole is removed, and the adsorptivity of the electroless plating catalyst to the surface of the upper insulating layer including the inside of the via hole is improved.

  Next, the lower wiring conductor surface exposed on the bottom surface of the via hole is soft etched. By this soft etching, the oxide film and the resin residue on the surface of the lower wiring conductor are completely removed. For the soft etching, a mixed solution of sulfuric acid and hydrogen peroxide water is used, and a thickness of about 1 to 2 μm is etched from the surface of the lower wiring conductor.

  Next, after removing the smut formed by the soft etching on the surface of the lower wiring conductor exposed at the bottom of the via hole by acid cleaning, the surface of the upper resin layer including the inside of the via hole is electrolessly plated by activator treatment. Sn-Pd catalyst is adsorbed.

  Next, after removing Sn in the Sn—Pd catalyst by the accelerator treatment, an electroless copper plating layer having a thickness of about 0.2 to 2 μm is deposited on the surface of the upper resin layer including the inside of the via hole.

  Next, a plating resist layer having an opening corresponding to the upper wiring conductor is deposited on the electroless copper plating layer, and then an upper layer is formed on the electroless copper plating layer in the opening of the plating resist layer. An electrolytic copper plating layer having a shape corresponding to the wiring conductor is applied to a thickness of about 10 to 20 μm. At this time, an electrolytic copper plating layer is deposited in the via hole.

  Next, the plating resist layer is removed by removing with an alkaline resist stripping solution, and the upper wiring conductor is formed by etching away the electroless copper plating layer where the electrolytic copper plating layer is not deposited. It is formed. Thereafter, if necessary, further upper insulating layers and wiring conductors are formed by the same method as described above, and finally a solder resist layer is formed on the outermost layer as necessary to complete the wiring board.

JP 2003-60330 A

  However, according to this conventional method of manufacturing a wiring board, when the lower surface of the wiring conductor exposed on the bottom surface of the via hole is soft etched, the etching greatly proceeds in the lateral direction from the lower end of the via hole to the lower surface of the upper insulating layer. As a result, a small void portion formed in the lateral direction is formed between the lower wiring conductor and the lower insulating layer lower surface around the via hole. Then, when the electroless copper plating layer is deposited by the activator process in such a state where the void is formed, the electroless copper plating layer is satisfactorily deposited on the lower surface of the upper insulating layer in the void. As a result, when an electrolytic plating layer is deposited in the via hole, the electrolytic copper plating layer is not deposited well in the via hole, and the electrical connection between the lower wiring conductor layer and the upper wiring conductor layer via the via hole does not occur. There is a problem in that the wiring board has low general connection reliability.

  The present invention has been devised in view of such conventional problems, and includes a step of laminating an upper insulating layer on a lower insulating layer having a lower wiring conductor formed on the upper surface, and the upper insulating layer. A step of forming a via hole with the lower conductor layer as a bottom surface, a step of desmearing the surface of the upper insulating layer including the inside of the via hole, and a surface of the lower layer wiring conductor exposed on the bottom surface of the via hole, Performing a soft etching process so that a small void is formed between the lower wiring conductor and the lower surface of the upper insulating layer around the via hole; and the surface of the upper insulating layer and the via hole A cleaner conditioner treatment inside, a step of adsorbing a catalyst for electroless plating on the surface of the upper insulating layer including the inside of the via hole, and the inside of the via hole Including a step of depositing an electroless plating layer on the surface of the upper insulating layer including, and a step of depositing the electroplating layer on the surface of the electroless plating layer including the inside of the via hole in a predetermined pattern. It is a feature.

  According to the method for manufacturing a wiring board of the present invention, the surface of the lower wiring conductor exposed on the bottom surface of the via hole formed in the upper insulating layer is formed between the lower wiring conductor and the lower surface of the upper insulating layer around the via hole. After performing soft etching so that a small void portion is formed in the lateral direction, a cleaner conditioner treatment is performed on the surface of the upper insulating layer and the via hole, so that the upper insulating layer in the void portion is formed. A state where the adsorptivity of the electroless plating catalyst is improved by the cleaner conditioner treatment is also formed on the lower surface of the substrate. Therefore, when the electroless plating catalyst is adsorbed on the surface of the upper insulating layer including the inside of the via hole, the electroless plating catalyst is also adsorbed well on the lower surface of the upper insulating layer in the gap, and the via hole continues. When an electroless plating layer is deposited on the surface of the upper insulating layer including the inside, the electroless plating is satisfactorily deposited. As a result, the electrolytic plating layer can be satisfactorily deposited on the surface of the electroless plating layer including the inside of the via hole, and the electrical connection reliability between the lower wiring conductor layer and the upper wiring conductor layer through the via hole A high wiring board can be provided.

FIG. 1 is a fragmentary cross-sectional view for explaining a method of manufacturing a wiring board according to the present invention.

  Next, embodiments of the method for manufacturing a wiring board according to the present invention will be described with reference to the accompanying drawings. First, as shown in FIG. 1A, a lower wiring conductor 2 is formed on the upper surface of the lower insulating layer 1. As the lower insulating layer 1, a glass fiber reinforced resin layer obtained by impregnating a glass fiber base material with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, or a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. A filler-containing resin layer in which an inorganic insulating filler such as silica is dispersed is preferably used. As the lower wiring conductor 2, a copper foil or a copper plating layer is preferably used, and is formed in a predetermined pattern by using a wiring forming technique such as a well-known subtractive method or semi-additive method. The lower insulating layer 1 has a thickness of about 20 to 800 mm, and the lower wiring conductor 2 has a thickness of about 10 to 50 μm.

  Next, as shown in FIG. 1B, the upper insulating layer 3 is laminated on the lower insulating layer 1 and the lower wiring conductor 2. As the upper insulating layer 3, a glass fiber reinforced resin layer formed by impregnating a glass fiber base material with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, an epoxy resin or a bismaleimide as in the lower insulating layer 1. A filler-containing resin layer in which an inorganic insulating filler such as silica is dispersed in a thermosetting resin such as a triazine resin is preferably used. The thickness of the upper insulating layer 3 is about 20 to 50 μm.

  Next, as shown in FIG. 1C, a plurality of via holes 4 are formed in the upper insulating layer 3 with the lower wiring conductor 2 as the bottom surface. The diameter of the via hole 4 is about 30 to 100 μm. For the formation of the via hole 4, a laser processing method using a carbon dioxide gas laser or a YAG laser is used. At this time, smears S such as resin scraps scattered by laser processing adhere to the inside and the periphery of the via hole 4 and the surface of the lower wiring conductor 2 exposed on the bottom surface of the via hole 4 is removed by laser processing. A thin resin residue R that has not been cut remains.

  Next, as shown in FIG. 1D, the surface of the upper insulating layer 3 is roughened by performing a desmear process, and the smear S and the resin residue R are removed. The desmear treatment is performed by swelling treatment with an alkaline aqueous solution containing sodium hydroxide and the like, followed by potassium permanganate treatment, and finally reduction treatment with an acidic aqueous solution containing sulfuric acid and the like.

  Next, as shown in FIG. 1E, the surface of the lower wiring conductor 2 exposed on the bottom surface of the via hole 4 is soft-etched to a thickness of about 0.2 to 2 μm. At this time, a small void V is formed between the lower wiring conductor 2 and the lower surface of the upper insulating layer 3 around the via hole 4. Note that the oxide film and the resin residue R on the surface of the lower wiring conductor 2 are completely removed by this soft etching. For the soft etching, an etching solution made of a mixed solution of sulfuric acid and hydrogen peroxide is used.

  Next, cleaner conditioner treatment is performed on the surface of the upper insulating layer 3 and the via holes 4. At this time, dirt on the surface of the upper insulating layer 3 and the via hole 4 is removed, and the adsorptivity of the electroless plating catalyst to the surface of the upper insulating layer 3 including the via hole 4 is improved. In this case, since the cleaner conditioner treatment is performed after the soft etching, a state in which the adsorptivity of the catalyst for electroless plating is improved by the cleaner conditioner treatment is also formed on the lower surface of the upper insulating layer 3 in the gap V. In addition, what is necessary is just to perform a cleaner conditioner process using a commercially available process liquid.

  Next, after removing the smut formed by the soft etching on the surface of the lower wiring conductor 2 exposed on the bottom surface of the via hole 4 by acid cleaning, an activator treatment is performed on the surface of the upper resin layer 3 including the inside of the via hole 4. Sn-Pd catalyst for electroless plating is adsorbed. At this time, since the state in which the adsorptivity of the catalyst for electroless plating is improved by the cleaner conditioner treatment is also formed on the lower surface of the upper insulating layer 3 in the void portion V, the upper insulating layer 3 in the void portion V is formed. The catalyst for electroless plating is also adsorbed satisfactorily on the lower surface of the substrate.

  Next, after Sn in the Sn—Pd catalyst is removed by an accelerator treatment, the thickness of the upper resin layer 3 including the inside of the via hole 4 is about 0.2 to 2 μm as shown in FIG. The electroless copper plating layer 5 is applied. At this time, since the electroless plating catalyst is well adsorbed on the lower surface of the upper insulating layer 3 in the void portion V, the surface of the upper insulating layer 3 including the inside of the void portion V of the via hole 4 is electrolessly formed. The copper plating layer 5 is deposited satisfactorily. A commercially available electroless copper plating solution may be used to deposit the electroless copper plating layer 5.

  Next, as shown in FIG. 1 (g), a plating resist layer 6 having an opening A having a shape corresponding to the upper wiring conductor is deposited on the electroless copper plating layer 5, and then the plating resist layer 6. On the electroless copper plating layer 5 in the opening A, an electrolytic copper plating layer 7 having a shape corresponding to the upper wiring conductor is deposited to a thickness of about 10 to 20 μm. At this time, since the electroless copper plating layer 5 is satisfactorily deposited on the surface of the upper insulating layer 3 including the inside of the void portion V of the via hole 4, electrolytic copper is deposited on the surface of the via hole 4 and the upper insulating layer 3. A plating layer 7 is applied.

  Next, as shown in FIG. 1 (h), the plating resist layer 6 is peeled off with an alkaline stripping solution containing sodium hydroxide and removed, and the portion where the electrolytic copper plating layer 7 is not deposited is removed. The upper wiring conductor 8 is formed by removing the electroless copper plating layer 5 by etching. At this time, the electroless copper plating layer 5 and the electrolytic copper plating layer 7 forming the upper wiring conductor 8 are satisfactorily applied to the surface of the upper insulating layer 3 including the inside of the void portion V of the via hole 4. Thus, it is possible to provide a wiring board having high electrical connection reliability between the lower wiring conductor layer 2 and the upper wiring conductor layer 8 via the via hole 4.

  Note that the method for manufacturing a wiring board according to the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, the above-described embodiment is possible. After the desmear process described with reference to FIG. 1D and before the soft etching described with reference to FIG. 1E, a cleaner conditioner is formed on the surface of the upper insulating layer 3 and in the via hole 4. Additional processing may be performed.

DESCRIPTION OF SYMBOLS 1 Lower insulating layer 2 Lower wiring conductor 3 Upper insulating layer 4 Via hole 5 Electroless plating layer 7 Electrolytic plating layer 8 Upper wiring conductor

Claims (1)

A step of laminating an upper insulating layer on a lower insulating layer having a lower wiring conductor formed on the upper surface; a step of forming a via hole having the lower conductive layer as a bottom surface in the upper insulating layer; A step of desmearing the surface of the upper insulating layer including the inside of the via hole, and a surface of the lower wiring conductor exposed on the bottom surface of the via hole between the lower wiring conductor and the lower surface of the upper insulating layer around the via hole. A soft etching process so that a small void portion is formed in the lateral direction therebetween, a cleaner conditioner process is performed on the surface of the upper insulating layer and the via hole, and the upper layer including the inside of the via hole. Adsorbing a catalyst for electroless plating on the surface of the insulating layer, and depositing an electroless plated layer on the surface of the upper insulating layer including the inside of the via hole That step a method of manufacturing a wiring substrate, characterized by performing the electrolytic plating layer on the surface of the electroless plating layer comprising the via hole sequentially and a step of depositing a predetermined pattern.

Images