JP2000049459A - Manufacture of multilayer printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer printed wiring board, which eliminates places in the lower ends of via holes where the thickness of plated layers is formed thin in comparison with the thickness of the plated layers on the peripheries of the places, and raises reliability in continuity of the board. SOLUTION: Conductor layers 1b under the bottoms of via holes 3 are etched, and, after the peripheral walls of the holes 3 are removed, plated layers 4 are respectively formed in the holes 3. The peripheral walls of the holes 3 are shaved to enable the layers 1b only under the bottoms of the holes 3 to protrude, the layers 4 are adhered to the protruding parts of conductor layers 1a, the continuity failure of a multilayer printed wiring board at places where the layers 4 are formed thin can be prevented, and the reliability in continuity of the board can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board used for, for example, electronic equipment, electric equipment, computers, communication equipment, and the like.

[0002]

2. Description of the Related Art A printed wiring board used for an electronic device or the like is formed by laminating a conductive pattern such as a copper foil on one or both sides of a plate-shaped insulating layer. 2. Description of the Related Art In recent years, with the demand for miniaturization and high performance of electronic devices, it has been desired that printed wiring boards used therein have higher density and thinner. In order to cope with such an application, a multilayer printed wiring board formed by laminating a plurality of conductor layers forming a circuit via an insulating layer is used.

In particular, in a multilayer printed wiring board, an insulating layer is laminated on a conductive layer forming a circuit, and a via hole is formed in the insulating layer using a laser to expose the conductive layer.
A built-up type printed wiring board in which a plating layer is provided in a via hole to connect upper and lower conductor layers has been actively developed, and its form and method are various.

In this built-up system, via holes 3
FIG. 4 shows that a part of the insulating layer 2 formed of resin remains on the surface of the conductor layer 1b at the bottom of the via hole 3 when the substrate is formed, and the residue 6 is not removed from the surface of the conductor layer 1b even by desmearing. 1 (d) may occur.
Even if plating is performed in the via hole 3 in this state, a residue that is an electrical insulator is interposed between the plating layer 4 and the conductor layer 1b, and there is a problem that conduction reliability cannot be maintained. Therefore, as shown in FIG. 1E, a method of completely removing the residue 6 of the insulating layer 2 remaining by etching the surface layer portion of the conductor layer 1b on the bottom surface of the via hole 3 is adopted.

There is another problem in the conduction reliability of the via hole 3. That is, irregularities are generated on the peripheral wall of the via hole 3, and when the via hole 3 is plated, particularly, a thin portion of the plating layer 4 is generated.

It is considered that this may be caused by variations in energy at the time of laser irradiation, irregularities in the end face due to fluctuations in the irradiation angle, and the inability to secure the thickness of the plating layer 4, and the like. After the via hole 3 is formed in the insulating layer 2 as shown in FIG. 1D, a pretreatment (for example, acid cleaning, soft etching) performed by a normal plating process is performed as shown in FIG. Although the conductor layer 1b at the bottom of the via hole 3 is largely etched, the lower tip of the end face of the insulating layer 2 is not removed at all and is left behind. Therefore, as a result, a large convex portion 7 is formed at the boundary between the insulating layer 2 and the conductor layer 1b. Even if this convex portion 7 is plated, the plating layer 4 is extremely thin as shown in FIG. Is extremely low.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and eliminates a portion where a thickness of a plating layer is thinner than a surrounding portion at a lower end of a via hole, thereby providing a multilayer print having good conduction reliability. It is an object of the present invention to provide a method for manufacturing a wiring board.

[0008]

According to a first aspect of the present invention, there is provided a method for manufacturing a multilayer printed circuit board, wherein a plurality of insulating layers and a plurality of conductor layers are alternately laminated and provided on the insulating layer. This is a method of manufacturing a multilayer printed circuit board formed by making electrical connection between conductor layers 1 by plating layers 4 on the inner periphery of via holes 3, wherein laser is applied to insulating layer 2 covering conductor layer 1. Then, the insulating layer 2 is removed until the conductive layer 1 is exposed to form a via hole 3, and the residue 6 of the insulating layer 2 remaining on the surface of the conductive layer 1 at the bottom of the via hole 3 is removed. After the surface layer of the conductor layer 1 is removed by etching and the insulating layer 2 forming the peripheral wall of the via hole 3 is removed, plating is performed in the via hole 3 to make an electrical connection between the conductor layers 1. 4 is characterized by forming That.

According to a second aspect of the present invention, in the method of manufacturing a multilayer printed board, the insulating layer 2 is made of a resin containing an epoxy resin as a main component, and the conductive layer 1 and a plating layer connecting the conductive layers 1 are provided. The method of removing the residue 6 of the insulating layer 2 remaining on the surface of the conductor layer 1 at the bottom of the via hole 3 and the method of removing the insulating layer 2 at the portion forming the peripheral wall of the via hole 3 are wet methods. Characterized by a permanganate treatment.

The method for manufacturing a multilayer printed circuit board according to claim 3 of the present application is characterized in that, in addition to the features of the method for manufacturing a multilayer printed circuit board according to claim 2 of the present application, the treatment with a wet permanganate is It is characterized by swelling of the resin component on the peripheral wall of the via hole by the surfactant, oxidation of the resin component by the permanganate, and removal of the oxide film formed by this oxidation.

The method for manufacturing a multilayer printed circuit board according to claim 4 of the present application is characterized in that, in addition to the features of the method for manufacturing a multilayer printed circuit board according to claims 1 to 3, the surface layer portion of the conductor layer 1b is etched. The method for removing is a wet etching process.

The method for manufacturing a multilayer printed circuit board according to claim 5 of the present application is characterized in that, in addition to the features of the method for manufacturing a multilayer printed circuit board according to claim 4 of the present application, the wet etching treatment uses an organic acid. It is characterized by being.

[0013]

Embodiments of the present invention will be described below.

A portion 8 of the conductor layer 1a on the surface of a multilayer board in which conductor layers 1 such as a metal foil and insulating layers 2 such as a resin as shown in FIG. 1
(B)).

The conductor layer 1a on the surface is removed, and the exposed insulating layer 2 is removed by a laser to form a via hole 3 so that the insulating layer 2 reaches the next conductor layer 1b. When the insulating layer 2 is removed by the laser, the insulating layer 2 cannot be completely removed, and a small residue 6 remains as shown in FIG.

Next, the residue 6 is removed using a desmear solution.
A desmear treatment was performed, and as shown in FIG.
Remove most of As the desmear liquid, sodium permanganate is preferable.

Next, the surface layer portion of the conductor layer 1b forming the bottom surface of the via hole 3 is etched to completely remove the residue 6 adhered to the surface layer portion of the conductor layer 1b which is not removed even by the above desmear treatment (FIG. 1). (E)). As described above, at this time, the surface layer portion of the conductor layer 1b is etched, and the conductor layer 1b is shaved in the horizontal direction by the etchant, so that the protrusion 7 is formed at the interface between the conductor layer 1b and the insulating layer 2 forming the peripheral wall of the via hole. It is formed. Figure 1 shows the situation at this time.
FIG. 2A is an enlarged view of the upper via hole of FIG.

This etching treatment is preferably performed by a wet method using an etching solution. As a component of the etching solution, an acid such as an inorganic acid such as sulfuric acid or an organic acid such as malic acid or citric acid is used. Acids are preferred.

The desmear treatment is performed again using the above desmear liquid, and as shown in FIG. 1 (f), the portion of the insulating layer 2 which forms the peripheral wall of the via hole 3 is removed to obtain a so-called etch back state. As a result, the protrusion 7 formed by the above-described etching is formed only by the conductor layer 1b. The state at this time is shown in FIG. 2B, which is an enlarged view of the upper via hole in FIG.

After performing electroless plating over the inner surface of the via hole 3 and the conductor layer 1a, electrolytic plating is performed on the electroless plated layer to form a plating layer 4 (FIG. 1).
(G)). FIG. 3 shows an enlarged view of the state of the coating of the plating layer 4. As shown in FIG. 3, since the plating layer 4 is formed on the protrusion 7 formed only by the conductor layer 1b, the conduction reliability in this portion is improved.

[0021]

The present invention will be described below in detail with reference to examples. (Example 1) After forming a double-sided copper-clad laminate in a circuit state, the copper surface was blackened and a resin-coated copper foil (R0880, manufactured by Matsushita Electric Works, copper foil thickness 12 µm, resin thickness 60 µm)
m) was laminated and pressed from both sides to form a multilayer plate as a four-layer plate as shown in FIG. Next, a copper film, which is a conductor layer 1 on the surface of the multilayer board, is formed in a circular shape with a hole diameter of 150 μm by using a tenting method in which a dry film is attached to the surface of the multilayer board and the dry film is processed as an etching resist. Etching was performed as shown in FIG. The etched portion 8 was irradiated with a carbon dioxide gas laser to remove the epoxy resin as the insulating layer 2 within the hole diameter, thereby forming a via hole 3 as shown in FIG.

Next, the via-hole-formed multilayer board is immersed in a swelling liquid containing 10% by weight of diethylene glycol monobutyl ether at 75 ° C. for 5 minutes to swell the residual epoxy resin, and then 50 g of sodium permanganate is added.
/ L-containing desmear solution at 80 ° C for 10 minutes to remove the epoxy resin residue 6, and immersion in a neutralizing solution containing 10% sulfuric acid at 50 ° C for 5 minutes to oxidize the sodium permanganate. The oxide film formed by the action was removed.

Next, the multilayer board subjected to the desmear treatment was immersed in an etching solution containing 10% of methanesulfonic acid and 10% of sodium persulfate for 3 minutes, and the copper exposed at the bottom of the via hole 3 as shown in FIG. Foil (conductor layer 1b)
Of the copper foil (conductor layer 1b), which was not removed in the desmear process, was completely etched.

Next, the etched multilayer board is immersed again in a swelling solution containing 10% by weight of diethylene glycol monobutyl ether at 75 ° C. for 5 minutes to swell, and then a desmear solution containing 50 g / L of sodium permanganate. After removing the epoxy resin (insulating layer 2) which forms the peripheral wall of the via hole 3 by immersion in a neutral solution containing 10% sulfuric acid at 50 ° C. for 5 minutes to remove the oxide film. went. The peripheral wall of the via hole 3 was etched back to be in a state as shown in FIG.

Next, electroless copper plating using copper plating using palladium-tin as a catalyst is applied to the inner surface of the via hole 3 to a thickness of about 0.5 μm, and then 20 μm on the electroless copper plating layer by electrolytic copper plating. The plating layer 4 of FIG.
The layers were laminated as shown in (g).

Using the obtained multilayer board, 50 sheets having 2000 via holes per sheet were manufactured (100,000 via holes in total). These samples were placed in a room temperature atmosphere and immersed in 260 ° C. oil 10 times, and the conduction reliability of how many via holes out of 100,000 via holes were defective was examined. 200 tested via holes in this example
Out of 0 × 50 sheets (100,000), no conduction failure occurred at all. (Example 2) The composition of the etching solution was malic acid 10%,
A multilayer printed wiring board was obtained in the same manner as in Example 1 except that sodium persulfate was changed to 10%.

When a conduction reliability test was performed in the same manner as in Example 1, the number of via holes was 2,000 × 50 sheets (10
(0000 pieces), no conduction failure occurred at all. (Example 3) Citric acid 10%
A multilayer printed wiring board was obtained in the same manner as in Example 1 except that sodium persulfate was changed to 10%.

When a conduction reliability test was performed in the same manner as in Example 1, the number of via holes was 2,000 × 50 sheets (10
(0000 pieces), no conduction failure occurred at all. Example 4 A multilayer printed wiring board was obtained in the same manner as in Example 1 except that the composition of the etching solution was 10% sulfuric acid and 10% sodium persulfate.

When a conduction reliability test was performed in the same manner as in Example 1, the number of via holes was 2,000 × 50 sheets (10
Out of 0,000), 13 via holes with poor conduction occurred. (Comparative Example) After the etching step in Example 1, the same plating as in Example 1 was performed without performing the second swelling, treatment with the desmear solution, and the treatment of the oxide film to obtain a multilayer printed wiring board. .

When a conduction reliability test was performed in the same manner as in Example 1, the number of via holes was 2,000 × 50 sheets (10
Out of 000), 75 via holes with poor conduction occurred.

[0031]

As described above, according to the present invention, a plurality of insulating layers and a plurality of conductive layers are alternately laminated, and the electrical connection between the conductive layers is formed by a plating layer on the inner periphery of a via hole provided in the insulating layer. Forming a via hole by irradiating a laser to the insulating layer covering the conductive layer, removing the insulating layer until the conductive layer is exposed, and forming a via hole. After removing the remainder of the insulating layer remaining on the surface of the conductor layer at the bottom of the via hole, then removing the surface layer of the conductor layer at the bottom of the via hole by etching, removing the insulating layer that forms the peripheral wall of the via hole, and then plating inside the via hole In order to form a plating layer for making an electrical connection between the above conductor layers, the peripheral wall of the via hole can be shaved and only the conductor layer at the bottom of the via hole can be protruded. When forming the layer, the plating layer adheres to the protruding part of the conductor layer, which can prevent poor conduction at thin places of the plating layer, and improve the conduction reliability when plating inside the via hole Can be done.

According to a second aspect of the present invention, the insulating layer is made of a resin containing an epoxy resin as a main component, the conductor layer and a plating layer connecting the conductor layers are made of copper, and the bottom of the via hole is formed of copper. Since the method of removing the residue of the insulating layer remaining on the surface of the conductive layer and the method of removing the insulating layer in the portion forming the peripheral wall of the via hole are wet permanganate treatments, the conductive layer at the bottom of the via hole is used. The removal of the remainder of the insulating layer remaining on the surface of the via hole can be performed satisfactorily, and the insulating layer that forms the peripheral wall of the via hole is effectively removed, and the conduction reliability when plating is applied inside the via hole The property can be improved.

[0033] The invention according to claim 3 of the present application is characterized in that the treatment with the wet permanganate is such that the surfactant swells the resin component on the peripheral wall of the via hole, the permanganate oxidizes the resin component. And the removal of the oxide film formed by this oxidation, the removal of the remainder of the insulating layer remaining on the surface of the conductor layer at the bottom of the via hole can be performed favorably, and furthermore, the removal of the portion forming the peripheral wall of the via hole It is possible to effectively remove the insulating layer and to improve conduction reliability when plating is performed inside the via hole.

According to the invention described in claim 4 of the present application, since the method of etching and removing the surface layer portion of the conductor layer is a wet etching process, the surface layer portion of the conductor layer can be favorably etched. is there.

In the invention according to claim 5 of the present application, since the wet etching treatment is a treatment using an organic acid,
The surface layer of the conductor layer can be more favorably etched.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, in which (a)
(G) is a sectional view.

FIG. 2 shows an embodiment of the present invention, in which (a)
And (b) is an enlarged sectional view.

FIG. 3 is an enlarged sectional view showing the embodiment of the present invention.

FIG. 4 is an enlarged sectional view showing a conventional example.

[Explanation of symbols]

 1a conductor layer 1b conductor layer 2 insulating layer 3 via hole 4 plating layer 6 residue

Continued on the front page (72) Inventor Masayuki Ishihara 1048 Odakadoma, Kadoma-shi, Osaka F-term in Matsushita Electric Works, Ltd. (reference) 5E339 AB02 AC01 AD05 AE01 BC02 BD02 BD08 BE13 CD01 CD10 CE12 CE16 DD03 GG10 5E346 AA06 AA12 AA15 AA43 CC09 CC32 CC51 CC58 DD25 DD32 EE02 EE06 EE07 EE31 FF02 FF03 FF04 FF07 FF15 GG15 GG16 GG17 GG22 GG28 HH07

Claims (5)

[Claims] 1. A multilayer formed by alternately laminating a plurality of insulating layers and a plurality of conductor layers, and forming an electrical connection between the conductor layers with a plating layer on an inner periphery of a via hole provided in the insulating layer. A method of manufacturing a printed laminated board, which comprises irradiating a laser to an insulating layer covering a conductive layer, removing the insulating layer until the conductive layer is exposed, forming a via hole, and forming a via hole on the surface of the conductive layer at the bottom of the via hole. The residue of the remaining insulating layer is removed, then the surface layer of the conductor layer at the bottom of the via hole is removed by etching, and the insulating layer forming the peripheral wall of the via hole is removed. A method for manufacturing a multilayer printed wiring board, comprising forming a plating layer for making an electrical connection. 2. The insulating layer is made of a resin containing an epoxy resin as a main component, the conductive layer and a plating layer connecting the conductive layers are made of copper, and the insulating layer remaining on the surface of the conductive layer at the bottom of the via hole is provided. 2. The multilayer printed wiring board according to claim 1, wherein the method of removing the residue of the layer and the method of removing the insulating layer in the portion forming the peripheral wall of the via hole are wet permanganate treatments. Production method. 3. The wet treatment with a permanganate comprises swelling the resin component on the peripheral wall of the via hole with a surfactant, oxidizing the resin component with a permanganate, and an oxide film formed by this oxidation. The method for producing a multilayer printed wiring board according to claim 2, comprising removing. 4. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the method of etching and removing the surface layer portion of the conductor layer is a wet etching process. 5. The method according to claim 4, wherein the wet etching process is a process using an organic acid.