JP2008218540A - Manufacturing method for wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To fill a blind via hole with copper while uniformly electroplating a plating film thickness regardless of a pattern density. <P>SOLUTION: A manufacturing method for a wiring board has at least a process forming an insulating-resin layer 4 on the surface layer of a core board 2 forming a first wiring pattern 1, a process forming a seed layer 3 on the surface of the insulating-resin layer 4 and a process forming an alkali peeling type plating-resistive insulating layer as a lower-layer insulating layer 5 on the seed layer 3. The manufacturing method for the wiring board further has at least a process forming a heating peeling type plating-resistive insulating layer as an upper-layer insulating layer 6, a process forming the blind via hole 7 reaching up to the first wiring pattern 1 and a process forming an electroless copper plating layer 8. The manufacturing method for the wiring board further has at least a process peeling the upper-layer insulating layer of two kinds of plating-resistive insulating layers, a first electroplating process filling the inside of a blind via hole section with a hole-filling plating layer 9 by electrolytic copper plating and a second electroplating process forming a second wiring pattern by electrolytic copper plating. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a wiring board by a semi-additive method which has a filled via structure and is advantageous for forming a fine pattern.

  In recent years, due to miniaturization of electronic devices, the density of printed wiring boards to be used has been rapidly increased. For this reason, a large number of wiring boards called build-up boards have been produced. This build-up board is formed by alternately stacking insulating resin layers and wiring layers on the surface of the multilayer printed wiring board that is the core, and conduction between the wiring layers forms blind via holes and copper plating is formed inside Is done by doing In response to demands for further design freedom and higher wiring density, a method called field via was developed to fill the blind via hole with copper in order to form an upper layer blind via hole on the blind via hole. Have been mass-produced (for example, see Patent Document 1).

In addition, a high density of wiring patterns has been required at the same time, and the formation of the desired narrow pitch wiring patterns is performed by side etching during etching in the subtractive method in which the substrate surface is entirely copper-plated and etched. A fine pattern cannot be formed. For this reason, the surface of the substrate is subjected to a conductive treatment with a thin copper film to form a plating seed layer, a plating resist pattern is formed on the plating seed layer, immersed in a plating solution, and the plating seed layer is used as a cathode electrode. A semi-additive method in which electrolytic plating is performed and a wiring pattern is formed by depositing plating has attracted attention (for example, see Patent Document 2).
JP 2003-142828 A JP 2003-46245 A

  However, when filling a blind via hole and producing a wiring board by a semi-additive method that is advantageous for fine pattern formation, as a copper sulfate plating solution used for filling a blind via hole, supply sufficient copper ions in the via hole, A copper sulfate plating solution having a relatively high copper ion concentration and a low sulfuric acid concentration is used so that a good embedding property can be obtained, and the plating solution having such a composition has a poor electric conductivity of the bath. In the pattern plating used in the semi-additive method, there is a problem that the variation in the plating thickness due to the size of the pattern and the density is increased, which is a great obstacle to progress to a fine pitch pattern in the future.

  In addition, when filled vias that fill blind via holes with copper are plated by electrolytic copper plating, in general, the phenomenon of voids and holes not filling is avoided by reducing the current density. Compared to conformal via plating that does not fill with, there was a problem that productivity was inferior.

  The present invention solves the above-described conventional problems, and provides a method of manufacturing a wiring board that can fill a blind via hole with copper and can make a fine pattern without lowering productivity by utilizing a semi-additive construction method. For the purpose.

  In order to solve the above-described conventional problems, the present inventor has intensively studied to achieve the above-described object. As a result, a plating-resistant insulating layer is provided in addition to the outer periphery of the substrate and the blind via hole, and the copper ion plating solution having a relatively high copper ion concentration for normal field via plating on the substrate to be plated and a low sulfuric acid concentration, In addition, by plating at a low current density, the current concentrates in the blind via part, and the plating deposition speed is 3 to 5 times (the speed varies depending on the number of vias), and there is no void in the blind via. We found that via plating is possible. As a result, the conventional field via plating time can be reduced to 1/3 to 1/5. Therefore, first, field via plating is performed with a copper sulfate plating solution having a relatively high copper ion concentration and a low sulfuric acid concentration, and then a copper sulfate plating solution having a relatively low copper ion concentration and a high sulfuric acid concentration. The present inventors have completed the present invention by studying a process capable of performing pattern plating.

  The process of the present invention includes a step of forming an insulating resin layer on a surface layer of a core substrate on which a first wiring pattern is formed, a step of forming a seed layer on the surface of the resin layer, and a lower insulating layer on the seed layer A step of forming an alkali peeling type plating-resistant insulating layer, a step of forming a heat peeling type plating-resistant insulating layer as an upper insulating layer, and the first wiring from the surface of the two insulating layers. A step of forming a blind via hole leading to a pattern, a step of forming an electroless copper plating layer after applying a catalyst to the surface of the insulating layer and the blind via hole, and an upper insulating layer of the two types of plating-resistant insulating layers A first electrolytic plating step of feeding copper from the seed layer and filling the blind via hole portion with copper by electrolytic copper plating, and the lower layer insulation , A step of forming a plating resist layer according to the second wiring pattern formed on the seed layer, and a second wiring pattern is formed by electrolytic copper plating by supplying power from the seed layer A method of manufacturing a wiring board, comprising: a second electrolytic plating step, a step of removing the plating resist layer, and a step of etching away the seed layer immediately below the plating resist layer. .

  The wiring board manufacturing method of the present invention can fill the blind via hole with copper and perform electrolytic plating with a uniform plating film thickness regardless of the density of the pattern.

(Embodiment)
Hereinafter, a method for manufacturing a wiring board according to an embodiment of the present invention will be described with reference to the drawings and tables.

  1 and 2 are process cross-sectional views illustrating a method for manufacturing a wiring board according to an embodiment of the present invention.

  First, as shown in FIG. 1A, an epoxy resin (40 μm thickness) containing an inorganic filler with a thin copper foil (3 μm) whose surface is roughened on the surface layer of the core substrate 2 on which the first wiring pattern 1 is formed. The insulating layer is vacuum laminated to form the insulating resin layer 4. Then, it pressurizes and heats at 180 degreeC for 1 hour with a vacuum press, and forms the seed layer 3 which consists of copper foil. In the present invention, the seed layer 3 may be an electroless copper plating + electrolytic plating film, an electroless copper plating film, a copper film formed by vacuum deposition, or a copper film formed by sputtering.

  Next, as shown in FIG. 1B, a plating-resistant photoresist 5 made of an alkali peeling type dry film is formed on the seed layer 3 as a lower insulating layer. Further, a heat-peeling type anti-plating tape (for example, ELEGrip tape manufactured by Denki Kagaku Kogyo Co., Ltd.) 6 is formed on the photoresist 5 as a surface insulating layer.

  Next, as shown in FIG. 1C, a UV-YAG laser is used to irradiate the copper surface of the first wiring pattern 1 from above the photoresist 5 and the heat-peeling tape 6 to form blind via holes (Φ60 μm) 7. Form.

  Next, the desmear process of the blind via hole 7 is performed. As desmear treatment, first, OPC-1050 conditioner (Okuno Pharmaceutical Co., Ltd.) was swollen with a solution of sodium hydroxide added, and then OPC-1200 Epo Etch (Okuno Pharmaceutical Co., Ltd.) was used to improve the adhesion with the copper plating film. The inside of the blind via hole is roughened with a solution obtained by adding potassium permanganate to the product, and neutralized with an acidic solution. Next, as a pretreatment for electroless copper plating, conditioning is performed with OPC-390 Condy Clean M (Okuno Pharmaceutical Co., Ltd.), soft etching is performed with sodium persulfate, and desmut treatment is performed with sulfuric acid. Next, pre-dip with OPC-SALM solution (Okuno Pharmaceutical Co., Ltd.), attach catalyst (Pd) with OPC-80 catalyst (Okuno Pharmaceutical Co., Ltd.), and OPC-555 accelerator M (Okuno Pharmaceutical Co., Ltd.). Accelerator treatment and nucleation for electroless copper plating treatment. Then, as shown in FIG.1 (d), the electroless copper plating layer 8 (0.5-1.5 micrometers) is formed in a blind via hole with an electroless copper plating solution.

  Then, as shown in FIG.1 (e), the heat peeling tape 6 which is an upper layer insulation layer is heated in 140 degreeC atmosphere among the two types of plating-resistant insulation layers from which the said property differs, and the heat peeling tape 6 top The electroless copper plating layer 8 is peeled off.

Next, a plating depositing portion is provided on the periphery of the substrate to be plated, or a plating depositing portion is provided on the substrate fixing jig (not shown), and as shown in FIG. Power supply is performed, and first electrolytic plating is performed in which copper, which is a filling metal layer 9, is filled in the blind via hole 7. The first electrolytic plating contains 200 g / L of copper sulfate pentahydrate, 50 g / L of sulfuric acid, and 50 mg / L of chlorine ions for field via plating, and includes additives (polymer component composed of a polymer compound, sulfur-based compound). A plating solution to which an appropriate amount of a brightener component composed of a compound and a leveler component composed of a nitrogen compound was added was used. While immersing in this plating solution and stirring with air, the inside of the blind via hole 7 was filled with copper at a plating bath temperature of 25 ° C. and a cathode current density of 1 A / dm ² to form a hole-filled plating layer 9.

  Here, the first electrolytic plating process will be described in detail. In the present invention, the composition of the first electrolytic copper plating solution includes, for field via plating, copper sulfate pentahydrate 160 to 250 g / L, sulfuric acid 15 to 80 g / L, and chlorine ions 20 to 70 mg / L. An aqueous solution containing a sulfur-containing organic compound as an accelerator and a nonionic polyether polymer surfactant and a nitrogen-containing organic compound as an inhibitor is suitable. About copper sulfate pentahydrate, if it becomes 160 g / L or less, the inside of a blind via hole cannot be filled with copper, and if it is 250 g / L or more, copper sulfate becomes difficult to dissolve. Desirably, 170-230 g / L is good. As for sulfuric acid, the electrical conductivity is deteriorated at 15 g / L or less, and copper sulfate is hardly dissolved at 80 g / L. Desirably, 20-70 mg / L is good. With respect to chlorine ions, voids are likely to be generated inside vias at 20 mg / L or less, and copper filling properties inside vias are deteriorated at 70 mg / L or more. 30-60 mg / L is desirable.

In addition, a plating deposition part is provided in the periphery of the substrate to be plated, or a plating deposition part is provided in the substrate fixing jig, and the outer periphery of the substrate to be plated and other than blind via holes are masked with an insulating resin at a current density of 0.5 to ^{2 A} / dm ^2. Then, when electrolytic copper plating was performed, it was possible to fill the blind vias with copper in a time of 1/3 to 1/5 of the case without the insulating resin mask. Furthermore, when the cross section of the blind via was observed, no void was generated and copper was filled. This point was considered. If there is no insulating mask around the blind via and the outer periphery of the substrate, uniform current lines reach the entire surface of the substrate except for the peripheral portion of the substrate or the plating deposition portion of the substrate fixing jig, and plating deposition occurs almost uniformly. In addition, since the insulating mask or the plating deposition portion of the substrate fixing jig is present on the outer peripheral portion of the substrate, the current is concentrated on the blind via portion and the plating is promoted as compared with the outer peripheral portion of the substrate.

  In addition, since no plating deposition reaction takes place except for the blind via portion, the copper concentration in the plating solution around the via is in a copper-rich state in the peripheral portion of the via. It is considered that copper is filled inside the via without being conformal plating. In addition, the accelerator, which is an additive, is accumulated inside the via, and the inhibitor is concentrated on the upper part of the via having a strong current line, thereby accelerating the precipitation of copper inside the via. From this, it is considered that the effect of the additive can be effectively exhibited by the concentration of the current line in the via portion.

In the present embodiment, the conventional via plating in the blind via hole 7 having a diameter of 60 μm and a depth of 40 μm takes 120 minutes at 1 A / dm ² to fill the inside of the via. If the plating method was only for the part, it was possible to fill the copper in 25 minutes and form the hole-filled plating layer 9.

  Next, as shown in FIG. 2G, the photoresist 5, which is the lower insulating layer, is swelled and peeled off with an alkaline solution (4% sodium hydroxide solution). Thereafter, as shown in FIG. 2 (h), the surface is lightly polished, and a plating resist 10 is formed according to the second wiring pattern formed on the seed layer 3. In the second wiring pattern, a pattern corresponding to a semiconductor package substrate including a fine pattern of line width (L) / inter-line (S) = 25/25 μm was formed.

Next, as shown in FIG. 2I, power is supplied to the seed layer 3, and a second wiring pattern 11 is formed by second electrolytic copper plating. The second electrolytic copper plating solution for pattern plating contains copper sulfate pentahydrate 70 g / L, sulfuric acid 200 g / L, and chlorine ions 50 mg / L. Additives (polymer component composed of a high molecular compound, sulfur type) A plating solution to which an appropriate amount of a brightener component composed of a compound and a leveler component composed of a nitrogen compound was added was used. A second wiring pattern 11 was formed by performing electrolytic copper plating at a plating bath temperature of 25 ° C. and a cathode current density of 3 A / dm ² while being immersed in this plating solution and stirring with air.

  Next, the second electrolytic plating process for pattern plating will be described in detail. In the present invention, the composition of the second electrolytic copper plating solution includes copper sulfate pentahydrate 50 to 100 g / L, sulfuric acid 160 to 220 g / L, chlorine ion 20 to 70 mg / L, and sulfur-containing organic as an accelerator. As the compound and inhibitor, an aqueous solution containing a nonionic polyether polymer surfactant and a nitrogen-containing organic compound is suitable. With respect to copper sulfate pentahydrate, the physical properties of the plated copper film deteriorate when it is 50 g / L or less, and with a plating solution rich in sulfuric acid at 100 g / L or more, copper sulfate is difficult to dissolve. Desirably, 60-80 g / L is good. Regarding sulfuric acid, the throwing power is poor at 160 g / L or less, and copper sulfate is difficult to dissolve at 220 g / L or more. Desirably, 180-210 g / L is good. As for chlorine ions, the dissolution of copper at the anode and anode becomes poor at 20 mg / L or less, the supply of copper ions becomes insufficient, and the effect is not seen at 70 mg / L or more. 30-60 mg / L is desirable.

  Next, as shown in FIG. 2 (j), the plating resist 10 is swelled and peeled off with an alkaline solution (4% sodium hydroxide solution). Next, as shown in FIG. 2 (k), the seed layer 3 made of copper is removed by quick etching with a sulfuric acid-hydrogen peroxide etching solution, and the formation of the second wiring pattern 11 is completed.

Here, the effect of the second electrolytic plating solution used for the second wiring pattern 11 will be described in detail. The wiring pattern formed on the substrate surface generally has a different pattern line width and pattern density, and there are a sparse part and a dense part in the plated part. It was important to develop a plating solution that hardly affected the density of this pattern. In the present invention, as an evaluation of plating thickness variation due to pattern density, so-called uniform electrodeposition, copper plating is performed using a hull cell plate while energizing under a current stirring condition of total current 2A, plating time 20 minutes. Measure the film thickness at 2.5 cm, 3.5 cm, 6.0 cm, and 8.5 cm from the left end (high current end) (FIG. 3) using a film thickness meter, and vary based on the Field formula shown below. The uniform electrodeposition ratio T (%) between two points was calculated. The combination between two different points is a combination of 2.5 cm / 8.5 cm → P13.3
In combination of 3.5cm / 8.5cm → P10,
The combination of 6.0 cm / 8.5 cm was set as P4.4.

In addition, the current densities at positions 2.5 cm, 3.5 cm, 6.0 cm, and 8.5 cm from the left end of the Hull cell plate are 6 A / dm ² , 4.5 A / dm ² , 2 A / dm ² , 0, respectively. .45 A / dm ² .

(Field expression)
T (%) = 100 · (P−M) / (P + M−2)
T: Uniform electrodeposition P: Primary current distribution between two points M: Plating film thickness ratio between two points (However, the distribution of the primary current density on the cathode of the hull cell is i = I * (5.10− 5.24 LogL) i: current density (A / dm ² ), I: total current (A), L: distance from the high current density side end (cm), between two points by a predetermined combination Is a numerical value of the primary current density ratio P (P13.3, P10, P4.4) at each position of 2.5 cm, 3.5 cm, and 6.0 cm, and the plating film at the measurement point by the combination The thickness ratio is a value of M for each.

  (Table 1) shows the test results of the throwing power in P13.3, P10, and P4.4.

  Theoretically, in the primary current distribution ratio P, numerical values are improved in the order of P4.4 <P10 <P13.3, and the uniform electrodeposition can be evaluated for each fixed P value between two points. P13.3 is uniformity in the high current portion and low current portion, P10 is evaluation in the middle current portion and low current portion, and P4.4 is uniformity evaluation in the low current portion. The larger the value of the throwing power T (%), the better.

  The results are shown in (Table 1). When compared with P13.3, as Example 1, a copper sulfate plating solution containing copper sulfate pentahydrate 70 g / L, sulfuric acid 200 g / L, and chloride ions 50 mg / L, The uniform electrodeposition was 70.3%. As Example 2, a copper sulfate plating solution containing 100 g / L of copper sulfate pentahydrate, 180 g / L of sulfuric acid, and 50 mg / L of chloride ions had a uniform electrodeposition of 67. As a comparative example, the copper sulfate plating solution containing copper sulfate pentahydrate 200 g / L, sulfuric acid 25 g / L, and chloride ion 15 mg / L was 35.14% as a comparative example.

  As a general guideline for throwing power, it is said that T> 40% is good, about 60% is excellent, and 70% or more is said to be an extremely excellent numerical value.

  In other words, even if the pattern density of the wiring pattern is different, if a copper sulfate plating solution with a low copper ion concentration and a high sulfuric acid concentration is used, the influence of the sparse and dense portions of the wiring pattern can be reduced and a fine wiring pattern can be formed it can.

  Furthermore, by implementing FIG. 1 and FIG. 2 again on the surface layer including the second wiring pattern 11, desired third and fourth wiring patterns (not shown) can be increased. A high-density multilayer printed wiring board can be manufactured.

  As described above, as shown in the method for manufacturing a wiring board according to the present invention, the via portion is first filled with copper with a via fill plating solution, and then a pattern is formed twice with a pattern plating solution. When performing plating twice, it has a feature in the method of forming a plating resist in which parts other than the via part are masked with a plating resist and only the via part is plated. Further, by constructing two types of resists having different properties, the matching between the via and the resist mask can be perfected.

  That is, after forming a seed layer on the substrate surface, an alkali peeling type plating resist is formed, and then a heat peeling type resist is formed, and then a blind via is formed on the substrate from the two layers of resist with a laser or the like. . Thereafter, a seed layer is formed on the resist surface and inside the via by electroless copper plating or the like, and then the resist on the surface layer is peeled off by heating to perform plating on the via portion. At this time, the current concentrates in the via part and the plating deposition rate increases, but since there is no plating pattern in the periphery, the copper ion is consumed only in the via part, and the copper ion is in a richer state than when there is a pattern. It was found that copper ions were sufficiently supplied and high-speed plating was possible. Next, pattern plating can be performed by a semi-additive process by peeling off the lower insulating layer with an alkaline peeling solution. As a result, the via portion was filled with copper at a high speed, and plating that was advantageous for pattern density was made possible.

  As described above, since the method for manufacturing a wiring board according to the present invention can perform electrolytic plating with a uniform plating film thickness regardless of the density of the pattern density, a fine pattern such as L / S = 25/25 μm. In addition, the blind via hole for interlayer connection in the build-up substrate can be filled with copper, which is useful as a method for manufacturing a wiring substrate for various electronic devices such as semiconductor packages and communication devices.

Process drawing which shows the manufacturing method of the wiring board in embodiment of this invention Process drawing which shows the manufacturing method of the wiring board in embodiment of this invention The figure which shows the hull cell board | substrate for uniform electrodeposition evaluation in embodiment of this invention, and a measurement place

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st wiring pattern 2 Core board 3 Seed layer 4 Insulating resin layer 5 Photoresist (lower insulating layer)
6 Heat release tape (surface insulation layer)
7 Blind via hole 8 Electroless copper plating layer 9 Hole filling plating layer 10 Plating resist 11 Second wiring pattern

Claims (6)

A step of forming an insulating resin layer on the surface layer of the core substrate on which the first wiring pattern is formed; a step of forming a seed layer on the surface of the resin layer; A step of forming a plating insulating layer, a step of forming a heat-resistant plating-resistant insulating layer as an upper insulating layer, and a blind via hole extending from the surface of the two insulating layers to the first wiring pattern A step of forming an electroless copper plating layer after applying a catalyst to the surface of the insulating layer and the blind via hole, a step of peeling an upper insulating layer of the two types of plating-resistant insulating layers, A first electroplating step of supplying power from the seed layer and filling the inside of the blind via hole portion by electrolytic copper plating and peeling off the lower insulating layer A step of forming a plating resist layer in accordance with the second wiring pattern formed on the seed layer, and a step of forming power supply from the seed layer and forming the second wiring pattern by electrolytic copper plating. 2. A method of manufacturing a wiring board, comprising: an electrolytic plating step of 2, a step of removing the plating resist layer, and a step of etching away the seed layer immediately below the plating resist layer. 2. The wiring board according to claim 1, wherein the seed layer is formed using any one of a copper foil, an electroless plating + electrolytic plating layer, an electroless plating layer, a vacuum deposition film, and a sputter film. Production method. A plating solution containing copper sulfate pentahydrate 160 to 250 g / L, sulfuric acid 15 to 80 g / L, and chloride ions 20 to 70 mg / L in the first electrolytic copper plating step, sulfuric acid in the second electrolytic copper plating step The method for producing a wiring board according to claim 1, wherein a plating solution containing copper pentahydrate 50 to 100 g / L, sulfuric acid 160 to 220 g / L, and chlorine ions 20 to 70 mg / L is used. 2. The method of manufacturing a wiring board according to claim 1, wherein a laser is used to form the blind via hole. The method for manufacturing a wiring board according to claim 1, wherein a seed layer for depositing a plating film is formed on a peripheral portion of the board. The method for manufacturing a wiring board according to claim 1, wherein the substrate holding jig has a plating deposition portion.

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