JP2833642B2 - Multilayer wiring board and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board and a method of manufacturing the same, and more particularly, to a miniaturized high-density multilayer wiring board having a small area loss.

[0002]

2. Description of the Related Art Generally, a multilayer wiring board is manufactured as follows. First, a single-sided wiring board is formed by a photochemical etching method, and it is prepreg (resin P).
REimPREGnated glass clot
h) Bonding using materials to form several stacked substrates. Here, the prepreg material is a bonding material in which a cloth woven of glass fiber is impregnated with a semi-cured epoxy resin. Since it is semi-cured (referred to as B stage), it has adhesiveness and is often used for stacking multilayer wiring boards.
Mainly polyimide prepregs and epoxy prepregs.

[0003] Thereafter, the stacked layers are electrically connected. That is, a through hole is formed in a portion of each layer to be electrically connected by a drill, and the through hole is plated with copper to make it electrically conductive, whereby a multilayer wiring board is manufactured.

In recent years, the terminal pitch has been narrowed in order to reduce the size of LSI packages.
The density of the multilayer wiring board manufactured as described above is improving year by year. In addition, a wiring board used for mounting a small-pitch small package is required not only to reduce the terminal pitch but also to reduce the interval between the LSI packages. This is because it is difficult to reduce the size of the entire electronic device by merely reducing the size of the LSI package to be mounted, and thus it is necessary to further reduce the size of the wiring board. A semiconductor device mounted on such a small wiring board is also called a semiconductor module.

[0005]

However, in the above manufacturing method, since the through holes are formed in the final stage, the number of the through holes increases, and the effective area of the substrate used for wiring routing is substantially reduced. Yes (area loss)
There is a problem. This is because, for example, when wiring the fourth layer of the substrate, if the first layer and the second layer are connected, through holes are also opened in the third and fourth layers that do not require connection. This becomes more problematic as the number of layers of the substrate increases.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a multilayer wiring board and a method of manufacturing the same, which can reduce the area loss of a double-sided wiring board by through holes and can simultaneously perform mechanical and electrical bonding between the double-sided wiring boards. To provide.

[0007]

According to the present invention, there is provided an Au-S for mechanically and electrically joining a plurality of wiring boards having wiring layers on both sides to solve the above-mentioned problems.
have a n junction layer, the Au-Sn bonding layer eutectic 217
Formed by Au-Sn junction method using
Au-Sn eutectic containing 60 to 90% by weight of Sn
Provided is a multilayer wiring board comprising an alloy .

In addition, a prepreg (Resin Prei) made by impregnating a polyimide woven cloth made of glass fiber on the wiring board is used.
mpregnated Glass Cloth), Au-S
In particular, a plurality of n-junction layers are provided on an outer peripheral portion of a bonding surface of a wiring board having wiring layers on both surfaces, and mechanically bond the plurality of wiring boards to each other. We decided to provide a chrome-plated copper plate on the laminated surface
Is also good .

In the present invention, wiring layers are provided on both surfaces.
A step of individually manufacturing a plurality of wiring boards having
The wiring substrate is mechanically and electrically bonded to form a multilayer by using an Au-Sn bonding method using a eutectic melting point of 217 ° C. , and each bonding portion contains 60 to 90% by weight of Sn.
There is provided a method for manufacturing a multilayer wiring board, comprising a step of forming an Au-Sn eutectic alloy layer .

Further, the present invention provides a method of manufacturing a plurality of wiring boards each having a wiring layer on both sides, a step of forming an Au layer on a wiring pattern of a plurality of wiring boards, and a step of bonding. Forming a Sn layer on a predetermined portion of the Au layer formed on the joint surface of one of the wiring substrates, and using a eutectic melting point of 217 ° C. by overlapping a plurality of wiring substrates .
By using the Au-Sn bonding method, it is mechanically and electrically bonded to form a multilayer, and each bonding portion has a weight of 60 to 90%.
% Of Sn, the method comprising the step of forming an Au-Sn eutectic alloy layer containing Sn .

The Au layer and the Sn layer can be formed by plating, and the Sn layer is a paste containing Au─Sn alloy powder, and a Au 含有 Sn alloy is a paste containing Au and Sn powder. It can be formed of foil or Sn foil. Further, the composition of the Au @ Sn junction layer is preferably 1 to 40% by weight Au @ Sn when the wiring substrate is an organic material, and 82% by weight Au @% when the wiring substrate is a ceramic.
Sn can be used. Further, the joining conditions are 1 to 40% by weight.
230-250 ° C., 82% by weight when using the low Au side region in the Au─Sn phase diagram such as Au─Sn
320 when using a high Au region such as Au @ Sn
~ 340 ° C is preferred. The bonding time depends on the material of the substrate used,
The optimum time varies depending on the thickness, the number of layers, and the like.

[0012]

Embodiment 1 Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a multilayer wiring board according to the present embodiment. This multilayer wiring board includes three double-sided wiring boards 1. Each double-sided wiring board 1 has a wiring pattern on the front surface and the back surface, and both wiring patterns are electrically connected by a through-hole copper plating 6 provided on an inner surface of a through-hole formed in the wiring substrate. Then, in the multilayer wiring board, the double-sided wiring board 1 is laminated,
It has a surface wiring pattern 2, an interlayer wiring pattern 3, a back wiring pattern 4, and an Au-Sn bonding layer 5 for mechanically and electrically bonding each double-sided wiring board 1.

Hereinafter, a method for manufacturing the multilayer wiring board will be described. First, a plurality of double-sided wiring boards 1 are individually manufactured. Here, the material used as the initial material of the double-sided wiring board may be any of a copper-pasted glass epoxy board, a copper-pasted glass foliimide board, and a thick-film wiring printed ceramic board.

The surface wiring pattern 2 of the double-sided wiring board 1 placed on the top of the multilayer wiring board is, for example, 0.3 mm so that a narrow pitch LSI package can be mounted.
Fine terminals having a pitch of 300 mm and equivalent to 300 mm pitch, and wiring routes for connecting these terminals are formed. Note that the wiring routing is not sufficient with the surface wiring pattern 2 alone, and therefore is further routed using the interlayer wiring pattern 3.
Double-sided wiring board 1 other than double-sided wiring board 1 placed on top
In the same manner, a wiring pattern is formed. The surface wiring pattern 2 and the interlayer wiring pattern 3 are provided with through-holes at necessary portions of the double-sided wiring board 1, and plated with through-hole copper plating 6 on the surface in the through-holes. The connection is made electrically.

Next, the double-sided wiring boards 1 manufactured as described above are joined as follows. FIG. 2 is an enlarged view of a joint portion of the multilayer wiring board. This figure 2
Although not shown in the drawings, Au plating having a thickness of 0.1 to 1.0 μm is previously formed on each wiring pattern of each double-sided wiring board 1 by using both electroless plating and electroplating. It has been subjected. This Au plating is frequently used for ultra-high-density module substrates for the purpose of improving the corrosion resistance of fine copper wiring patterns. Au plating is used as an optimal surface treatment method for mounting an LSI on the surface wiring pattern 3 by a wire bonding method and for connecting the LSI by a TAB method.

Then, Sn plating is partially applied on the Au plating on one of the bonding surfaces of the double-sided wiring board 1 to form a Sn plating layer 9. For the Sn plating, any method such as electric Sn plating or chemical Sn plating may be used, and a plating resist is applied to a plating unnecessary portion, or a permanent solder resist 8 is applied (a dam for stopping the flow of the brazing filler metal). ) Can be partially plated. In the case of electroless Sn plating, it is possible to prevent the electroless Sn from adhering to the application surface by applying the resist after the activation of palladium. Further, in the case of electric Sn plating, it is necessary to attach a plating electrode wiring for flowing a current.

After the bonding surface of the double-sided wiring board 1 is processed as described above, the two-sided wiring boards 1 are heated and pressurized to form Au─.
Joining is performed using a Sn eutectic alloy method. However, at this time,
There are the following problems. That is, most of the multilayer wiring boards are made of the above-described glass epoxy, glass foliimide or the like, and thus have a problem that they are very weak to heat. Therefore, if the bonding is not performed at a low temperature, the material of the substrate is deteriorated at the bonding temperature, for example, peeling of the copper wiring pattern due to softening of the substrate, peeling of the through-hole copper plating, and thermal deterioration of the substrate itself.

Therefore, in this embodiment, the double-sided wiring board 1 is joined as described below. FIG. 3 is an equilibrium diagram for explaining the substrate bonding principle of the present embodiment. As shown in FIG. 3, the state system of Au @ Sn has Sn of about 18% by weight, about 58% by weight and about 85% by weight.
Eutectic point at 3 points by weight, especially 18% by weight and 8% by weight.
Two points of 5% by weight are prominent. In general, the composition used for sealing a ceramic package or the like is when Sn is 18% by weight, and a sealing temperature of about 350 ° C. is selected. That is, the eutectic melting point at the point of Sn 18% by weight is as follows:
Since the temperature is 280 ° C., the sealing is completed at a higher temperature. Such a composition is often used in the case of a material having high heat resistance, such as ceramics, because it has a characteristic of high heat resistance after connection and sealing.

However, when the above-mentioned organic material such as glass epoxy or polyimide is used, the composition of 18% by weight of Sn cannot be used for the multilayer wiring board of this embodiment because of its weakness to heat as described above. This is because the softening point of the epoxy resin differs depending on the type of the hardening material, but is 150 ° C. for the one having the highest heat deformation temperature, and 250 ° C. for Kapton, Iupirex, etc. for polyimide resin, while Sn 18% by weight This is because the eutectic melting point is 280 ° C. when the composition is used, so that the bonding temperature becomes 250 ° C. or higher, and the above-described deterioration occurs in the double-sided wiring board 1.

On the other hand, in the case of the composition of Sn 85% by weight, the eutectic melting point is 217 ° C. This temperature is 15 ° C. lower than the melting point of pure tin, 232 ° C. The characteristics of the bonding method using this composition include that bonding can be performed at a temperature lower than the softening temperature of polyimide of 250 ° C. and that the cost is low because the composition ratio of Au is low. A composite lead frame using this composition is disclosed in Japanese Patent Application No. 4-106353.

Therefore, a method of bonding the double-sided wiring board 1 using a composition of 85% by weight of Sn will be described. For this joining, a joining jig such as a heat tool or a hot plate press is used, and the two-sided wiring boards 1 to be joined are overlapped and heated and pressed. The heating set temperature of this joining jig is 250 ° C.
The double-sided wiring board 1 is pressed at a pressure equivalent to 0 kg / cm ² . When the superposed double-sided wiring board 1 is heated and the junction temperature reaches 217 ° C., the phase of the 85% by weight Sn of the interdiffusion layer formed based on the pressure starts to melt. Since the bonding jig is set at a maximum of 250 ° C., the temperature further rises and melting of the Sn plating itself starts. Since the melting of the Sn plating is rapid, it reacts quickly with the Au plating phase to form an Au─Sn alloy layer. Also in this case, the reaction of the combination of Sn 85% by weight-Au having the lowest melting point and the eutectic composition is proceeding with the highest priority. At this time, if the amount of Sn and Au is exactly the composition of Sn 85% by weight / Au as the basis weight of the joint, the composition when finally solidified is almost the same as this composition.

As described above, the Au @ Sn composition which has already started melting and has a low eutectic melting point is extruded out of the system at the joining boundary by the pressing of the joining jig. Therefore, after the two-sided wiring boards are joined together, only the high melting point composition remains at the joining interface. Even when residual Sn not participating in the reaction remains, it is similarly pushed out of the system because of its low melting point and high fluidity. Therefore, the boundary of the bonding portion of the double-sided wiring board has a composition having a high melting point, and the portion flowing out to the wall of the bonding portion has a composition having a low melting point.
Is formed. The composition having a low melting point extruded out of the system is shown in FIG. 1 as a low melting point Au─Sn bonding layer 7. However, a clear boundary does not exist between the high melting point composition and the low melting point composition as described above.

Here, based on the above description, the preferable Au 好 ま し い in the present embodiment is taken into consideration while considering the requirement of heat resistance.
The range of the composition of the Sn bonding layer 5 is defined as Sn 60 to 90% by weight ΔA.
u. In other words, the Au─Sn bonding layer 5 of the double-sided wiring board is formed by the heating and pressurization by the bonding jig as a total composition of the high melting point bonding layer at the bonding interface and the low melting point bonding layer around the bonding layer. This is because the amount is controlled to be% by weight. Therefore, for example, a combination of plating compositions of Sn 60% by weight @ Au can also be realized at a joining temperature of 250 ° C. Also, in the case of Sn 90% by weight @ Au,
High heat resistance can be obtained at the same joining temperature.

On the basis of the manufacturing method described above, Examples 1 to 9 described below were obtained. Example 1 A six-layer wiring board (three double-sided wiring boards 1) as shown in FIG. 1 was manufactured using a 100 mm square polyimide base material having copper foils bonded on both sides. The copper-clad polyimide plate is formed by laminating a 18-μm-thick copper foil on both sides of a B-stage (semi-cured) polyimide adhesive film of 100 μm.
A hole of 5φ was opened by a punching die, and a through-hole copper plating 6 having a thickness of 10 μm was applied to the side wall of the hole.
The through-hole copper plating 6 is made by electroless copper plating 1.0 μm.
After that, electrolytic copper plating was applied to a thickness of 9 μm to complete the plating. Since the plating mask on the surface is omitted, copper plating of 10 μm is applied to the entire surface (panel plating method). Next, a photoresist was applied to the surface of the substrate, exposed, developed, and etched to form wiring patterns on both the front and back surfaces of the substrate. The other two double-sided wiring boards 1 were formed in the same manner.

Next, on the copper wiring pattern of the double-sided wiring board 1, Ni base plating 0.5 μm, Au plating 0.5 μm
m. Further, an epoxy solder resist 8 is formed on the entire surface of the substrate, leaving a bonding surface for bonding the double-sided wiring boards 1 to each other.
Was applied by a screen printing method so as to have a thickness of 10 μm. The purpose of this application is to prevent a short circuit due to contact of a pattern other than a joint portion and to prevent a pattern short circuit due to scattering of molten Au @ Sn. The state of this joint is shown in FIG. After the application of the solder resist, 10 μm electric Sn plating was applied to a portion of the wiring pattern requiring an opening. The same processing was performed on the other two double-sided wiring boards 1.

Thereafter, the three double-sided wiring boards 1 were overlaid using positioning holes (not shown) and inserted into a hot vacuum press. The reason why the vacuum press is used is to prevent oxidation of Sn before joining. Basically, in this bonding method, it is important to prevent the surface oxidation because the flux (flux 9 is not used. It is not necessary to use the flux as long as the surface oxidation is prevented and the double-sided wiring board 1 is bonded. Therefore, cleaning after bonding is not required, and resistance to migration and the like is improved, and high reliability is obtained.

The press plate temperature at the time of joining was 250 ° C. In addition, the temperature of the bonding portion was 230 ° C. as an actually measured value at a certain point in the second stage. Since the press plate used is of a double-sided heating type, heat is applied from above and below the double-sided wiring board 1. Since the thermal conductivity of the polyimide is low, but is as thin as 100 μm, and the thermal conductivity of the copper foil and the through-hole copper plating 6 is high, the heating / pressing time for bonding is 1 minute. The pressure at the time of joining is 30 kg / cm ² .

After one minute, the heater of the hot press plate is turned off.
And the cooling is started. Further, the temperature of the hot plate is cooled to 200 ° C. by blowing cooling air for one minute simultaneously with turning off the heater. At this time, the pressing pressure was released to obtain a multilayer wiring board.

Example 2 In the case of Example 1, the thickness of the Sn plating was reduced to 5 μm. At this time, the basis weight of Sn and Au is Sn 30% by weight @ Au. The bonding of the double-sided wiring board 1 was performed using the same method as in Example 1 to obtain a multilayer wiring board.

Example 3 A prepreg made of glass cloth impregnated with polyimide was used for the double-sided wiring board 1. The substrate was manufactured by impregnating a glass cloth with a polyimide varnish, evaporating the solvent to obtain a semi-cured B-stage prepreg, and then bonding copper foil on both sides using a hot press. After that, a multilayer wiring board was obtained by using the same method as in the first embodiment. The third embodiment is characterized in that since the double-sided wiring board 1 contains glass, a multilayer wiring board having a high bending strength of the board can be obtained.

[Embodiment 4] Similar to Embodiment 1 described above, except that the Au─Sn bonding layer 5, which is not used for electrical connection, is formed on the bonding surface of the double-sided wiring board 1, especially around the bonding surface.
A plurality of dummy pads were provided. Since the dummy pad is not used for electrical connection, it can be arbitrarily provided on a substrate having no wiring pattern. As a result, a multilayer wiring board with increased bonding strength can be obtained.

Fifth Embodiment In the case of the first embodiment, a 0.3 mm-thick copper plate plated with 5 μm of chromium is adhered to the back side in order to enhance the heat radiation of the substrate. A 50 μm-thick polyimide-based adhesive film was used for attachment.

[Embodiment 6] Au─ in Embodiment 1 is used.
As the Sn bonding method, a method of printing a paste containing Au @ Sn alloy powder and performing bonding in a similar manner was employed.

[Seventh Embodiment] AuＡ in the first embodiment is used.
As the Sn bonding method, a method of printing a paste containing Au and Sn powder and performing bonding in a similar manner was employed.

[Embodiment 8] Au─ in Embodiment 1 is used.
As the Sn bonding method, a method was employed in which an Au @ Sn alloy foil was attached to the bonding portion and bonded.

[Embodiment 9] Au─ in Embodiment 1 is used.
As the Sn bonding method, a method in which a Sn foil was attached and bonded was adopted.

According to the present embodiment as described above, the following effects can be obtained. First, since a through hole is provided for each double-sided wiring board 1, the area loss of the wiring pattern is reduced, and the size of the board is reduced. Second,
Since the bonding between the layers is performed by Au─Sn bonding, mechanical and electrical bonding can be performed simultaneously. Third
In addition, the multilayering process using the insulating adhesive film (prepreg) described in the section of the prior art is not required. Fourth, a step of opening a final through hole and a step of plating the through hole are unnecessary. Fifth, since a through hole is provided for each layer, through hole processing with a small diameter is possible, and the area loss is reduced from this point as well. Because
This is because, when a through hole is finally formed as in the conventional case, the thickness of the entire substrate is increased due to the multilayered substrate, and a thick drill is required. For example, the through hole in the present embodiment is 0.3φ, but in the conventional case it is 0.5φ. Sixth, each layer is reel-to-reel continuous FP
It can be manufactured by C or TAB line, and a fine pattern can be formed. On the other hand, in the conventional case, the pattern of the outermost layer is formed after laminating the double-sided wiring boards, through holes are formed, and plated through holes.
A fine pattern cannot be formed. For example, FPC or T
The resolution of the AB line is 100 μm pitch, while the resolution of the printed circuit board is 200 μm pitch.

[0038]

As described above, according to the multilayer wiring board and the method of manufacturing the same of the present invention, the double-sided wiring boards are made to have a eutectic melting point.
Au-Sn junction using 217 ° C
Even if an organic material is used for the wiring board,
The wiring board is not deteriorated, the area loss of the double-sided wiring board is reduced, and the mechanical and electrical bonding between the double-sided wiring boards can be performed simultaneously.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a sectional view showing one embodiment of the present invention.

FIG. 3 is an equilibrium diagram of an Au @ Sn system showing one embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Double-sided wiring board 2 Surface wiring pattern 3 Interlayer wiring pattern 4 Back wiring pattern 5 Au @ Sn bonding layer 6 Through-hole copper plating 7 Au @ Sn low-melting-point bonding layer 8 Solder resist 9 Sn plating layer

Claims (11)

(57) [Claims] 1. A multi-layer wiring board for mounting a semiconductor device such as an LSI in which a plurality of wiring boards having wiring layers on both sides are stacked, for mechanically and electrically joining the plurality of wiring boards to each other. have a Au-Sn bonding layer, the Au
-Sn bonding layer is made of Au-Sn using a eutectic melting point of 217 ° C.
It is formed by a joining method, and has a weight of 60 to 90
A multilayer wiring board comprising an Au-Sn eutectic alloy containing% Sn . 2. The method according to claim 1, wherein the wiring board is a cloth woven of glass fiber.
Prepreg impregnated with polyimide (Resin Preimpregn
2. The multilayer wiring board according to claim 1, comprising an ated glass cloth.
Board. 3. The semiconductor device according to claim 2, wherein the Au—Sn junction layer is formed of a wiring.
A plurality of wirings are provided on the outer peripheral portion of the bonding surface of the substrate, and
2. The multilayer wiring according to claim 1, wherein the wiring substrates are mechanically joined to each other.
substrate. 4. The wiring board according to claim 1, wherein the wiring board is an uppermost layer or a lowermost layer.
2. A chromium-plated copper plate is provided on the non-laminated surface.
The multilayer wiring board as described in the above. 5. A plurality of wiring boards each having a wiring layer on both sides.
Separately manufacturing a plurality of wiring boards;
By using the Au-Sn junction method using 17 ° C,
Mechanical and electrical bonding to form multiple layers
Au-Sn eutectic alloy layer containing 60 to 90% by weight of Sn
Characterized by having a step of forming a multilayer wiring board
Manufacturing method. 6. A plurality of wiring boards each having a wiring layer on both sides.
A separate manufacturing process, and a wiring pattern of the plurality of wiring boards;
Forming an Au layer on the substrate,
Before being formed on the bonding surface of one of the wiring boards of the board
Forming a Sn layer on a predetermined portion of the Au layer;
Utilizing eutectic melting point of 217 ° C by stacking multiple wiring boards
By using the Au-Sn junction method, mechanical and
It is electrically joined to form a multilayer , and each joint is 60 to 90
Forming Au-Sn eutectic alloy layer containing wt% Sn
A method for manufacturing a multilayer wiring board, comprising: 7. The Au layer and the Sn layer are formed by plating.
7. The method for manufacturing a multilayer wiring board according to claim 6, wherein the method is performed. 8. The Sn layer contains an Au—Sn alloy powder.
7. The production of a multilayer wiring board according to claim 6, wherein the paste is made of a paste.
Construction method. 9. The Sn layer contains Au and Sn powder.
7. The production of a multilayer wiring board according to claim 6, wherein the paste is made of a paste.
Method. 10. The Sn layer is made of an Au—Sn alloy foil.
The method for manufacturing a multilayer wiring board according to claim 6. 11. The method according to claim 6, wherein said Sn layer is made of Sn foil.
Manufacturing method of the multilayer wiring board described above.