JPH11163522A - Multilayer wiring boar and its manufacture - Google Patents

Multilayer wiring boar and its manufacture

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Publication number
JPH11163522A
JPH11163522A JP26862198A JP26862198A JPH11163522A JP H11163522 A JPH11163522 A JP H11163522A JP 26862198 A JP26862198 A JP 26862198A JP 26862198 A JP26862198 A JP 26862198A JP H11163522 A JPH11163522 A JP H11163522A
Authority
JP
Japan
Prior art keywords
double
wiring board
multilayer wiring
sided circuit
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26862198A
Other languages
Japanese (ja)
Inventor
Yasushi Inoue
泰史 井上
Masakazu Sugimoto
正和 杉本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP26862198A priority Critical patent/JPH11163522A/en
Publication of JPH11163522A publication Critical patent/JPH11163522A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer wiring board whose manufacture process is simple and connection reliability is high. SOLUTION: A manufacturing method is composed of a process of preparing a plurality of double-side circuit boards 1, wherein circuit 3 are provided on the both front and rear planes of an insulating layer 2 composed of polyimide resin, and the circuits 3 are electrically connected via a through hole; a process of preparing an adhesive sheet 8 which has a hole at a position corresponding to the prescribed position of the circuit 3 of the double-side board 1; a process of tentatively adhering the adhesive sheet 8 on the double-side circuit board 1; a process of filling opened part of each adhesive sheet 8 with solder paste, by printing after tentatively adhering the adhesive sheet 8, and melting the solder paste with heat to form a solder bump 9; and a process of staking each double-side circuit board 1, after forming the solder bump 9 and applying heat and pressure for entire integration.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子等を搭
載するのに適した多層配線基板およびその製造方法に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board suitable for mounting a semiconductor element or the like and a method for manufacturing the same.

【0002】[0002]

【従来の技術】近年の電子機器の小型化,高性能化に伴
い、電子機器を構成する半導体装置およびこれを実装す
る多層プリント配線基板には、小型薄型化,高性能化,
高信頼性が要求されている。これらの要求を受けて、実
装方法はピン挿入型パッケージから表面実装型パッケー
ジへと移行してきており、最近では半導体素子を直接プ
リント基板に実装するベアチップ実装と呼ばれる実装方
法が研究されている。また、半導体素子の多ピン化に伴
い、これを搭載する基板の多層化の必要性が増してい
る。この多層化の方法として、基体の片面もしくは両面
に、感光性樹脂を用いた絶縁層と、めっきや蒸着により
形成した導体層を交互に積み重ねたビルトアップ方式の
多層配線基板が提案されている。ところが、このもので
は、製造工程が複雑で、かつ工程数が多いこと、しかも
歩留りが低いことや納期がかかること等の問題があっ
た。また、ガラスエポキシ片面銅張り積層板の片面(銅
張り面)に電導性ペーストをディスペンサー等により突
起として形成し、接着シートと銅箔を重ねて加圧し、そ
れを繰り返すことにより多層化する方法も提案されてい
る(特開平8−288649号公報)。しかしながら、
このものでは、接続の信頼性,接続抵抗等の面に問題が
あるうえ、ファイン回路への応用が困難であり、しかも
多層化するために層数の分だけプレスを繰り返す必要が
あり、製造に時間がかかる等の種々の問題があった。
2. Description of the Related Art With the recent miniaturization and high performance of electronic devices, semiconductor devices constituting electronic devices and multilayer printed wiring boards on which the electronic devices are mounted have been reduced in size and thickness and improved in performance.
High reliability is required. In response to these demands, the mounting method has shifted from a pin insertion type package to a surface mount type package. Recently, a mounting method called bare chip mounting, in which a semiconductor element is directly mounted on a printed circuit board, has been studied. Further, with the increase in the number of pins of the semiconductor element, the necessity of increasing the number of layers of the substrate on which the semiconductor element is mounted is increasing. As a method of multi-layering, a built-up type multilayer wiring board has been proposed in which an insulating layer using a photosensitive resin and a conductor layer formed by plating or vapor deposition are alternately stacked on one or both sides of a base. However, this method has problems that the manufacturing process is complicated, the number of steps is large, the yield is low, and the delivery time is long. Alternatively, a method of forming a conductive paste on one surface (copper-coated surface) of a glass epoxy single-sided copper-clad laminate as a projection using a dispenser or the like, stacking an adhesive sheet and a copper foil, applying pressure, and repeating the process to form a multilayer structure. It has been proposed (JP-A-8-288649). However,
This method has problems in connection reliability, connection resistance, etc., and is difficult to apply to fine circuits. In addition, it is necessary to repeat pressing for the number of layers in order to increase the number of layers. There were various problems such as a long time.

【0003】一方、ベアチップ実装では、熱膨張係数:
3〜4ppm/℃のシリコンチップを熱膨張係数:10
〜20ppm/℃のプリント基板上に直接接着剤を介し
て接着するため、両者の熱膨張の差により応力がかか
り、接続信頼性が低下するという問題が生じている。ま
た、上記応力は接着剤にクラックを生じさせて耐湿性を
低下させる等の問題をも引き起こしている。このような
応力を緩和するために、接着剤の弾性率を下げて応力の
拡散効果を図る方法等も実施されているが、これらの方
法によっても、接続信頼性を充分に確保することができ
ず、さらに高い接続信頼性を確保するには、基体自体の
熱膨張係数を下げることが必要不可欠となっている。そ
こで、これを解決するものとして、Ni−Fe合金を基
体とし、その上に絶縁層と配線導体を交互に積み重ねた
多層配線板もしくはこれの表面層に半田パッドを写真食
刻法により形成して加熱加圧一体化した多層配線板が提
案されている(特開昭61−212096号公報)。
On the other hand, in the bare chip mounting, the thermal expansion coefficient:
A silicon chip of 3 to 4 ppm / ° C. has a coefficient of thermal expansion of 10
Since the printed circuit board is directly bonded to the printed board at 2020 ppm / ° C. via an adhesive, a stress is applied due to a difference in thermal expansion between the two, causing a problem that connection reliability is reduced. In addition, the above-mentioned stress also causes problems such as causing cracks in the adhesive and reducing moisture resistance. In order to alleviate such stress, a method of lowering the elastic modulus of the adhesive to achieve the effect of diffusing the stress has been carried out. However, even with these methods, sufficient connection reliability can be ensured. In order to ensure even higher connection reliability, it is essential to lower the thermal expansion coefficient of the base itself. In order to solve this problem, a Ni—Fe alloy is used as a base material, and a multilayer wiring board in which insulating layers and wiring conductors are alternately stacked thereon, or solder pads are formed on a surface layer of the multilayer wiring board by photolithography. A multilayer wiring board integrated by heating and pressurizing has been proposed (JP-A-61-212096).

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このも
のでは、配線導体として銅を用いた場合に、この銅の弾
性率が絶縁層を構成するポリイミド樹脂の弾性率に比べ
て非常に大きいため、多層配線板全体の熱膨張率を半導
体素子を構成するシリコン並に低くすることは困難であ
った。しかも、蒸着法,スパッタリング法等の金属薄膜
形成技術を用いているため、生産性が低く、コスト高と
なる。また、半田パッドの形成も蒸着法,写真食刻法に
より行っているため、煩雑な工程が必要であった。
However, in this case, when copper is used as the wiring conductor, the elastic modulus of the copper is much larger than the elastic modulus of the polyimide resin forming the insulating layer. It has been difficult to reduce the coefficient of thermal expansion of the entire wiring board to as low as that of silicon constituting a semiconductor element. Moreover, since a metal thin film forming technique such as a vapor deposition method or a sputtering method is used, productivity is low and cost is high. In addition, since the formation of the solder pad is performed by a vapor deposition method or a photolithography method, a complicated process is required.

【0005】本発明は、このような事情に鑑みなされた
もので、製造工程が簡便で、接続信頼性が高い多層配線
基板およびその製造方法の提供をその目的とする。
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a multilayer wiring board having a simple manufacturing process and high connection reliability and a method of manufacturing the same.

【0006】[0006]

【課題を解決するための手段】上記の目的を達成するた
め、本発明は、有機高分子樹脂からなる絶縁層の両面に
配線導体が設けられこれら両配線導体がスルーホールで
電気的に接続された複数の両面回路基板がそれぞれ接着
剤層を介して積層一体化され、上記接着剤層には、これ
を挟む2つの両面回路基板の配線導体に当接する部分の
所定位置に孔が穿設され、上記穿孔部に半田製導電体が
設けられ、上記半田製導電体により上記2つの両面回路
基板の配線導体が電気的に接続されている多層配線基板
を第1の要旨とし、有機高分子樹脂からなる絶縁層の両
面に配線導体が設けられこれら両配線導体がスルーホー
ルで電気的に接続された複数の両面回路基板と、上記両
面回路基板の配線導体の所定部分に対応する位置に開孔
した接着シートとを準備する工程と、上記両面回路基板
に設けた配線導体の所定部分に上記接着シートの開孔部
を位置合わせした状態で上記両面回路基板に接着シート
を仮接着する工程と、接着シート仮接着後に各接着シー
トの開孔部に半田ペーストを充填し加熱溶融させて半田
バンプを形成する工程と、半田バンプ形成後に上記各両
面回路基板の配線導体が所定の電気的接続を行えるよう
位置合わせして上記各両面回路基板を積み重ね加熱加圧
して全体を一体化させる工程を備えている多層配線基板
の製造方法を第2の要旨とする。
In order to achieve the above-mentioned object, the present invention provides a wiring conductor provided on both sides of an insulating layer made of an organic polymer resin, and these wiring conductors are electrically connected through through holes. A plurality of double-sided circuit boards are laminated and integrated via an adhesive layer, respectively, and a hole is formed in the adhesive layer at a predetermined position of a portion in contact with the wiring conductor of the two double-sided circuit boards sandwiching the adhesive layer. A first aspect is a multilayer wiring board in which a solder conductor is provided in the perforated portion, and the wiring conductors of the two double-sided circuit boards are electrically connected by the solder conductor. Wiring conductors are provided on both surfaces of an insulating layer made of a plurality of double-sided circuit boards in which both wiring conductors are electrically connected by through holes, and holes are formed at positions corresponding to predetermined portions of the wiring conductors of the double-sided circuit board. Adhesive sheet and A step of preparing, and a step of temporarily bonding the adhesive sheet to the double-sided circuit board in a state where the opening of the adhesive sheet is aligned with a predetermined portion of the wiring conductor provided on the double-sided circuit board, and after the temporary bonding of the adhesive sheet. Filling the solder paste into the opening of each adhesive sheet and heating and melting to form solder bumps; and, after the formation of the solder bumps, align the wiring conductors of each of the double-sided circuit boards so that predetermined electrical connections can be made. A second gist of the present invention is a method for manufacturing a multilayer wiring board including a step of stacking the above-mentioned double-sided circuit boards, and heating and pressurizing to integrate the whole.

【0007】すなわち、本発明者らは、製造工程が簡便
で、接続信頼性が高い多層配線基板を得るため、一連の
研究を行った結果、上記の製造方法によると、多層配線
基板を簡便に製造することができ、しかも、得られた多
層配線基板は、その接続信頼性が高いことを見出し、本
発明に到達した。すなわち、本発明の方法では、両面回
路基板に接着シートを位置合わせして仮接着し、この接
着シートに開けた開孔部に半田バンプを形成したのち、
各両面回路基板位置合わせして積み重ね加熱加圧して全
体を一体化させているため、一回の加熱加圧により複数
の両面回路基板を一体化することができる。と同時に、
配線導体の層数が何層であっても、上記一回の加熱加圧
により各配線導体間の電気的接続が行える。しかも、各
両面回路基板にスルーホールを設けて各両面回路基板の
表裏両面の配線導体を電気的に接続しているため、スル
ーホールの位置,半田導電体の位置を任意に設定するこ
とにより各配線導体間の電気的接続を任意の位置で行う
ことができる。本発明において、「両面回路基板の配線
導体の所定部分に対応する位置に開孔した接着シートと
を準備する」とは、接着シートを両面回路基板上に載せ
たのち開孔する場合を含む意味である。
That is, the present inventors have conducted a series of studies in order to obtain a multilayer wiring board having a simple manufacturing process and high connection reliability. As a result, according to the above manufacturing method, the multilayer wiring board can be easily manufactured. The present inventors have found that the multilayer wiring board which can be manufactured and has high connection reliability is obtained, and arrived at the present invention. That is, in the method of the present invention, the adhesive sheet is aligned and temporarily bonded to the double-sided circuit board, and after the solder bumps are formed in the openings formed in the adhesive sheet,
Since the whole double-sided circuit boards are aligned and stacked and heated and pressed to integrate the whole, a plurality of double-sided circuit boards can be integrated by a single heating and pressing. At the same time
Regardless of the number of layers of the wiring conductor, electrical connection between the wiring conductors can be performed by the single heating and pressing. Moreover, since through-holes are provided in each double-sided circuit board to electrically connect the wiring conductors on the front and back surfaces of each double-sided circuit board, the position of the through-hole and the position of the solder conductor can be set arbitrarily. The electrical connection between the wiring conductors can be made at any position. In the present invention, “preparing an adhesive sheet that is opened at a position corresponding to a predetermined portion of a wiring conductor of a double-sided circuit board” includes a case where the adhesive sheet is placed on a double-sided circuit board and then opened. It is.

【0008】また、本発明において、上記絶縁層にNi
−Fe系合金箔,チタン箔もしくはセラミックス材料シ
ートが芯材として含まれている場合には、配線導体2層
に対して1層の割合でNi−Fe系合金箔,チタン箔も
しくはセラミックス材料シートからなる低熱膨張率の芯
材が含まれることになり、配線導体として銅を用いた場
合にも、多層基板全体の熱膨張率をシリコンに限りなく
近づけることが可能になる。このように、絶縁層にNi
−Fe系合金箔,チタン箔もしくはセラミックス材料シ
ートが芯材として含まれている場合には、熱膨張率を極
めて低くすることができるため、ベアチップ実装におい
ても、極めて高い接続信頼性を有する。
In the present invention, the insulating layer may be made of Ni.
-When an Fe-based alloy foil, a titanium foil, or a ceramic material sheet is included as a core material, a Ni-Fe-based alloy foil, a titanium foil, or a ceramic material sheet is used in a ratio of one layer to two wiring conductors. Since a core material having a low coefficient of thermal expansion is included, even when copper is used as a wiring conductor, the coefficient of thermal expansion of the entire multilayer substrate can be made as close as possible to silicon. Thus, the insulating layer is made of Ni
-When an Fe-based alloy foil, a titanium foil, or a ceramic material sheet is included as a core material, the coefficient of thermal expansion can be extremely reduced, so that extremely high connection reliability can be obtained even in bare chip mounting.

【0009】つぎに、本発明を詳しく説明する。Next, the present invention will be described in detail.

【0010】本発明の多層配線基板の製造方法には、有
機高分子材料からなる絶縁層と、この絶縁層の両面に設
けた配線導体とからなる両面回路基板、接着シート、お
よび半田ペーストが用いられる。
The method for manufacturing a multilayer wiring board of the present invention uses a double-sided circuit board comprising an insulating layer made of an organic polymer material and wiring conductors provided on both sides of the insulating layer, an adhesive sheet, and a solder paste. Can be

【0011】上記絶縁層を構成する有機高分子材料とし
ては、ポリイミド系樹脂が好適に用いられるが、これに
限定するものではなく、ポリエーテルイミド,ポリエー
テルサルフォン,エポキシ系樹脂,フェノール系樹脂,
フッ素系樹脂等が用いられる。また、配線導体を構成す
る金属材料としては、銅が好適に用いられるが、これに
限定するものではなく、金,銀等が用いられる。
As the organic polymer material constituting the insulating layer, a polyimide resin is preferably used, but is not limited thereto, and may be polyetherimide, polyether sulfone, epoxy resin, phenol resin. ,
A fluorine resin or the like is used. As a metal material constituting the wiring conductor, copper is preferably used, but not limited thereto, and gold, silver, or the like is used.

【0012】上記接着シートは積層一体化後に絶縁層と
なるため、これを構成する接着剤としては、耐熱性,電
気的特性等からポリイミド系接着剤またはその混合系接
着剤等が好ましいが、エポキシ系,ポリエーテルイミ
ド,フェノール系等を用いてもよい。接着シートの厚み
は、0.01〜1.0mmの範囲内に設定するのが好ま
しい。この範囲より小さいと、作業性が悪く、また、回
路間の凹凸やスルーホールを埋めることができない。一
方、この範囲より大きいと、半田ペーストをうまく孔に
充填させことが難しく、信頼性を低下させる原因とな
る。上記接着シートに孔を開ける手段としては、ドリル
やパンチ等従来の公知技術を用いることができる。
Since the above-mentioned adhesive sheet becomes an insulating layer after lamination and integration, the adhesive constituting the adhesive sheet is preferably a polyimide-based adhesive or a mixed adhesive thereof in view of heat resistance, electric characteristics and the like. System, polyetherimide, phenol, etc. may be used. The thickness of the adhesive sheet is preferably set in the range of 0.01 to 1.0 mm. If it is smaller than this range, workability is poor, and irregularities and through holes between circuits cannot be filled. On the other hand, if it is larger than this range, it is difficult to fill the hole with the solder paste well, which causes a decrease in reliability. As a means for making a hole in the adhesive sheet, a conventionally known technique such as a drill or a punch can be used.

【0013】上記半田ペーストは一般に市販されている
ものが用いられるが、半田粒子の粒径は100μm以
下、好ましくは50μm以下、さらに好ましくは20μ
m以下に設定される。また、半田組成は、特に限定され
ず、基板に求められる耐熱性に応じて選択すればよい。
積層後の半田バンプは対極電極に接触して導通される
が、必要であれば半田の融点以上に基板を加熱して金属
接合させてもよい。この金属接合は、加熱加圧による基
板の一体化と同時に行ってもよいし、一体化した後に再
度加熱して行ってもよい。
As the above-mentioned solder paste, a commercially available solder paste is used, and the particle size of the solder particles is 100 μm or less, preferably 50 μm or less, more preferably 20 μm or less.
m or less. The solder composition is not particularly limited, and may be selected according to the heat resistance required for the substrate.
The solder bumps after the lamination are brought into contact with the counter electrode to conduct, but if necessary, the substrate may be heated to a temperature higher than the melting point of the solder for metal bonding. The metal bonding may be performed simultaneously with the integration of the substrates by heating and pressing, or may be performed again by heating after the integration.

【0014】上記絶縁層には、基板の低熱膨張化(多層
配線基板全体の熱膨張率をシリコンに限りなく近づける
こと)のため、Ni−Fe系合金箔,チタン箔もしくは
セラミックス材料シートを芯材として配設することがで
きる。Ni−Fe系合金箔,チタン箔もしくはセラミッ
クス材料シートは、導体層および絶縁層の膨張を抑制す
る働きをするため、それ自体の熱膨張率が充分に小さい
必要がある。
In order to reduce the thermal expansion of the substrate (to make the thermal expansion coefficient of the entire multilayer wiring substrate as close as possible to silicon), the insulating layer is made of a Ni—Fe alloy foil, a titanium foil or a ceramic material sheet as a core material. Can be arranged as Since the Ni—Fe alloy foil, titanium foil or ceramic material sheet functions to suppress the expansion of the conductor layer and the insulating layer, the thermal expansion coefficient of the foil itself must be sufficiently small.

【0015】芯材がNi−Fe系合金箔の場合、Ni−
Fe系合金の比率により熱膨張率が変化するため、Ni
含有率は31〜50重量%、好ましくは31〜45重量
%の範囲が好適に用いられる。この範囲以上もしくは以
下であると、熱膨張係数が大きくなり、多層配線基板全
体の熱膨張を抑制することが難しくなる。
[0015] When the core material is a Ni-Fe alloy foil, Ni-
Since the coefficient of thermal expansion changes depending on the ratio of the Fe-based alloy, Ni
The content is in the range of 31 to 50% by weight, preferably 31 to 45% by weight. If it is above or below this range, the coefficient of thermal expansion will increase, making it difficult to suppress the thermal expansion of the entire multilayer wiring board.

【0016】チタン箔の場合、市販の純チタン箔および
チタン合金箔が含まれる。チタン合金としては、主成分
のTiに対してAl,V,Cr,Mn,Sn,Zr等の
金属を配合した合金が使用される。これらのチタン箔
は、熱膨脹係数が8.8〜9.0ppm/℃程度である
が、比重が4.5程度で体積当りの重量が軽い特徴を有
している。一方、セラミックス材料としては、アルミ
ナ,ムライト,コージライト,炭化珪素,窒化珪素,窒
化アルミ,ジルコニア等、あるいはこれらの混合物が挙
げられる。
In the case of titanium foil, commercially available pure titanium foil and titanium alloy foil are included. As the titanium alloy, an alloy in which metals such as Al, V, Cr, Mn, Sn, and Zr are blended with Ti as a main component is used. These titanium foils have a coefficient of thermal expansion of about 8.8 to 9.0 ppm / ° C., but have a specific gravity of about 4.5 and a light weight per volume. On the other hand, examples of the ceramic material include alumina, mullite, cordierite, silicon carbide, silicon nitride, aluminum nitride, zirconia, and the like, or a mixture thereof.

【0017】これらの芯材の厚みは、10〜300μm
であるのが好ましい。10μmを下回ると、多層配線基
板の熱膨張率を抑えることが難しくなり、一方300μ
mを超えると加工性が低下するとともにスルーホールめ
っきの信頼性が低下する。なお、Ni−Fe系合金箔,
チタン箔もしくはセラミックス材料シートを芯材とした
両面回路基板の表裏両導体層を電気的に接続する方法
は、従来のスルーホールめっきにより行う。
The thickness of these core materials is 10 to 300 μm
It is preferred that When the thickness is less than 10 μm, it is difficult to suppress the coefficient of thermal expansion of the multilayer wiring board.
If it exceeds m, workability is reduced and reliability of through-hole plating is reduced. In addition, Ni-Fe alloy foil,
A method for electrically connecting both front and back conductor layers of a double-sided circuit board using a titanium foil or a ceramic material sheet as a core material is performed by conventional through-hole plating.

【0018】[0018]

【発明の実施の形態】つぎに、本発明の実施の形態を図
面にもとづいて説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

【0019】図1は本発明の多層配線基板の一実施の形
態を示している。図において、1はポリイミド樹脂から
なる絶縁層2の表裏両面に銅箔からなる回路(配線導
体)3が形成された両面回路基板である。この実施の形
態では、3枚の両面回路基板1が用いられており、これ
により、多層配線基板として6層配線基板が作製されて
いる。4は上記各両面回路基板1に穿設した孔1aに銅
めっき加工を施して形成したスルーホールめっき部であ
り、表裏両面の回路3を電気的に接続している。5は上
記各両面回路基板1同士を接着するポリイミド系接着剤
層である。6は上下に隣り合う2つの両面回路基板1の
回路3を電気的に接続する半田製導電体である。
FIG. 1 shows an embodiment of the multilayer wiring board of the present invention. In the figure, reference numeral 1 denotes a double-sided circuit board in which a circuit (wiring conductor) 3 made of copper foil is formed on both sides of an insulating layer 2 made of a polyimide resin. In this embodiment, three double-sided circuit boards 1 are used, whereby a six-layer wiring board is manufactured as a multilayer wiring board. Reference numeral 4 denotes a through-hole plated portion formed by applying a copper plating process to a hole 1a formed in each of the double-sided circuit boards 1, and electrically connects the circuits 3 on both sides. Reference numeral 5 denotes a polyimide adhesive layer for bonding the double-sided circuit boards 1 to each other. Reference numeral 6 denotes a solder conductor for electrically connecting the circuits 3 of the two double-sided circuit boards 1 adjacent to each other.

【0020】上記多層配線基板を、つぎのようにして製
造することができる。すなわち、まず、ポリイミド樹脂
からなる絶縁層2の表裏両面に銅箔よりなる導体層3a
が形成された3枚の基材10(図2参照)と、ポリイミ
ド系接着剤からなる2枚の接着シート(図4参照)8と
を準備する。上記両接着シート8には、その所定位置
(図1の半田製導電体6を設ける位置)に孔8aが開け
られている。ついで、図3に示すように、上記各基材1
0の所定位置にドリル等で孔1aを開け、この孔1aに
銅のスルーホールめっきを行ってスルーホールめっき部
4を設け、上記各基材10の表裏両面の導体層3aに従
来のエッチング法により回路3を形成し、3枚の両面回
路基板1を作製する。つぎに、図4に示すように、上記
各接着シート8を(3枚のうちの)2枚の両面回路基板
1の上面に、各接着シート8の開孔部8aを各両面回路
基板1の回路3の所定位置(図1の半田製導電体6を設
ける位置)に位置合わせして仮接着する。つぎに、上記
各接着シート8の開孔部8aにスクリーン印刷により半
田ペーストを入れ、加熱溶融させて各両面回路基板1の
回路3上に半田バンプ9を形成する。つぎに、半田バン
プ9を設けた2枚の両面回路基板1と、回路3を形成し
ただけの1枚の両面回路基板1をそれぞれ位置合わせし
て複数枚重ねたのち(図6参照)、加熱加圧し一体化さ
せる。この状態では、各接着シート8は接着剤層5とな
り、各半田バンプ9は半田製導電体6となる。これによ
り、3枚の両面回路基板1が積層一体化された6層配線
基板を得ることができる。
The above multilayer wiring board can be manufactured as follows. That is, first, the conductor layers 3a made of copper foil are formed on both front and back surfaces of the insulating layer 2 made of polyimide resin.
Are prepared, and three adhesive sheets (see FIG. 4) 8 made of a polyimide-based adhesive are prepared. Holes 8a are formed in the two adhesive sheets 8 at predetermined positions (positions where the solder conductors 6 in FIG. 1 are provided). Next, as shown in FIG.
0 is drilled at a predetermined position with a drill or the like, and through-hole plating of copper is performed on the hole 1a to form a through-hole plating portion 4. The conductor layer 3a on each of the front and back surfaces of each of the base materials 10 is formed by a conventional etching method. The circuit 3 is formed by the above method, and three double-sided circuit boards 1 are manufactured. Next, as shown in FIG. 4, each of the adhesive sheets 8 is provided on the upper surface of two (three) double-sided circuit boards 1, and the opening 8 a of each adhesive sheet 8 is provided with each of the double-sided circuit boards 1. The circuit 3 is temporarily bonded at a predetermined position (position where the solder conductor 6 of FIG. 1 is provided). Next, a solder paste is put into the opening 8a of each of the adhesive sheets 8 by screen printing, and is heated and melted to form solder bumps 9 on the circuit 3 of each double-sided circuit board 1. Next, two double-sided circuit boards 1 on which the solder bumps 9 are provided and one double-sided circuit board 1 on which only the circuit 3 is formed are aligned with each other, and a plurality of the double-sided circuit boards 1 are stacked (see FIG. 6). Press and integrate. In this state, each adhesive sheet 8 becomes the adhesive layer 5, and each solder bump 9 becomes the conductor 6 made of solder. As a result, a six-layer wiring board in which three double-sided circuit boards 1 are laminated and integrated can be obtained.

【0021】上記のように、この実施の形態では、一回
の加熱加圧により3枚の両面回路基板1の一体化が行え
ると同時に、6層の回路3間の電気的接続(6層間の電
気的接続)も行える。また、半田を用いているため、低
抵抗の層間接続が行える。さらに、各両面回路基板1に
スルーホールめっき部4を設けているため、各スルーホ
ールめっき部4および各半田製導電体6の位置を任意に
設定することにより、6層間の電気的接続をそれぞれ任
意の位置で行うことができ、設計の自由度が大幅に増え
る。
As described above, in this embodiment, the three double-sided circuit boards 1 can be integrated by one heating / pressing operation, and at the same time, the electrical connection between the six-layer circuits 3 (the six-layer circuit 3). Electrical connection). Further, since solder is used, low-resistance interlayer connection can be performed. Furthermore, since the through-hole plated portions 4 are provided on each of the double-sided circuit boards 1, the positions of the through-hole plated portions 4 and the respective solder-made conductors 6 are arbitrarily set so that the electrical connection between the six layers is established. It can be performed at any position, greatly increasing the degree of freedom of design.

【0022】図7は本発明の多層配線基板の他の実施の
形態を示している。この実施の形態では、両面回路基板
1の絶縁層2にNi−Fe系合金箔12が芯材として配
設されている。それ以外の部分は図1に示す多層配線基
板と同様であり、同様の部分には同じ符号を付してい
る。
FIG. 7 shows another embodiment of the multilayer wiring board of the present invention. In this embodiment, a Ni—Fe alloy foil 12 is disposed as a core material on the insulating layer 2 of the double-sided circuit board 1. Other parts are the same as those of the multilayer wiring board shown in FIG. 1, and the same parts are denoted by the same reference numerals.

【0023】この実施の形態では、両面回路基板1をつ
ぎのようにして製造することができる。すなわち、図8
に示すように、Ni−Fe系合金箔12の所定位置(ス
ルーホールめっき部4を設ける位置)に孔12aを開
け、ついで、Ni−Fe系合金箔12の表裏両面からポ
リイミド系接着剤(基材10の絶縁層2となる)を用い
て導体層3aを張り合わせ、図9に示すような基材10
を作製する。つぎに、図10に示すように、上記基材1
0の、Ni−Fe系合金箔12の開孔部12aに対応す
る部分に、この開孔部12aより小さい孔1aを開け、
図11に示すように、この孔1aに銅めっき加工を施す
ことにより形成したスルーホール部4で表裏両面の導体
層3aを電気的に接続する。このようにして得られた基
材10の熱膨張率は芯材の材料であるNi−Fe系合金
に支配されているため、Ni−Feの比率や箔の厚みを
変えることで上記熱膨張率を調節することができる。つ
ぎに、図11に示す基材10の表裏両面の導体層3aに
回路3を形成して両面回路基板1(図3参照)を作製す
る。そののち、図4〜図6に示す方法と同様にして、6
層配線基板を製造する。
In this embodiment, the double-sided circuit board 1 can be manufactured as follows. That is, FIG.
As shown in the figure, a hole 12a is opened at a predetermined position (position where the through-hole plating portion 4 is provided) of the Ni-Fe-based alloy foil 12, and then a polyimide-based adhesive (base) is applied from both front and back surfaces of the Ni-Fe-based alloy foil 12. The conductive layer 3a is bonded using the insulating layer 2 of the material 10) to form a base material 10 as shown in FIG.
Is prepared. Next, as shown in FIG.
0, a hole 1a smaller than the opening 12a is formed in a portion corresponding to the opening 12a of the Ni—Fe alloy foil 12,
As shown in FIG. 11, through holes 4 formed by applying copper plating to the holes 1a electrically connect the conductor layers 3a on both the front and back surfaces. Since the coefficient of thermal expansion of the base material 10 thus obtained is governed by the Ni—Fe-based alloy as the material of the core material, the coefficient of thermal expansion can be changed by changing the ratio of Ni—Fe or the thickness of the foil. Can be adjusted. Next, the circuit 3 is formed on the conductor layers 3a on both the front and back surfaces of the base material 10 shown in FIG. 11 to produce the double-sided circuit board 1 (see FIG. 3). After that, in the same manner as in the method shown in FIGS.
A layer wiring board is manufactured.

【0024】上記のように、この実施の形態でも、図1
に示す実施の形態と同様に、一回の加熱加圧により3枚
の両面回路基板1の一体化が行えると同時に、6層間の
電気的接続も行える。しかも、2層の回路3に対して1
層の割合でNi−Fe系合金箔12が配設されているた
め、銅箔で回路3を構成する場合にも、6層配線基板全
体の熱膨張率を極めて低くすることができ、極めて高い
接続信頼性を得ることができる。また、半田を用いてい
るため、低抵抗の6層間接続が行える。さらに、各両面
回路基板1にスルーホールめっき部4を設けているた
め、各スルーホールめっき部4および各半田製導電体6
の位置を任意に設定することにより、6層間の電気的接
続をそれぞれ任意の位置で行うことができ、設計の自由
度が大幅に増える。そのうえ、この実施の形態では、熱
膨張率の極めて低い多層配線基板を得ることができる。
As described above, also in this embodiment, FIG.
In the same manner as in the embodiment shown in FIG. 1, the three double-sided circuit boards 1 can be integrated by one heating and pressing, and the electrical connection between the six layers can also be performed. Moreover, 1 for the two-layer circuit 3
Since the Ni—Fe-based alloy foil 12 is disposed in the proportion of the layers, even when the circuit 3 is formed of a copper foil, the coefficient of thermal expansion of the entire six-layer wiring board can be extremely low and extremely high. Connection reliability can be obtained. In addition, since solder is used, low-resistance six-layer connection can be performed. Furthermore, since the through-hole plated portions 4 are provided on each of the double-sided circuit boards 1, each of the through-hole plated portions 4 and each of the solder conductors 6 are provided.
By setting the positions arbitrarily, the electrical connection between the six layers can be made at any positions, respectively, and the degree of freedom in design is greatly increased. In addition, in this embodiment, a multilayer wiring board having a very low coefficient of thermal expansion can be obtained.

【0025】また、芯材としてNi−Fe系合金箔に代
えてチタン箔を使用することができる。チタン箔は熱膨
脹係数が比較的小さく、軽量かつ耐腐食性に優れた多層
配線基板を製造することができる。
Further, a titanium foil can be used as the core material instead of the Ni—Fe alloy foil. Titanium foil has a relatively small coefficient of thermal expansion, and can be used to manufacture a multilayer wiring board that is lightweight and has excellent corrosion resistance.

【0026】図12は本発明の多層配線基板のさらに他
の実施の形態を示している。この実施の形態では、両面
回路基板1の絶縁層2にアルミナ等のセラミックス材料
からなるシート13が芯材として配設されている。それ
以外の部分は図1に示す多層配線基板と同様であり、同
様の部分には同じ符号を付している。
FIG. 12 shows still another embodiment of the multilayer wiring board of the present invention. In this embodiment, a sheet 13 made of a ceramic material such as alumina is provided as a core material on the insulating layer 2 of the double-sided circuit board 1. Other parts are the same as those of the multilayer wiring board shown in FIG. 1, and the same parts are denoted by the same reference numerals.

【0027】この実施の形態でも、両面回路基板1を上
記他の実施の形態と同様に作製することができる。な
お、アルミナ等のセラミックス材料は絶縁物なので、図
8に示すような孔12aをシート13に開ける必要はな
い。また、この実施の形態でも、上記他の実施の形態と
同様の作用・効果を奏する。しかも、この実施の形態で
は、図8に示すような孔12aをシート13に開ける必
要がない分、両面回路基板1の作製工程が簡単になる。
In this embodiment, the double-sided circuit board 1 can be manufactured in the same manner as the other embodiments. Since the ceramic material such as alumina is an insulating material, it is not necessary to form the holes 12a in the sheet 13 as shown in FIG. Also, in this embodiment, the same operation and effect as those of the above-described other embodiments can be obtained. In addition, in this embodiment, the process of manufacturing the double-sided circuit board 1 is simplified because it is not necessary to form the holes 12a in the sheet 13 as shown in FIG.

【0028】[0028]

【実施例1】表裏両面の銅箔層の厚み18μm,ポリイ
ミド樹脂からなる絶縁層22の厚み50μmの両面銅張
ポリイミド基材(三井東圧社製:NEOFLEXNEX
−231R)の所定の位置に直径0.2mmのドリルで
孔21aを開け、めっきの厚み5μmの銅のスルーホー
ルめっきを行い(スルーホールめっき部24を形成
し)、従来のエッチング法により表裏両面の銅箔層に回
路23を形成して両面回路基板21を作製した(図13
参照)。つぎに、直径0.2mmのドリルで孔28aを
開けたポリイミド系接着シート28(新日鐡化学社製:
SPB−035A)を両面回路基板21上に位置合わせ
して載せ、その状態で加熱加圧接着(30Kg/c
2 、180℃で30分)した(図14参照)。つぎ
に、接着シート28の開孔部28aに半田ペースト(日
本スペリア社製:Sn8RA−3AMQ、融点260
℃)をスクリーン印刷で充填し、290℃でリフローし
たのち、フラックスを洗浄除去し半田バンプ29を形成
した(図15参照)。同様の方法により、もう一枚の半
田バンプ29付き両面回路基板27aと、回路23形成
まで行った両面回路基板27b(図16参照)を製造
し、これら3枚を位置合わせして重ね、加熱加圧(30
Kg/cm2 、200℃で1時間)により一体化し、6
層配線基板を作製した(図17参照)。図17におい
て、25は接着シート28により形成された接着剤層で
あり、26は半田バンプ29により形成された半田製導
電体である。
EXAMPLE 1 A double-sided copper-clad polyimide substrate (manufactured by Mitsui Toatsu Co., Ltd .: NEOFLEXNEX) having a thickness of 18 μm of a copper foil layer on both sides and a thickness of 50 μm of an insulating layer 22 made of a polyimide resin.
-231R), a hole 21a is drilled at a predetermined position with a drill having a diameter of 0.2 mm, and a through-hole plating of copper having a plating thickness of 5 μm is performed (a through-hole plating portion 24 is formed). The circuit 23 was formed on the copper foil layer of FIG.
reference). Next, a polyimide-based adhesive sheet 28 (manufactured by Nippon Steel Chemical Co., Ltd.) having a hole 28a opened with a drill having a diameter of 0.2 mm:
SPB-035A) is positioned and placed on the double-sided circuit board 21, and in this state, heat and pressure is applied (30 kg / c).
m 2 at 180 ° C. for 30 minutes) (see FIG. 14). Next, a solder paste (Sn8RA-3AMQ, manufactured by Nippon Superior Co., Ltd., melting point 260
C.) by screen printing, and after reflow at 290.degree. C., the flux was washed away to form solder bumps 29 (see FIG. 15). In the same manner, another double-sided circuit board 27a with solder bumps 29 and a double-sided circuit board 27b (see FIG. 16) on which the formation of the circuit 23 has been completed are manufactured. Pressure (30
Kg / cm 2 at 200 ° C. for 1 hour)
A layer wiring board was produced (see FIG. 17). In FIG. 17, reference numeral 25 denotes an adhesive layer formed by an adhesive sheet 28, and reference numeral 26 denotes a solder conductor formed by solder bumps 29.

【0029】[0029]

【実施例2】厚み18μmの銅箔33aにポリイミド前
駆体ワニス(p−フェニレンジアミンと,3,3´,
4、4´−ビフェニルテトラカルボン酸二無水物をn−
メチルピロリドン中で反応させたポリアミック酸ワニ
ス)を塗布、乾燥し、窒素雰囲気中で400℃,1時間
イミド化し、厚み20μmのポリイミド層32aを設け
ることにより、銅ポリイミドの2層基材30を作製した
(図18参照)。つぎに、所定位置に直径0.3mmの
ドリルで孔35aを開けた厚み50μmの42アロイ箔
35(ニッケル42重量%,鉄58重量%,熱膨張係数
4.5ppm/℃)の表裏両面に上記2層基材30をポ
リイミド系接着シート32b(新日鐡化学社製:SPB
−035A)を用いて(図19参照)、加圧加熱接着
(40Kg/cm2 、200℃で1時間)を行い、図2
0に示すような低熱膨張両面基板36を作製した。この
低熱膨張両面基板36ではポリイミド層32aとポリイ
ミド系接着シート32bにより絶縁層32が形成されて
いる。さらに、42アロイ箔35の孔35aと同じ位置
に直径0.2mmのドリルを用いて貫通孔36aを開
け、これを実施例1と同様の方法で銅のスルーホールめ
っきを行い(スルーホールめっき部34)、回路33形
成を行い、両面回路基板31を作製した。そののちは、
実施例1と同様にして接着シートを仮接着し、半田バン
プを形成し、加熱加圧して全体を一体化し、層間の電気
的接続を行い、6層配線基板を作製した。
Example 2 A polyimide precursor varnish (p-phenylenediamine, 3,3 ′,
4,4'-biphenyltetracarboxylic dianhydride is n-
A polyamic acid varnish reacted in methylpyrrolidone) is applied, dried, imidized in a nitrogen atmosphere at 400 ° C. for 1 hour, and a 20 μm-thick polyimide layer 32 a is provided to produce a copper polyimide two-layer substrate 30. (See FIG. 18). Next, a 50 μm-thick 42-alloy foil 35 (nickel 42% by weight, iron 58% by weight, thermal expansion coefficient 4.5 ppm / ° C.) having a hole 35 a drilled at a predetermined position with a drill having a diameter of 0.3 mm was formed on both the front and back surfaces. The two-layer substrate 30 is made of a polyimide-based adhesive sheet 32b (manufactured by Nippon Steel Chemical: SPB).
−035A) (see FIG. 19), and pressure and heat bonding (40 kg / cm 2 , 200 ° C. for 1 hour) was performed.
A low thermal expansion double-sided substrate 36 as shown in FIG. In this low-thermal-expansion double-sided substrate 36, the insulating layer 32 is formed by the polyimide layer 32a and the polyimide-based adhesive sheet 32b. Further, a through-hole 36a was opened at the same position as the hole 35a of the 42 alloy foil 35 using a drill having a diameter of 0.2 mm, and the through-hole 36a was plated with copper in the same manner as in Example 1 (through-hole plating portion). 34), a circuit 33 was formed, and a double-sided circuit board 31 was produced. After that,
In the same manner as in Example 1, an adhesive sheet was temporarily bonded, solder bumps were formed, the whole was integrated by heating and pressing, and electrical connection between layers was performed, thereby producing a six-layer wiring board.

【0030】[0030]

【実施例3】実施例2で使用した42アロイ箔35の代
わりに、厚み50μmの36アロイ箔(ニッケル36重
量%,鉄64重量%,熱膨張係数1.5ppm/℃)を
用いた以外は、実施例2と同様にして6層配線基板を作
製した。
EXAMPLE 3 Instead of the 42 alloy foil 35 used in Example 2, a 36 alloy foil having a thickness of 50 μm (nickel: 36% by weight, iron: 64% by weight, thermal expansion coefficient: 1.5 ppm / ° C.) was used. In the same manner as in Example 2, a six-layer wiring board was manufactured.

【0031】[0031]

【実施例4】厚み200μmの窒化アルミシート(Al
N、熱膨張係数4.3ppm/℃)の両面に、実施例2
と同様の方法で作製した銅ポリイミドの2層基材を、ポ
リイミド系接着シート(新日鐡化学社製:SPB−03
5A)を用いて加圧加熱接着(40Kg/cm2 、20
0℃で60分)を行い、低熱膨張両面基板を作製した。
この低熱膨張両面基板に直径0.2mmのドリルを用い
て貫通孔を開け、これを実施例1と同様の方法で銅のス
ルーホールめっきを行い、回路形成を行い、両面回路基
板を作製した。そののちは、実施例1と同様にして接着
シートを仮接着し、半田バンプを形成し、加熱加圧して
全体を一体化し、層間の電気的接続を行い、6層配線基
板を作製した。
Embodiment 4 A 200 μm thick aluminum nitride sheet (Al
N, thermal expansion coefficient 4.3 ppm / ° C.)
A copper-based two-layer substrate prepared by the same method as described above was used as a polyimide-based adhesive sheet (SPB-03 manufactured by Nippon Steel Chemical Co., Ltd.).
5A) using pressure and heat bonding (40 kg / cm 2 , 20
0 ° C. for 60 minutes) to produce a low thermal expansion double-sided substrate.
A through-hole was formed in this low-thermal-expansion double-sided board using a drill having a diameter of 0.2 mm, and this was plated with copper through-holes in the same manner as in Example 1 to form a circuit, thereby producing a double-sided circuit board. Thereafter, the adhesive sheet was provisionally bonded in the same manner as in Example 1, solder bumps were formed, the whole was integrated by heating and pressing, and electrical connection between layers was performed, thereby producing a six-layer wiring board.

【0032】[0032]

【実施例5】厚み50μmの純チタン箔(熱膨脹係数
8.8ppm/℃)を用いた以外は、実施例2と同様に
して6層配線基板を作製した。
Example 5 A six-layer wiring board was produced in the same manner as in Example 2, except that a pure titanium foil having a thickness of 50 μm (coefficient of thermal expansion: 8.8 ppm / ° C.) was used.

【0033】上記のようにして作製した実施例1〜5の
多層配線基板は6層の導体層からなり、しかも任意の位
置で層間接続できることが確認された。また、順次積み
重ねていく方法ではなく、一括で積層できるため、製造
工程は大幅に簡略化された。一方、実施例1〜5の6層
配線基板の熱膨張率を室温(25℃)から200℃の範
囲で設定したところ、以下のようになった。
It was confirmed that the multilayer wiring boards of Examples 1 to 5 produced as described above consisted of six conductor layers, and that they could be connected at any position between layers. In addition, since the layers can be stacked at once instead of a method of sequentially stacking, the manufacturing process is greatly simplified. On the other hand, when the coefficient of thermal expansion of the six-layer wiring boards of Examples 1 to 5 was set in the range from room temperature (25 ° C.) to 200 ° C., the results were as follows.

【0034】[0034]

【表1】 [Table 1]

【0035】表1に示すように、芯材として、Ni−F
e系合金箔,チタン箔もしくはセラミックス材料シート
を使用した実施例2〜4の6層配線基板の熱膨張率は極
めて小さく、ベアチップ実装に適した基板であることは
明白である。
As shown in Table 1, Ni-F was used as the core material.
The six-layer wiring boards of Examples 2 to 4 using an e-based alloy foil, a titanium foil, or a ceramic material sheet have extremely low coefficients of thermal expansion, and are clearly suitable for bare chip mounting.

【0036】なお、上記各実施の形態では、接着シート
8,28の開孔部8a,28aに半田ペーストをスクリ
ーン印刷により充填しているが、これに限定するもので
はなく、メタルマスク印刷,ディスペンス印刷,転写法
により充填してもよい。
In each of the above embodiments, the openings 8a and 28a of the adhesive sheets 8 and 28 are filled with the solder paste by screen printing. However, the present invention is not limited to this. It may be filled by a printing and transfer method.

【0037】[0037]

【発明の効果】以上のように、本発明の多層配線基板の
方法によれば、両面回路基板に接着シートを位置合わせ
して仮接着し、この接着シートに開けた開孔部に半田バ
ンプを形成したのち、各両面回路基板位置合わせして積
み重ね加熱加圧して全体を一体化させているため、一回
の加熱加圧により複数の両面回路基板を一体化すること
ができる。と同時に、配線導体の層数が何層であって
も、上記一回の加熱加圧により各配線導体間の電気的接
続が行える。また、本発明の多層配線基板は、複数の両
面回路基板がそれぞれ接着剤層を介して積層一体化さ
れ、上記接着剤層には、これを挟む2つの両面回路基板
の配線導体に当接する部分の所定位置に孔が穿設され、
この穿孔部に半田製導電体が設けられているため、接続
抵抗が低く、薄型で高性能の接続信頼性の高い基板を提
供することができる。しかも、各両面回路基板にスルー
ホールを設けて各両面回路基板の表裏両面の配線導体を
電気的に接続しているため、スルーホールの位置,半田
導電体の位置を任意に設定することにより各配線導体間
の電気的接続を任意の位置で行うことができる。
As described above, according to the multilayer wiring board method of the present invention, the adhesive sheet is aligned and temporarily bonded to the double-sided circuit board, and the solder bumps are formed in the openings formed in the adhesive sheet. After the formation, each double-sided circuit board is aligned, stacked, heated and pressed to integrate the whole, so that a plurality of double-sided circuit boards can be integrated by a single heating and pressing. At the same time, regardless of the number of layers of the wiring conductor, electrical connection between the wiring conductors can be performed by the single heating and pressing. Also, in the multilayer wiring board of the present invention, a plurality of double-sided circuit boards are laminated and integrated via an adhesive layer, respectively, and the adhesive layer has a portion in contact with the wiring conductors of the two double-sided circuit boards sandwiching this. A hole is drilled in the predetermined position of
Since the conductor made of solder is provided in the perforated portion, it is possible to provide a thin, high-performance, highly reliable connection substrate with low connection resistance. Moreover, since through-holes are provided in each double-sided circuit board to electrically connect the wiring conductors on the front and back surfaces of each double-sided circuit board, the position of the through-hole and the position of the solder conductor can be set arbitrarily. The electrical connection between the wiring conductors can be made at any position.

【0038】また、本発明において、上記絶縁層にNi
−Fe系合金箔,チタン箔もしくはセラミックス材料シ
ートが芯材として含まれている場合には、配線導体2層
に対して1層の割合でNi−Fe系合金箔,チタン箔も
しくはセラミックス材料シートからなる低熱膨張率の芯
材が含まれることになり、配線導体として銅を用いた場
合にも、多層基板全体の熱膨張率をシリコンに限りなく
近づけることが可能になる。このように、絶縁層にNi
−Fe系合金箔,チタン箔もしくはセラミックス材料シ
ートが芯材として含まれている場合には、熱膨張率を極
めて低くすることができるため、ベアチップ実装におい
ても、極めて高い接続信頼性を有する。
In the present invention, the insulating layer may be made of Ni.
-When an Fe-based alloy foil, a titanium foil, or a ceramic material sheet is included as a core material, a Ni-Fe-based alloy foil, a titanium foil, or a ceramic material sheet is used in a ratio of one layer to two wiring conductors. Since a core material having a low coefficient of thermal expansion is included, even when copper is used as a wiring conductor, the coefficient of thermal expansion of the entire multilayer substrate can be made as close as possible to silicon. Thus, the insulating layer is made of Ni
-When an Fe-based alloy foil, a titanium foil, or a ceramic material sheet is included as a core material, the coefficient of thermal expansion can be extremely reduced, so that extremely high connection reliability can be obtained even in bare chip mounting.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層配線基板の一実施の形態を示す断
面図である。
FIG. 1 is a sectional view showing an embodiment of a multilayer wiring board of the present invention.

【図2】基材の断面図である。FIG. 2 is a sectional view of a substrate.

【図3】両面回路基板の断面図である。FIG. 3 is a sectional view of a double-sided circuit board.

【図4】両面回路基板に接着シートを仮接着した状態を
示す断面図である。
FIG. 4 is a cross-sectional view showing a state where an adhesive sheet is temporarily bonded to a double-sided circuit board.

【図5】接着シートに半田バンプを形成した状態を示す
断面図である。
FIG. 5 is a cross-sectional view showing a state where solder bumps are formed on an adhesive sheet.

【図6】各両面回路基板を積層する状態を示す断面図で
ある。
FIG. 6 is a cross-sectional view showing a state in which the double-sided circuit boards are stacked.

【図7】本発明の多層配線基板の他の実施の形態を示す
断面図である。
FIG. 7 is a sectional view showing another embodiment of the multilayer wiring board of the present invention.

【図8】芯材の断面図である。FIG. 8 is a sectional view of a core material.

【図9】基材の断面図である。FIG. 9 is a sectional view of a base material.

【図10】基材に孔をあけた状態を示す断面図である。FIG. 10 is a cross-sectional view showing a state in which holes are formed in a base material.

【図11】基材をスルーホールめっきした状態を示す断
面図である。
FIG. 11 is a cross-sectional view showing a state in which a base material is plated through holes.

【図12】本発明の多層配線基板のさらに他の実施の形
態を示す断面図である。
FIG. 12 is a sectional view showing still another embodiment of the multilayer wiring board of the present invention.

【図13】実施例1の両面回路基板の断面図である。FIG. 13 is a cross-sectional view of the double-sided circuit board according to the first embodiment.

【図14】両面回路基板に接着シートを仮接着した状態
を示す断面図である。
FIG. 14 is a cross-sectional view showing a state where an adhesive sheet is temporarily bonded to a double-sided circuit board.

【図15】接着シートに半田バンプを形成した状態を示
す断面図である。
FIG. 15 is a cross-sectional view showing a state where solder bumps are formed on an adhesive sheet.

【図16】各両面回路基板を積層する状態を示す断面図
である。
FIG. 16 is a cross-sectional view showing a state in which the double-sided circuit boards are stacked.

【図17】実施例1の6層配線基板を示す断面図であ
る。
FIG. 17 is a cross-sectional view illustrating a six-layer wiring board according to the first embodiment.

【図18】実施例2の2層基材の断面図である。FIG. 18 is a cross-sectional view of a two-layer base material of Example 2.

【図19】低膨張率両面基板の作製要領を示す断面図で
ある。
FIG. 19 is a cross-sectional view showing the procedure for producing a low expansion coefficient double-sided substrate.

【図20】低膨張率両面基板の断面図である。FIG. 20 is a cross-sectional view of a low expansion coefficient double-sided substrate.

【図21】低膨張率両面基板をスルーホールめっきした
状態を示す断面図である。
FIG. 21 is a cross-sectional view showing a state in which a low expansion coefficient double-sided substrate is plated with through holes.

【符号の説明】[Explanation of symbols]

1 両面回路基板 2 絶縁層 3 回路 4 スルーホールめっき部 8 接着シート 8a 開孔部 9 半田バンプ DESCRIPTION OF SYMBOLS 1 Double-sided circuit board 2 Insulating layer 3 Circuit 4 Through-hole plating part 8 Adhesive sheet 8a Opening part 9 Solder bump

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】 有機高分子樹脂からなる絶縁層の両面に
配線導体が設けられこれら両配線導体がスルーホールで
電気的に接続された複数の両面回路基板がそれぞれ接着
剤層を介して積層一体化され、上記接着剤層には、これ
を挟む2つの両面回路基板の配線導体に当接する部分の
所定位置に孔が穿設され、上記穿孔部に半田製導電体が
設けられ、上記半田製導電体により上記2つの両面回路
基板の配線導体が電気的に接続されていること特徴とす
る多層配線基板。
A plurality of double-sided circuit boards in which wiring conductors are provided on both surfaces of an insulating layer made of an organic polymer resin and both of these wiring conductors are electrically connected through through holes are integrally laminated via an adhesive layer. The adhesive layer is provided with a hole at a predetermined position in a portion where the adhesive layer comes into contact with the wiring conductor of the two double-sided circuit boards, a solder conductor is provided in the hole, and the solder material is provided. A multilayer wiring board, wherein the wiring conductors of the two double-sided circuit boards are electrically connected by a conductor.
【請求項2】 有機高分子樹脂からなる絶縁層に、Ni
−Fe系合金箔,チタン箔もしくはセラミックス材料シ
ートが芯材として含まれている請求項1記載の多層配線
基板。
2. An insulating layer made of an organic polymer resin,
2. The multilayer wiring board according to claim 1, wherein a core is made of an Fe-based alloy foil, a titanium foil or a ceramic material sheet.
【請求項3】 Ni−Fe系合金箔のNi含有率が、3
1〜50重量%である請求項2記載の多層配線基板。
3. The Ni—Fe alloy foil having a Ni content of 3
The multilayer wiring board according to claim 2, wherein the content is 1 to 50% by weight.
【請求項4】 芯材の厚みが、10〜300μmである
請求項2記載の多層配線基板。
4. The multilayer wiring board according to claim 2, wherein the thickness of the core material is 10 to 300 μm.
【請求項5】 有機高分子樹脂からなる絶縁層が、ポリ
イミド系樹脂からなる請求項1記載の多層配線基板。
5. The multilayer wiring board according to claim 1, wherein the insulating layer made of an organic polymer resin is made of a polyimide resin.
【請求項6】 接着剤層が、ポリイミド系接着剤からな
る請求項1記載の多層配線基板。
6. The multilayer wiring board according to claim 1, wherein the adhesive layer comprises a polyimide-based adhesive.
【請求項7】 有機高分子樹脂からなる絶縁層の両面に
配線導体が設けられこれら両配線導体がスルーホールで
電気的に接続された複数の両面回路基板と、上記両面回
路基板の配線導体の所定部分に対応する位置に開孔した
接着シートとを準備する工程と、上記両面回路基板に設
けた配線導体の所定部分に上記接着シートの開孔部を位
置合わせした状態で上記両面回路基板に接着シートを仮
接着する工程と、接着シート仮接着後に各接着シートの
開孔部に半田ペーストを充填し加熱溶融させて半田バン
プを形成する工程と、半田バンプ形成後に上記各両面回
路基板の配線導体が所定の電気的接続を行えるよう位置
合わせして上記各両面回路基板を積み重ね加熱加圧して
全体を一体化させる工程を備えていること特徴とする多
層配線基板の製造方法。
7. A plurality of double-sided circuit boards in which wiring conductors are provided on both surfaces of an insulating layer made of an organic polymer resin, and both wiring conductors are electrically connected by through holes; A step of preparing an adhesive sheet that is opened at a position corresponding to a predetermined portion; and A step of temporarily bonding the adhesive sheet, a step of filling the opening of each adhesive sheet with the solder paste after the adhesive sheet is temporarily bonded and heating and melting to form a solder bump, and a step of forming the solder bumps after the formation of the solder bump. A method of manufacturing a multilayer wiring board, comprising a step of stacking the above-mentioned double-sided circuit boards and aligning the whole by heating and pressurizing the conductors so that conductors can perform predetermined electrical connection. Law.
【請求項8】 有機高分子樹脂からなる絶縁層に、Ni
−Fe系合金箔,チタン箔もしくはセラミックス材料シ
ートが芯材として含まれている請求項7記載の多層配線
基板の製造方法。
8. An insulating layer made of an organic polymer resin is made of Ni
8. The method for manufacturing a multilayer wiring board according to claim 7, wherein the core material comprises an Fe-based alloy foil, a titanium foil or a ceramic material sheet.
【請求項9】 Ni−Fe系合金箔のNi含有率が、3
1〜50重量%である請求項8記載の多層配線基板の製
造方法。
9. The Ni—Fe alloy foil having a Ni content of 3
9. The method according to claim 8, wherein the amount is 1 to 50% by weight.
【請求項10】 芯材の厚みが、10〜300μmであ
る請求項8記載の多層配線基板の製造方法。
10. The method according to claim 8, wherein the thickness of the core material is 10 to 300 μm.
【請求項11】 有機高分子樹脂からなる絶縁層が、ポ
リイミド系樹脂からなる請求項7記載の多層配線基板の
製造方法。
11. The method according to claim 7, wherein the insulating layer made of an organic polymer resin is made of a polyimide resin.
【請求項12】 接着剤層が、ポリイミド系接着剤から
なる請求項7記載の多層配線基板の製造方法。
12. The method according to claim 7, wherein the adhesive layer is made of a polyimide adhesive.
JP26862198A 1997-09-25 1998-09-22 Multilayer wiring boar and its manufacture Pending JPH11163522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26862198A JPH11163522A (en) 1997-09-25 1998-09-22 Multilayer wiring boar and its manufacture

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP26020197 1997-09-25
JP9-260201 1997-09-25
JP26862198A JPH11163522A (en) 1997-09-25 1998-09-22 Multilayer wiring boar and its manufacture

Publications (1)

Publication Number Publication Date
JPH11163522A true JPH11163522A (en) 1999-06-18

Family

ID=26544491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26862198A Pending JPH11163522A (en) 1997-09-25 1998-09-22 Multilayer wiring boar and its manufacture

Country Status (1)

Country Link
JP (1) JPH11163522A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100315751B1 (en) * 1999-12-31 2001-12-12 송재인 Low Temperature Ceramic Circuit
JP2003023248A (en) * 2001-07-05 2003-01-24 Nitto Denko Corp Multilayered flexible wiring circuit board and its manufacturing method
EP1109430A3 (en) * 1999-12-14 2003-09-10 Nitto Denko Corporation Double-sided circuit board and multilayer wiring board comprising the same and process for producing double-sided circuit board
JP2009130049A (en) * 2007-11-21 2009-06-11 Furukawa Electric Co Ltd:The Multilayer printed circuit board and method of manufacturing the same
US7943001B2 (en) 2006-06-16 2011-05-17 Fujitsu Limited Process for producing multilayer board
US20140291006A1 (en) * 2013-03-28 2014-10-02 Fujitsu Limited Printed circuit board solder mounting method and solder mount structure
JP2015211048A (en) * 2014-04-23 2015-11-24 トヨタ自動車株式会社 Multilayer substrate, and method of manufacturing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1109430A3 (en) * 1999-12-14 2003-09-10 Nitto Denko Corporation Double-sided circuit board and multilayer wiring board comprising the same and process for producing double-sided circuit board
KR100315751B1 (en) * 1999-12-31 2001-12-12 송재인 Low Temperature Ceramic Circuit
JP2003023248A (en) * 2001-07-05 2003-01-24 Nitto Denko Corp Multilayered flexible wiring circuit board and its manufacturing method
US7943001B2 (en) 2006-06-16 2011-05-17 Fujitsu Limited Process for producing multilayer board
JP2009130049A (en) * 2007-11-21 2009-06-11 Furukawa Electric Co Ltd:The Multilayer printed circuit board and method of manufacturing the same
US20140291006A1 (en) * 2013-03-28 2014-10-02 Fujitsu Limited Printed circuit board solder mounting method and solder mount structure
JP2015211048A (en) * 2014-04-23 2015-11-24 トヨタ自動車株式会社 Multilayer substrate, and method of manufacturing the same

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