JP2002076557A - Circuit wiring board and multilayer circuit wiring board using the same as well as its manufacturing method - Google Patents

Circuit wiring board and multilayer circuit wiring board using the same as well as its manufacturing method

Info

Publication number
JP2002076557A
JP2002076557A JP2000268157A JP2000268157A JP2002076557A JP 2002076557 A JP2002076557 A JP 2002076557A JP 2000268157 A JP2000268157 A JP 2000268157A JP 2000268157 A JP2000268157 A JP 2000268157A JP 2002076557 A JP2002076557 A JP 2002076557A
Authority
JP
Japan
Prior art keywords
circuit wiring
wiring board
hole
layer
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000268157A
Other languages
Japanese (ja)
Inventor
Masayuki Kaneto
正行 金戸
Kei Nakamura
圭 中村
Shinya Ota
真也 大田
Takuji Okeyui
卓司 桶結
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP2000268157A priority Critical patent/JP2002076557A/en
Publication of JP2002076557A publication Critical patent/JP2002076557A/en
Pending legal-status Critical Current

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Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a circuit wiring board capable of satisfying electrical connecting reliability. SOLUTION: The circuit wiring board comprises a metal layer 2 having a plurality of first through holes 2a formed at a predetermined interval in a thickness direction, insulating resin layers 3 made of insulating resins laminated on both side surfaces of the layer 2 to cover both side surfaces of the layer 2 by heating and pressurizing and to close inner peripheral surfaces of the first through holes 2a, and electrical circuit wirings 4 formed on both side surfaces of the layers 3. Second through holes 1a smaller than the first holes 2a are substantially concentrically provided at a part of the layer 3 for closing the holes 2a, and the wirings 4 formed on both side surfaces of the layer 3 are conducted by utilizing the holes 1a. An elastic modulus of the insulating layer is 7 MPa or less at a temperature for laminating, heating and pressurizing.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、回路配線基板およ
びそれを用いた多層回路配線基板ならびにその製造方法
に関するものである。
The present invention relates to a circuit wiring board, a multilayer circuit wiring board using the same, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年の電子機器の小型化,高性能化に伴
い、電子機器を構成する半導体装置およびこれを実装す
る方法には、小型薄型化,高性能化,高信頼性が要求さ
れている。これらの要求を受け、半導体素子は高集積化
されながらも大型化している。また、パッケージされて
いない裸の半導体素子(ベアチップ)が、直接プリント
回路基板に高密度実装される方法が実用化されてきてい
る。
2. Description of the Related Art With the recent miniaturization and high performance of electronic devices, semiconductor devices constituting electronic devices and methods for mounting the same have been required to be small, thin, high performance, and high reliability. I have. In response to these demands, semiconductor elements have become larger while being highly integrated. In addition, a method has been put to practical use in which unpackaged bare semiconductor elements (bare chips) are directly mounted at high density on a printed circuit board.

【0003】このような大型素子のベアチップ実装で
は、通常、熱膨張係数:3〜4ppm/℃のシリコンチ
ップを熱膨張係数:10〜20ppm/℃のプリント回
路基板上に直接接着剤を介して接着し接続している。ま
た、電気的な導通を、従来の金属ワイヤーでの接続のみ
ならず、シリコンチップに形成された金属突起電極によ
ってより短い導通路で達成している。ところが、このと
き、シリコンチップとプリント回路基板との熱膨張の差
により接続部に応力が発生し、接続信頼性が低下すると
いう問題が生じている。また、これら熱膨張の差により
発生する応力は、上記接着剤にクラックを生じさせて耐
湿性を低下させたり、端子電気接続部を破断させる等の
問題をも引き起こしている。また、これら熱膨張の差
は、シリコンチップとプリント回路基板との積層後の構
造に反りを発生する原因ともなる。
In the bare chip mounting of such a large element, a silicon chip having a coefficient of thermal expansion of 3 to 4 ppm / ° C. is usually bonded directly to a printed circuit board having a coefficient of thermal expansion of 10 to 20 ppm / ° C. via an adhesive. Connected. In addition, electrical conduction is achieved not only by conventional metal wires but also by shorter conductive paths by metal bump electrodes formed on the silicon chip. However, at this time, there is a problem that stress is generated in the connection portion due to a difference in thermal expansion between the silicon chip and the printed circuit board, and connection reliability is reduced. Further, the stress generated due to the difference in thermal expansion causes cracks in the adhesive, causing problems such as a decrease in moisture resistance and breakage of terminal electrical connection portions. In addition, these differences in thermal expansion also cause warpage of the structure after lamination of the silicon chip and the printed circuit board.

【0004】このような問題を解決するために、シリコ
ンチップ上の金属突起電極の材料,構造,配置または上
記接着剤の諸物性を最適化して応力の拡散を狙った方法
等が実施されているが、これらの方法によっても、接続
信頼性は充分ではなく、今後さらにシリコンチップが大
きくなり、さらに高密度な接続が要求されると、プリン
ト回路基板とシリコンチップとの熱膨張率の違いにより
発生する応力の問題はより深刻になる。
[0004] In order to solve such a problem, a method of optimizing the material, structure and arrangement of the metal bump electrodes on the silicon chip or various physical properties of the adhesive and aiming at diffusion of stress has been implemented. However, even with these methods, the connection reliability is not sufficient, and in the future silicon chips will become larger and higher density connections will be required due to differences in the coefficient of thermal expansion between printed circuit boards and silicon chips. The problem of stress is more severe.

【0005】そこで、上記の問題を抜本的に解決するた
めに、特開平11−163522号公報では、低線膨張
係数を有する金属箔51を芯材として配設した両面回路
基板50を作製し、この両面回路基板50の熱膨張をシ
リコンチップ(図示せず)の熱膨張に近接させるように
した発明が提案されている(図29参照)。
[0005] In order to drastically solve the above problem, Japanese Patent Application Laid-Open No. 11-163522 discloses a double-sided circuit board 50 in which a metal foil 51 having a low linear expansion coefficient is provided as a core material. An invention has been proposed in which the thermal expansion of the double-sided circuit board 50 is made close to that of a silicon chip (not shown) (see FIG. 29).

【0006】この発明では、上記両面回路基板50の作
製工程において、まず、スルーホールめっき部52に対
応する位置に貫通孔51aが形成された金属箔51を準
備する(図30参照)。ついで、ポリイミド系接着剤等
の絶縁樹脂53を介して、上記貫通孔51aを充填しな
がら、金属箔51の両面に導体層54aを加熱加圧積層
する。つぎに、上記貫通孔51aの位置にひとまわり小
さな径の貫通孔55を形成し(図29参照)、この貫通
孔55の内周面に銅めっきを施すことによりスルーホー
ルめっき部52を形成し、このスルーホールめっき部5
2を介して両面の導体層54aを厚み方向に導通させ
る。そののち、両面の導体層54aに回路54を形成し
ていた。図30において、56は導体層54aの裏面に
形成された絶縁樹脂層である。
In the present invention, in the manufacturing process of the double-sided circuit board 50, first, a metal foil 51 having a through hole 51a formed at a position corresponding to the through-hole plating portion 52 is prepared (see FIG. 30). Next, a conductor layer 54a is laminated by heating and pressing on both surfaces of the metal foil 51 while filling the through holes 51a via an insulating resin 53 such as a polyimide-based adhesive. Next, a through hole 55 having a diameter slightly smaller than the diameter of the through hole 51a is formed at the position of the through hole 51a (see FIG. 29), and the inner peripheral surface of the through hole 55 is plated with copper to form a through hole plated portion 52. , This through-hole plated part 5
2, the conductive layers 54a on both surfaces are conducted in the thickness direction. After that, the circuit 54 was formed on the conductor layers 54a on both surfaces. In FIG. 30, reference numeral 56 denotes an insulating resin layer formed on the back surface of the conductor layer 54a.

【0007】もしくは、図31に示すように、貫通孔5
1aが形成された金属箔51の両面に、上記貫通孔51
aを充填しながら、ポリイミド系接着剤等の絶縁樹脂5
3をプレス積層し、つぎに、上記貫通孔51aの位置に
ひとまわり小さな径の貫通孔55を形成し、これに金属
材料57を充填したのち、金属箔51の両面から導体層
(図示せず)を貼り合わせ、両面の導体層を厚み方向に
導通させることもできる。図31において、54は導体
層に形成した回路である。後者の方法では、複数の両面
回路基板50を積み重ねて多層回路基板を作製した場合
に、積み重なる各両面回路基板50を厚み方向に導通す
るための導電路の位置の設計自由度が、前者の方法より
も高く、高密度配線基板構造として適している。
[0007] Alternatively, as shown in FIG.
The through holes 51 are formed on both sides of the metal foil 51 on which the metal foil 1a is formed.
a while filling the insulating resin 5 such as a polyimide adhesive.
3 is press-laminated, and a through hole 55 having a diameter slightly smaller than that of the through hole 51a is formed at the position of the through hole 51a, and a metal material 57 is filled into the through hole 55. ) Can be bonded to make conductive layers on both sides conductive in the thickness direction. In FIG. 31, reference numeral 54 denotes a circuit formed on a conductor layer. In the latter method, when a multilayer circuit board is manufactured by stacking a plurality of double-sided circuit boards 50, the degree of freedom in designing the position of the conductive path for conducting the stacked double-sided circuit boards 50 in the thickness direction is limited to the former method. Higher and suitable as a high-density wiring board structure.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、上記の
ような製作工程においては、貫通孔51aが形成された
金属箔51の両面に絶縁樹脂53をプレス積層する際
に、この絶縁樹脂53が上記貫通孔51aを確実に充填
しながら、平坦な表面を得る必要がある。もし、上記貫
通孔51aの孔埋め充填が不充分である場合には、あと
で貫通孔55に銅めっきを施すとき、もしくは金属材料
57を充填するときに、金属箔51と短絡が起きるとい
う問題がある。また、後者の方法では、上記絶縁樹脂5
3は、プレス積層工程のあとで導体層54aを貼り合わ
せるときに、充分な接着力を発揮する必要がある。一方
で、後者の方法では、上記絶縁樹脂53に、金属材料5
7で厚み方向の電気導通路を形成する際の、金属材料5
7の硬化温度での耐熱性が要求される。しかも、このよ
うな両面回路基板50には、電子部品がはんだ実装搭載
されて利用されるため、上記絶縁樹脂53には、はんだ
の溶融温度(リフロー)での耐熱性が求められるととも
に、導体層54aや金属材料57の、平面方向や厚み方
向での寸法安定性を確保して、回路基板としての電気接
続信頼性を満足させる必要がある。
However, in the above-described manufacturing process, when the insulating resin 53 is press-laminated on both sides of the metal foil 51 having the through-holes 51a formed therein, the insulating resin 53 is pressed through the through-hole 51a. It is necessary to obtain a flat surface while securely filling the holes 51a. If the filling of the through-holes 51a is not sufficient, a short-circuit with the metal foil 51 occurs when the through-holes 55 are later plated with copper or filled with the metal material 57. There is. In the latter method, the insulating resin 5 is used.
No. 3 needs to exhibit sufficient adhesive strength when bonding the conductor layer 54a after the press laminating step. On the other hand, in the latter method, a metal material 5
7 to form an electrical conduction path in the thickness direction.
Heat resistance at a curing temperature of 7 is required. Moreover, since electronic components are mounted on such a double-sided circuit board 50 by solder mounting, the insulating resin 53 is required to have heat resistance at the melting temperature (reflow) of the solder, It is necessary to secure the dimensional stability of the metal material 54a and the metal material 57 in the plane direction and the thickness direction, and to satisfy the electrical connection reliability as a circuit board.

【0009】本発明は、このような事情に鑑みなされた
もので、電気接続信頼性を満足させることのできる回路
配線基板およびそれを用いた多層回路配線基板ならびに
その製造方法の提供をその目的とする。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit wiring board capable of satisfying electrical connection reliability, a multilayer circuit wiring board using the same, and a method of manufacturing the same. I do.

【0010】[0010]

【課題を解決するための手段】上記の目的を達成するた
め、本発明は、厚み方向に形成された複数の第1の貫通
孔が所定間隔で設けられている金属層と、この金属層の
両面にそれぞれ絶縁樹脂を積層し加熱加圧することによ
り金属層の両面を被覆するとともに上記第1の貫通孔の
内周面を閉塞する上記絶縁樹脂からなる絶縁樹脂層と、
上記絶縁樹脂層の両面にそれぞれ形成された電気回路配
線とからなり、上記第1の貫通孔を閉塞する上記絶縁樹
脂層の部分にその貫通孔より小さい第2の貫通孔を略同
心的に設け、この第2の貫通孔を利用して上記絶縁樹脂
層の両面にそれぞれ形成された電気回路配線を導通させ
た回路配線基板であって、上記絶縁樹脂の弾性率が、積
層加熱加圧する温度において7MPa以下である回路配
線基板を第1の要旨とし、上記回路配線基板が所定位置
で対向され、その状態で絶縁接着剤層を介して積層さ
れ、かつ、上記絶縁接着剤層の所定位置に導電路が形成
され、上記導電路により上記対向する回路配線基板の電
気回路配線が厚み方向に導通している多層回路配線基板
を第2の要旨とし、上記回路配線基板を複数枚準備する
とともに各回路配線基板の間に配設される絶縁接着剤層
を準備する工程と、上記絶縁接着剤層の所定位置に貫通
孔を形成する工程と、上記絶縁接着剤層の貫通孔の内部
に金属材料を充填する工程と、貫通孔の内部に金属材料
を充填した絶縁接着剤層を介して上記複数枚の回路配線
基板を一括積層させる工程とを備えた多層回路配線基板
の製造方法を第3の要旨とする。
In order to achieve the above-mentioned object, the present invention provides a metal layer having a plurality of first through holes formed in a thickness direction at a predetermined interval; An insulating resin layer made of the insulating resin, which covers both surfaces of the metal layer by laminating insulating resins on both surfaces and applying heat and pressure, and closing the inner peripheral surface of the first through hole;
A second through hole smaller than the through hole is provided substantially concentrically in a portion of the insulating resin layer that closes the first through hole, the second through hole comprising electric circuit wiring formed on both surfaces of the insulating resin layer. A circuit wiring board which electrically connects electric circuit wirings formed on both surfaces of the insulating resin layer using the second through-holes, wherein the elastic modulus of the insulating resin is at a temperature at which the laminate is heated and pressed. A first aspect of the present invention is a circuit wiring board having a pressure of 7 MPa or less. The circuit wiring board is opposed at a predetermined position, is laminated via an insulating adhesive layer in that state, and is electrically conductive at a predetermined position of the insulating adhesive layer. A second aspect is a multi-layer circuit wiring board in which a path is formed and the electric circuit wiring of the opposing circuit wiring board is conducted in the thickness direction by the conductive path. wiring A step of preparing an insulating adhesive layer disposed between the plates, a step of forming a through hole at a predetermined position of the insulating adhesive layer, and a step of filling a metal material into the through hole of the insulating adhesive layer A third gist of the present invention is a method for manufacturing a multilayer circuit wiring board, comprising: a step of collectively stacking the plurality of circuit wiring boards via an insulating adhesive layer in which a metal material is filled in the through hole.

【0011】本発明者らは、電気接続信頼性を満足させ
ることのできる回路配線基板を得るため、一連の研究を
行った結果、金属層の両面にそれぞれ絶縁樹脂を積層し
加熱加圧することにより金属層の両面を被覆するととも
に金属層の第1の貫通孔の内周面を閉塞する上記絶縁樹
脂からなる絶縁樹脂層として、それ自体の弾性率が、積
層加熱加圧する温度において7MPa以下である絶縁樹
脂層を用いると、回路配線基板としての電気接続信頼性
を満足させることができることを見出し、本発明に到達
した。すなわち、本発明の回路配線基板では、上記の絶
縁樹脂層を用いているため、これを構成する絶縁樹脂を
金属層の両面にプレス積層すると、上記絶縁樹脂で金属
層の両面と第1の貫通孔の内周面とを確実に絶縁するこ
とができる。しかも、プレス積層工程のあとで導体層を
貼り合わせる際にも、上記絶縁樹脂が再溶融し、充分な
接着力を発揮することができる。さらに、上記の絶縁樹
脂層に厚み方向の電気導通路を形成するために用いる金
属材料の硬化温度や、上記の絶縁樹脂層に電気回路配線
用の導体層を積層する温度や、回路配線基板同士を積層
する温度や、さらに、電子部品搭載時のはんだリフロー
温度における、上記の絶縁樹脂層の熱膨張や収縮による
寸法変化を、上記金属層によって抑止することができ
る。したがって、回路配線基板の反りや厚み方向の電気
導通路の変形を抑え、回路接続位置を安定させることに
より、より電気接続信頼性の高い回路配線基板を提供す
ることができる。
The present inventors have conducted a series of studies to obtain a circuit wiring board which can satisfy the electrical connection reliability. As a result, the present inventors have found that laminating an insulating resin on both surfaces of a metal layer and applying heat and pressure respectively. As an insulating resin layer made of the above-mentioned insulating resin, which covers both surfaces of the metal layer and closes the inner peripheral surface of the first through hole of the metal layer, the elastic modulus of itself is 7 MPa or less at a temperature at which the laminate is heated and pressed. The inventors have found that the use of an insulating resin layer can satisfy the electrical connection reliability as a circuit wiring board, and have reached the present invention. That is, in the circuit wiring board of the present invention, since the insulating resin layer described above is used, when the insulating resin constituting the same is press-laminated on both sides of the metal layer, the insulating resin forms the first through hole with both sides of the metal layer. The inner peripheral surface of the hole can be reliably insulated. In addition, even when the conductor layers are bonded after the press laminating step, the insulating resin is re-melted, and sufficient adhesive strength can be exhibited. Further, the curing temperature of a metal material used to form a thickness-direction electrical conduction path in the insulating resin layer, the temperature at which a conductor layer for electric circuit wiring is laminated on the insulating resin layer, The dimensional change due to the thermal expansion and contraction of the insulating resin layer at the temperature at which the insulating layer is laminated and at the solder reflow temperature at the time of mounting the electronic component can be suppressed by the metal layer. Therefore, it is possible to provide a circuit wiring board with higher electrical connection reliability by suppressing warping of the circuit wiring board and deformation of the electric conduction path in the thickness direction and stabilizing the circuit connection position.

【0012】また、本発明の多層回路配線基板は、上記
の回路配線基板を用いており、上記の優れた効果を奏す
る。また、本発明の多層回路配線基板の製法によれば、
上記の優れた効果を奏する多層回路配線基板を製造する
ことができる。
Further, the multilayer circuit wiring board of the present invention uses the above-mentioned circuit wiring board, and has the above-mentioned excellent effects. Further, according to the method for manufacturing a multilayer circuit wiring board of the present invention,
A multilayer circuit wiring board exhibiting the above-described excellent effects can be manufactured.

【0013】つぎに、本発明を詳しく説明する。Next, the present invention will be described in detail.

【0014】本発明の回路配線基板は、芯材となる金属
層と、電気回路配線と、絶縁樹脂層とで構成されてい
る。
The circuit wiring board according to the present invention comprises a metal layer serving as a core, an electric circuit wiring, and an insulating resin layer.

【0015】上記金属層としては、Fe,Ni,Cr,
Cu,Al,Ti,Coもしくはこれらを含む合金箔を
用いることができ、シリコンチップと回路基板との熱膨
張率差を抑制するため、特に低熱膨張率(20〜250
℃の範囲で20ppm/℃以下)を有するものを用いる
のが好ましい。また、これら金属箔は、単独でもしくは
積層して用いることができる。
As the metal layer, Fe, Ni, Cr,
Cu, Al, Ti, Co or alloy foils containing these can be used. In order to suppress the difference in the coefficient of thermal expansion between the silicon chip and the circuit board, a particularly low coefficient of thermal expansion (20 to 250) is used.
(In the range of 20 ° C / ° C or less). These metal foils can be used alone or in a laminated form.

【0016】Fe−Ni系合金箔である場合には、Fe
とNiとの成分比率により熱膨張率が異なり、本発明に
おいては、Ni含有率(重量%)は31〜50重量%、
好ましくは31〜45重量%の範囲が好適に用いられ
る。この範囲より大きいか、もしくは小さいと、回路基
板側の熱膨張率が大きく、シリコンチップと回路基板と
の熱膨張率差を抑制することができない。また、低熱膨
張金属箔の厚みは、10〜500μm、好ましくは20
〜200μmの範囲がよい。この厚みより小さいと、シ
リコンチップと回路基板との熱膨張率差を抑えることが
できない。また、この厚みより大きいと、例えば、30
0μm以下の微細孔を容易に形成することができず、高
密度回路が形成しにくくなったり、重量面で回路基板が
重くなったりして、用途面での制限が生じる。
In the case of an Fe—Ni alloy foil, Fe
The coefficient of thermal expansion differs depending on the component ratio of Ni and Ni. In the present invention, the Ni content (% by weight) is 31 to 50% by weight,
Preferably, a range of 31 to 45% by weight is suitably used. If it is larger or smaller than this range, the coefficient of thermal expansion on the circuit board side is large, and the difference in coefficient of thermal expansion between the silicon chip and the circuit board cannot be suppressed. The low thermal expansion metal foil has a thickness of 10 to 500 μm, preferably 20 to 500 μm.
The range of -200 µm is good. If the thickness is smaller than this, the difference in thermal expansion coefficient between the silicon chip and the circuit board cannot be suppressed. If the thickness is larger than this, for example, 30
Fine pores of 0 μm or less cannot be easily formed, making it difficult to form a high-density circuit, and making the circuit board heavier in terms of weight, thereby limiting applications.

【0017】上記金属層に貫通孔を形成する手段として
は、例えば、ドリル,パンチ,レーザーもしくは化学エ
ッチング等が挙げられる。
Means for forming a through hole in the metal layer include, for example, a drill, a punch, a laser, and a chemical etching.

【0018】上記絶縁樹脂層を構成する絶縁樹脂は、そ
のガラス転移温度以上で熱分解温度以下の加熱加圧によ
り溶融し、かつ、予め第1の貫通孔が形成された金属層
に積層されるとともに上記第1の貫通孔に充填される必
要がある。このような絶縁樹脂としては、耐熱性,電気
的特性等から、ポリイミド系,ポリアミド系,ポリエー
テルイミド系,エポキシ系,シリコーン系もしくはその
混合系の接着性シートが好適に用いられる。あるいは、
低吸湿のポリエステル系の熱可塑性液晶ポリマーフィル
ムを用いるのも好ましい。
The insulating resin constituting the insulating resin layer is melted by heating and pressing at a temperature not lower than its glass transition temperature but not higher than the thermal decomposition temperature, and is laminated on a metal layer in which a first through-hole is formed in advance. In addition, it is necessary to fill the first through hole. As such an insulating resin, an adhesive sheet of a polyimide type, a polyamide type, a polyetherimide type, an epoxy type, a silicone type or a mixture type thereof is preferably used from the viewpoint of heat resistance, electric characteristics and the like. Or
It is also preferable to use a polyester-based thermoplastic liquid crystal polymer film having low moisture absorption.

【0019】また、上記厚み範囲に設定された金属層の
第1の貫通孔を充填するため、積層温度での弾性率が7
MPa以下、好適には3MPa以下に設計された絶縁樹
脂が用いられる。上記弾性率は、粘弾性スペクトロメー
ター(セイコー電子社製SDM/5600)を用いて測
定する。その測定条件は、昇温:5℃/分、周波数:1
0Hz、サンプル幅:10mm、厚み:50μm、チャ
ック間距離:20mmである。上記積層温度は、特に限
定されるものではないが、回路基板上への電子部品実装
にはんだが使用されるため、180℃以上、好ましくは
200℃以上で上記弾性率を有する絶縁樹脂を用いるの
が好ましい。
Further, since the first through holes of the metal layer set in the above thickness range are filled, the elastic modulus at the lamination temperature is 7
An insulating resin designed to be equal to or less than MPa, preferably equal to or less than 3 MPa is used. The elastic modulus is measured using a viscoelastic spectrometer (SDM / 5600 manufactured by Seiko Instruments Inc.). The measurement conditions were as follows: heating: 5 ° C./min, frequency: 1
0 Hz, sample width: 10 mm, thickness: 50 μm, distance between chucks: 20 mm. The lamination temperature is not particularly limited, but since solder is used for mounting electronic components on a circuit board, an insulating resin having the above elastic modulus at 180 ° C or higher, preferably 200 ° C or higher is used. Is preferred.

【0020】また、上記絶縁樹脂の厚みは、0.01〜
1.0mm程度とするのがよい。この範囲より小さい
と、作業性が悪いうえ、上記金属層に形成された第1の
貫通孔を充分に充填することができない。また、この範
囲より大きいと、積層後に形成される第2の貫通孔の内
周に、電気導通のための金属層を形成することが難しく
なる。また、上記絶縁樹脂の積層には、熱板プレスや、
気圧で加熱加圧するオートクレープ等を利用することが
できる。加圧条件は1.5MPa以上、好適には2〜1
0MPaの範囲である。1.5MPaより小さいと、上
記金属層との接着が不充分であったり、上記金属層に形
成された第1の貫通孔を充分に充填できなかったりす
る。
The thickness of the insulating resin is 0.01 to
It is good to be about 1.0 mm. If it is smaller than this range, workability is poor and the first through hole formed in the metal layer cannot be sufficiently filled. On the other hand, if it is larger than this range, it becomes difficult to form a metal layer for electrical conduction on the inner periphery of the second through hole formed after lamination. In addition, the lamination of the insulating resin, hot plate press,
An autoclave that heats and pressurizes at atmospheric pressure can be used. The pressure condition is 1.5 MPa or more, preferably 2-1.
The range is 0 MPa. If it is less than 1.5 MPa, the adhesion to the metal layer may be insufficient, or the first through hole formed in the metal layer may not be sufficiently filled.

【0021】上記絶縁樹脂が充填された第1の貫通孔
に、より小さい径の第2の貫通孔を形成する方法として
は、その孔径によって適切な方法を用いればよいが、例
えば、ドリル,パンチ,レーザー等が挙げられる。
As a method of forming a second through-hole having a smaller diameter in the first through-hole filled with the insulating resin, an appropriate method may be used depending on the diameter of the hole. , Laser and the like.

【0022】上記絶縁樹脂に形成された第2の貫通孔に
電気導通路を形成するためには、上記第2の貫通孔の内
周面に電解めっき,無電解めっき,スパッタや蒸着によ
って金属層を形成したり、金属粉末を含有する導電ペー
ストを印刷法を用いてスキージで第2の貫通孔内部に充
填したりする方法、もしくはそれらの組み合わせが用い
られる。
In order to form an electric conduction path in the second through hole formed in the insulating resin, a metal layer is formed on the inner peripheral surface of the second through hole by electrolytic plating, electroless plating, sputtering or vapor deposition. Or a method in which a conductive paste containing a metal powder is filled in the second through-hole with a squeegee using a printing method, or a combination thereof.

【0023】上記導電ペーストを構成する金属粉末に
は、Sn,Pb,Cu,Ag,Au,Ni,Pd,Z
n,Bi,Sb,Co等の単独,合金,混合物が、必要
な耐熱性に応じて使用される。また、上記絶縁樹脂に形
成された第2の貫通孔の孔径に応じて、直径50μm以
下、好ましくは直径10μm以下のものが使用される。
特に、Snを含むはんだ材料は、積層時の加熱加圧工程
で溶融し、導電ペーストを構成する他の金属粉末や電気
回路配線を構成する金属材料と合金層を形成して、信頼
性の高い電気接続が得られる。これら金属粉末をペース
ト状にするためには、必要に応じて、樹脂バインダーや
有機溶剤が所定量混合される。
The metal powder constituting the conductive paste includes Sn, Pb, Cu, Ag, Au, Ni, Pd, Z
A single, alloy, or mixture of n, Bi, Sb, Co, etc. is used depending on the required heat resistance. In addition, the diameter of the second through hole formed in the insulating resin is 50 μm or less, preferably 10 μm or less.
In particular, the solder material containing Sn is melted in the heating and pressurizing step at the time of lamination, and forms an alloy layer with other metal powder forming the conductive paste and the metal material forming the electric circuit wiring, thereby achieving high reliability. An electrical connection is obtained. In order to make these metal powders into a paste, a predetermined amount of a resin binder or an organic solvent is mixed as necessary.

【0024】上記電気回路配線を構成する金属材料とし
ては、Cu,Ag,Au,Ni,Co等の金属箔もしく
はそれらの合金箔が用いられるが、上記絶縁樹脂層の第
2の貫通孔を形成する前もしくは形成したあとに、加熱
加圧されて上記絶縁樹脂層の両面に積層される。
As a metal material constituting the electric circuit wiring, a metal foil of Cu, Ag, Au, Ni, Co or the like or an alloy foil thereof is used, and a second through hole of the insulating resin layer is formed. Before or after forming, it is heated and pressed to be laminated on both surfaces of the insulating resin layer.

【0025】上記電気回路配線は、感光性レジスト,フ
ォトリソグラフィー法を用いて形成され、もしくは化学
エッチングやめっき等でサブトラクティブ,アディティ
ブ,セミアディティブ法で形成される。また、必要に応
じて、電気回路配線の表面に研磨,めっきや防錆処理が
施される。
The electric circuit wiring is formed by using a photosensitive resist, a photolithography method, or by a subtractive, additive, or semi-additive method by chemical etching, plating, or the like. Further, if necessary, the surface of the electric circuit wiring is polished, plated or rust-proofed.

【0026】上記のようにして得られた回路配線基板を
複数枚準備し、上記のような接着性シートを用い、複数
枚の回路配線基板を位置合わせして積層し、多層回路配
線基板を製造することができる。
A plurality of circuit wiring boards obtained as described above are prepared, and a plurality of circuit wiring boards are aligned and laminated by using the above-mentioned adhesive sheet to manufacture a multilayer circuit wiring board. can do.

【0027】この場合、上記回路配線基板の片面に、予
め貫通孔が形成された接着性シートを回路パターンに合
わせて積層したり、接着性シートを積層したのちに所定
位置にレーザー等で貫通孔を形成したりする。そのの
ち、上記貫通孔に、上記のような導電ペーストを印刷充
填して導電路を形成し、別の回路配線基板を位置合わせ
して積層することにより、多層回路配線基板を製造する
ことができる。上記導電路の露出部をバンプ状の突起に
盛り上げて形成することもできる。この場合、接続時に
加圧されたバンプは潰れて、シリコンチップもしくは回
路基板端子の凹凸形状に追随して信頼性のよい接続が可
能になる。また、上記の方法は回路配線基板を3枚以上
積層する場合にも用いることができる。
In this case, an adhesive sheet in which a through-hole is formed in advance is laminated on one surface of the circuit wiring board in accordance with the circuit pattern, or the adhesive sheet is laminated, and then the through-hole is formed at a predetermined position by a laser or the like. Or to form. Thereafter, the through-holes are printed and filled with the conductive paste as described above to form conductive paths, and another circuit wiring board is aligned and laminated, whereby a multilayer circuit wiring board can be manufactured. . The exposed portion of the conductive path can be formed by being raised to a bump-like projection. In this case, the bumps pressed at the time of connection are crushed, and the connection can be made with high reliability following the irregularities of the silicon chip or the circuit board terminal. The above method can also be used when three or more circuit wiring boards are stacked.

【0028】[0028]

【発明の実施の形態】つぎに、本発明の実施の形態を図
面にもとづいて説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

【0029】図1は本発明の多層回路配線基板の一実施
の形態を示している。図において、1はFe/Ni系合
金箔(金属層)2を芯材としたポリイミド樹脂からなる
絶縁樹脂層3(この絶縁樹脂層3の弾性率は、後述する
張り合わせ時の加熱加圧温度で7MPa以下である)の
表裏両面に銅箔からなる回路(電気回路配線)4が形成
された回路配線基板である。この実施の形態では、2枚
の回路配線基板1が用いられており、これにより、多層
回路配線基板として4層回路配線基板が作製されてい
る。5は上記各回路配線基板1に穿設された貫通孔(第
2の貫通孔)1aに銅めっき加工を施して形成したスル
ーホールめっき部(電気導通路)であり、表裏両面の回
路4を電気的に接続している。6は上記両回路配線基板
1を接着するポリイミド系接着剤層である。7は積み重
なる(上下に隣り合う)2つの回路配線基板1の回路4
を電気的に接続する導電路である。
FIG. 1 shows an embodiment of a multilayer circuit wiring board according to the present invention. In the figure, reference numeral 1 denotes an insulating resin layer 3 made of a polyimide resin having a Fe / Ni-based alloy foil (metal layer) 2 as a core material (the elastic modulus of the insulating resin layer 3 is determined by the heating and pressing temperature at the time of lamination described later). This is a circuit wiring board in which a circuit (electric circuit wiring) 4 made of copper foil is formed on both front and back surfaces of the circuit board (not more than 7 MPa). In this embodiment, two circuit wiring boards 1 are used, whereby a four-layer circuit wiring board is manufactured as a multilayer circuit wiring board. Reference numeral 5 denotes a through-hole plated portion (electrically conductive path) formed by performing a copper plating process on a through-hole (second through-hole) 1a formed in each of the circuit wiring boards 1, and the circuit 4 on both front and back sides is formed. Electrically connected. Reference numeral 6 denotes a polyimide-based adhesive layer for bonding the circuit wiring boards 1 to each other. 7 is a circuit 4 of two circuit wiring boards 1 which are stacked (adjacent vertically)
Are electrically connected to each other.

【0030】上記回路配線基板1を、例えば、つぎのよ
うにして製造することができる。すなわち、まず、Fe
/Ni系合金箔2の所定位置(スルーホールめっき部5
を設ける位置)に貫通孔(第1の貫通孔)2aを開け
(図2参照)、ついで、Fe/Ni系合金箔2の表裏両
面にポリイミド系接着シート11を用いて銅箔からなる
導体層4aを所定の加熱加圧温度で張り合わせ(図2参
照。この図2において、12は導体層4aの片面に形成
したポリイミド系絶縁樹脂層であり、上記ポリイミド系
接着シート11とともに、後述する基材8の絶縁樹脂層
3となる)、図3に示すような基材8を作製する。つぎ
に、図4に示すように、上記貫通孔2aに対応する上記
基材8の部分に、上記貫通孔2aより小さい貫通孔1a
を開ける。つぎに、この貫通孔1aに銅のスルーホール
めっきを行ってスルーホールめっき部5を設け、表裏両
面の導体層4aを電気的に接続する(図5参照)。この
ようにして得られた基材9の熱膨張率は、芯材の材料で
あるFe/Ni系合金に支配されているため、Fe/N
iの比率や箔の厚みを変えることにより上記熱膨張率を
調節することができる。つぎに、図5に示す基材9の表
裏両面の導体層4aに回路4を形成して回路配線基板1
(図6参照)を作製する。
The circuit wiring board 1 can be manufactured, for example, as follows. That is, first, Fe
/ Ni-based alloy foil 2 at predetermined position (through-hole plated portion 5
(A position where the is provided), a through-hole (first through-hole) 2 a is opened (see FIG. 2). Then, a conductor layer made of copper foil using a polyimide-based adhesive sheet 11 on both sides of the Fe / Ni-based alloy foil 2 4a are bonded together at a predetermined heating / pressing temperature (see FIG. 2. In FIG. 2, reference numeral 12 denotes a polyimide-based insulating resin layer formed on one surface of the conductor layer 4a. The substrate 8 as shown in FIG. 3 is produced. Next, as shown in FIG. 4, a through hole 1a smaller than the through hole 2a is formed in a portion of the base material 8 corresponding to the through hole 2a.
Open. Next, through-hole plating of copper is performed on the through-hole 1a to provide a through-hole plating portion 5, and the conductor layers 4a on both front and back surfaces are electrically connected (see FIG. 5). Since the coefficient of thermal expansion of the base material 9 thus obtained is governed by the Fe / Ni-based alloy which is the material of the core material, Fe / N
The coefficient of thermal expansion can be adjusted by changing the ratio of i and the thickness of the foil. Next, the circuit 4 is formed on the conductor layers 4a on both the front and back surfaces of the substrate 9 shown in FIG.
(See FIG. 6).

【0031】また、上記多層回路配線基板を、例えば、
つぎのようにして製造することができる。すなわち、ま
ず、上記のようにして作製された2枚の回路配線基板1
(図1参照)と、ポリイミド系接着剤からなる1枚の接
着シート13(図7参照)とを準備する。ついで、上記
接着シート13を(2枚のうちの)1枚の回路配線基板
1の上面に、接着シート13に穿設された貫通孔13a
を回路配線基板1の回路4の所定位置(図1の導電路7
を設ける位置)に位置合わせし仮接着する(図8参
照)。つぎに、図9に示すように、上記接着シート13
の貫通孔13aにスクリーン印刷により半田ペーストを
入れ、加熱溶融させて回路配線基板1の回路4上に半田
バンプ14を形成する。つぎに、半田バンプ14を設け
た1枚の回路配線基板1と、回路4を形成しただけの1
枚の回路配線基板1とをそれぞれ位置合わせして重ねた
のち、加熱加圧し一体化させる。この状態では、接着シ
ート13は接着剤層6となり、各半田バンプ14は導電
路7となる。これにより、2枚の回路配線基板1が積層
一体化された4層回路配線基板を得ることができる。
Further, the multilayer circuit wiring board is, for example,
It can be manufactured as follows. That is, first, the two circuit wiring boards 1 manufactured as described above are used.
(See FIG. 1) and one adhesive sheet 13 (see FIG. 7) made of a polyimide-based adhesive are prepared. Then, the adhesive sheet 13 is provided on the upper surface of one of the two circuit wiring boards 1 through the through holes 13a formed in the adhesive sheet 13.
At a predetermined position of the circuit 4 on the circuit wiring board 1 (the conductive path 7 in FIG. 1).
(The position where is provided) and temporarily adhered (see FIG. 8). Next, as shown in FIG.
A solder paste is put into the through hole 13a by screen printing, and is heated and melted to form a solder bump 14 on the circuit 4 of the circuit wiring board 1. Next, one circuit wiring board 1 provided with the solder bumps 14 and one circuit
After the two circuit wiring boards 1 are aligned with each other and overlapped, they are heated and pressed to be integrated. In this state, the adhesive sheet 13 becomes the adhesive layer 6 and each solder bump 14 becomes the conductive path 7. As a result, a four-layer circuit wiring board in which the two circuit wiring boards 1 are laminated and integrated can be obtained.

【0032】上記のように、この実施の形態では、Fe
/Ni系合金箔2の表裏両面に張り合わせる絶縁樹脂層
3として、その弾性率が上記張り合わせ時の加熱加圧温
度で7MPa以下である絶縁樹脂層を用いているため、
Fe/Ni系合金箔2の貫通孔2aを確実に絶縁するこ
とができ、電気接続信頼性に優れている。しかも、一回
の加熱加圧により2枚の回路配線基板1の一体化が行え
ると同時に、4層間の電気的接続が行える。しかも、2
層の回路4に対して、1層の割合でFe/Ni系合金箔
2が配設されているため、銅箔で回路4を構成する場合
にも、4層回路配線基板全体の熱膨張率を低くすること
ができ、極めて高い接続信頼性を得ることができる。
As described above, in this embodiment, Fe
As the insulating resin layer 3 bonded to both the front and back surfaces of the / Ni-based alloy foil 2, an insulating resin layer having an elastic modulus of 7 MPa or less at the heating and pressing temperature at the time of the bonding is used.
The through hole 2a of the Fe / Ni-based alloy foil 2 can be reliably insulated, and the electrical connection reliability is excellent. In addition, the two circuit wiring boards 1 can be integrated by one heating and pressing operation, and at the same time, the electrical connection between the four layers can be performed. Moreover, 2
Since the Fe / Ni-based alloy foil 2 is disposed at a ratio of one layer to the circuit 4 of the layer, even when the circuit 4 is formed of a copper foil, the thermal expansion coefficient of the entire four-layer circuit wiring board is increased. Can be reduced, and extremely high connection reliability can be obtained.

【0033】以下、実施例により、本発明の効果を示
す。
Hereinafter, the effects of the present invention will be described with reference to examples.

【0034】[0034]

【実施例1】まず、3,3′,4,4′−テトラカルボ
キシジフタルエーテル酸二無水物、2,2−ビス−4−
(4−アミノキシ)フェニルプロパン、末端シリコーン
変性ジアミンをモル比で1:0.85:0.15となる
ようにN−メチルピロリドン中で重合し、ポリアミド酸
溶液(固形分20重量%)を得た。これを塗工,乾燥
し、さらに300℃で処理して熱可塑性ポリイミドフィ
ルムを作製した。作製されたフィルムのガラス転移温度
は210℃,240℃での弾性率は5MPaであった。
Example 1 First, 3,3 ', 4,4'-tetracarboxydiphthalether dianhydride, 2,2-bis-4-
(4-Aminoxy) phenylpropane and a silicone-terminated diamine are polymerized in N-methylpyrrolidone in a molar ratio of 1: 0.85: 0.15 to obtain a polyamic acid solution (solid content: 20% by weight). Was. This was coated, dried and further treated at 300 ° C. to produce a thermoplastic polyimide film. The glass transition temperature of the produced film was 210 ° C., and the elastic modulus at 240 ° C. was 5 MPa.

【0035】ついで、厚み50μmのFe/Ni系合金
箔2(Ni:36重量%,Fe:64重量%、熱膨張率
1.5ppm/℃)に、直径300μm,ピッチ500
μmの貫通孔2aをドリルであけた(図2参照)。つぎ
に、このFe/Ni系2の両面に、厚み18μmの銅箔
4aと厚み25μmのフィルム12(上記熱可塑性ポリ
イミドフィルムからなる)とからなる積層材(新日鐡化
学社製:エスパックス)を、銅箔4aが外側に露出する
ように、厚み50μmの接着シート11(上記熱可塑性
ポリイミドフィルムからなる)を介して加熱加圧して
(5MPa、240℃、30分)接着した(図2参
照)。これにより、Fe/Ni系合金箔2の両面を絶縁
樹脂(フィルム12および接着シート11を構成する熱
可塑性ポリイミド)で被覆するとともに、Fe/Ni系
合金箔2の貫通孔2aを上記絶縁樹脂で充填し、フィル
ム12と接着シート11とからなる絶縁樹脂層3の両面
に銅箔4a層を形成した(図3参照)。
Then, a 50 μm-thick Fe / Ni-based alloy foil 2 (Ni: 36% by weight, Fe: 64% by weight, thermal expansion coefficient: 1.5 ppm / ° C.) was coated with a diameter of 300 μm and a pitch of 500 μm.
A μm through hole 2a was drilled (see FIG. 2). Next, on both sides of the Fe / Ni-based material 2, a laminated material composed of a copper foil 4a having a thickness of 18 μm and a film 12 (comprising the thermoplastic polyimide film) having a thickness of 25 μm (Nippon Steel Corporation: Espax) Were bonded by heating and pressing (5 MPa, 240 ° C., 30 minutes) via a 50 μm-thick adhesive sheet 11 (made of the above thermoplastic polyimide film) so that the copper foil 4 a was exposed to the outside (see FIG. 2). ). Thus, both surfaces of the Fe / Ni-based alloy foil 2 are covered with the insulating resin (the thermoplastic polyimide constituting the film 12 and the adhesive sheet 11), and the through holes 2a of the Fe / Ni-based alloy foil 2 are covered with the insulating resin. The copper foil 4a layer was formed on both surfaces of the insulating resin layer 3 composed of the film 12 and the adhesive sheet 11 after filling (see FIG. 3).

【0036】つぎに、上記貫通孔2aと同じ位置に直径
200μmの貫通孔1aをパンチャーで形成し(図4参
照)、これら各貫通孔1aの内周面に無電解めっきと電
解めっきとを用いて銅層を設け、スルーホールめっき部
5を形成した(図5参照)。つぎに、両面の銅箔4a層
にエッチング法により回路4を形成し、回路配線基板1
を作製した(図6参照)。この実施例1では、この回路
配線基板1を2枚作製した。
Next, through holes 1a having a diameter of 200 μm are formed at the same positions as the through holes 2a by a puncher (see FIG. 4), and the inner peripheral surface of each through hole 1a is formed by electroless plating and electrolytic plating. To form a through-hole plated portion 5 (see FIG. 5). Next, a circuit 4 is formed on the copper foil 4a layer on both sides by an etching method, and the circuit wiring board 1 is formed.
(See FIG. 6). In Example 1, two circuit wiring boards 1 were manufactured.

【0037】つぎに、ポリイミド系接着シート13(新
日鐡化学社製:SPB−035A)の所定位置に直径2
00μmの貫通孔13aを形成し、1枚の回路配線基板
1に位置合わせして(図7参照)、この回路配線基板1
の片側に加熱加圧接着(2MPa、175℃、30分)
した(図8参照)。つぎに、上記貫通孔13aにSn−
Pb共晶はんだペースト(日本ゲンマ社製)を印刷充填
し、220℃,1分でリフローしたのち、フラックスを
洗浄してバンプ14を形成した(図9参照)。そのの
ち、もう1枚の回路配線基板1を上記ポリイミド系接着
シート13上に位置合わせして重ね、加熱加圧(5MP
a、180℃、60分)により一体化し、4層回路配線
基板を作製した(図1参照)。
Then, the polyimide adhesive sheet 13 (SPB-035A, manufactured by Nippon Steel Chemical Co., Ltd.)
A through-hole 13a of 00 μm is formed and aligned with one circuit wiring board 1 (see FIG. 7).
Heat and pressure bonding to one side of (2MPa, 175 ° C, 30 minutes)
(See FIG. 8). Next, Sn- is inserted into the through hole 13a.
A Pb eutectic solder paste (manufactured by Nippon Genma Co., Ltd.) was printed and filled, and after reflowing at 220 ° C. for 1 minute, the flux was washed to form bumps 14 (see FIG. 9). After that, another circuit wiring board 1 is aligned and superimposed on the polyimide adhesive sheet 13 and heated and pressed (5MP).
a, 180 ° C., 60 minutes) to produce a four-layer circuit wiring board (see FIG. 1).

【0038】[0038]

【実施例2】まず、3,3′,4,4′−テトラカルボ
キシジフタルエーテル酸二無水物、1,3−ビス(3−
アミノフェノキシ)ベンゼンをモル比で1:1となるよ
うにN−メチルピロリドン中で重合し、ポリアミド酸溶
液(固形分20重量%)を得た。これを塗工,乾燥し、
さらに300℃で処理して熱可塑性ポリイミドフィルム
を作製した。作製されたフィルムのガラス転移温度は1
90℃,240℃での弾性率は6MPaであった。
Example 2 First, 3,3 ', 4,4'-tetracarboxydiphthalether dianhydride, 1,3-bis (3-
Aminophenoxy) benzene was polymerized in N-methylpyrrolidone at a molar ratio of 1: 1 to obtain a polyamic acid solution (solid content 20% by weight). This is coated and dried,
Further processing was performed at 300 ° C. to produce a thermoplastic polyimide film. The glass transition temperature of the produced film is 1
The elastic modulus at 90 ° C. and 240 ° C. was 6 MPa.

【0039】ついで、厚み100μmのFe/Ni系合
金箔22(Ni:42重量%,Fe:58重量%、熱膨
張率5.0ppm/℃)に、直径250μm,350μ
mピッチの貫通孔22aをレーザーであけた(図10参
照)。つぎに、このFe/Ni系合金箔22の両面に、
厚み18μmの銅箔24aを厚み50μmの接着シート
23a(上記熱可塑性ポリイミドフィルムからなる)を
介して加熱加圧して(5MPa、240℃、30分)接
着した(図10参照)。これにより、Fe/Ni系合金
箔22の両面を絶縁樹脂(接着シート23aを構成する
熱可塑性ポリイミド)で被覆するとともに、Fe/Ni
系合金箔22の貫通孔22aを上記絶縁樹脂で充填し、
接着シート23aからなる絶縁樹脂層23の両面に銅箔
24a層を形成した(図11参照)。
Then, the Fe / Ni-based alloy foil 22 having a thickness of 100 μm (Ni: 42% by weight, Fe: 58% by weight, thermal expansion coefficient: 5.0 ppm / ° C.) was placed on a 250 μm, 350 μm diameter.
The m-pitch through holes 22a were opened with a laser (see FIG. 10). Next, on both sides of the Fe / Ni-based alloy foil 22,
A copper foil 24a having a thickness of 18 μm was adhered by heating and pressing (5 MPa, 240 ° C., 30 minutes) via an adhesive sheet 23a (composed of the thermoplastic polyimide film) having a thickness of 50 μm (see FIG. 10). As a result, both surfaces of the Fe / Ni-based alloy foil 22 are covered with the insulating resin (the thermoplastic polyimide constituting the adhesive sheet 23a), and the Fe / Ni
Filling the through hole 22a of the system alloy foil 22 with the insulating resin,
Copper foil 24a layers were formed on both surfaces of the insulating resin layer 23 composed of the adhesive sheet 23a (see FIG. 11).

【0040】つぎに、上記貫通孔22aと同じ位置に直
径150μmの貫通孔21aを炭酸ガスレーザーで形成
し(図12参照)、これら各貫通孔21aの内周面に無
電解めっきと電解めっきとを用いて銅層を形成し、スル
ーホールめっき部25を形成した(図13参照)。つぎ
に、両面の銅箔24a層にエッチング法により回路24
を形成して回路配線基板21を作製した(図14参
照)。この実施例2では、この回路配線基板21を2枚
作製した。
Next, a through-hole 21a having a diameter of 150 μm was formed at the same position as the above-mentioned through-hole 22a by using a carbon dioxide gas laser (see FIG. 12). Was used to form a copper layer, and a through-hole plated portion 25 was formed (see FIG. 13). Next, a circuit 24 is formed on the copper foil 24a layer on both sides by etching.
Was formed to produce a circuit wiring board 21 (see FIG. 14). In Example 2, two circuit wiring boards 21 were manufactured.

【0041】つぎに、図15に示すポリイミド系接着シ
ート26(新日鐡化学社製:SPB−035A)を1枚
の回路配線基板21の片側に加熱加圧接着(2MPa、
175℃、30分)したのち、所定位置に回路24まで
達する直径200μmの貫通孔26aをYAGレーザー
で形成した(図16参照)。つぎに、上記貫通孔26a
に、Ni粉末が15重量%混合されたSn−Sbはんだ
ペースト(日本ゲンマ社製)を印刷充填し、240℃,
1分でリフローしてバンプ27を形成した(図17参
照)。そののち、もう一枚の回路配線基板21を位置合
わせして重ね、加熱加圧(5MPa、180℃、60
分)により一体化し、4層回路基板を作製した(図18
参照)。
Next, a polyimide-based adhesive sheet 26 (SPB-035A manufactured by Nippon Steel Chemical Co., Ltd.) shown in FIG. 15 was bonded to one side of one circuit wiring board 21 by heating and pressing (2 MPa,
After 175 ° C. for 30 minutes), a through hole 26 a having a diameter of 200 μm reaching the circuit 24 at a predetermined position was formed with a YAG laser (see FIG. 16). Next, the through hole 26a
Was printed and filled with a Sn-Sb solder paste (manufactured by Nippon Genma Co., Ltd.) mixed with 15% by weight of Ni powder.
Reflow was performed in one minute to form bumps 27 (see FIG. 17). After that, another circuit wiring board 21 is aligned and stacked, and heated and pressed (5 MPa, 180 ° C., 60 ° C.).
) To produce a four-layer circuit board (FIG. 18).
reference).

【0042】[0042]

【実施例3】まず、厚み100μmのFe/Ni系合金
箔32(Ni:36重量%,Fe:64重量%、熱膨張
率1.5ppm/℃)に、直径250μm,ピッチ35
0μmの貫通孔32aをレーザーであけた(図19参
照)。ついで、このFe/Ni系合金箔32の両面に、
厚み50μmの液晶性芳香族ポリエステル33(クラレ
社製:OCグレード、ガラス転移温度300℃、330
℃で弾性率は0.1MPa以下)を加熱加圧して(3M
Pa、330℃、10分)接着し、Fe/Ni系合金箔
32の両面を絶縁樹脂(液晶性芳香族ポリエステル3
3)で被覆するとともに、Fe/Ni系合金箔32の貫
通孔32aを上記絶縁樹脂で充填した(図20参照)。
Embodiment 3 First, a 100 μm-thick Fe / Ni-based alloy foil 32 (Ni: 36% by weight, Fe: 64% by weight, thermal expansion coefficient: 1.5 ppm / ° C.) has a diameter of 250 μm and a pitch of 35 μm.
A 0 μm through hole 32a was opened with a laser (see FIG. 19). Then, on both sides of the Fe / Ni-based alloy foil 32,
Liquid crystalline aromatic polyester 33 having a thickness of 50 μm (Kuraray Co., Ltd .: OC grade, glass transition temperature 300 ° C., 330
(The elastic modulus is 0.1 MPa or less at ℃)
Pa, 330 ° C., 10 minutes), and the both sides of the Fe / Ni alloy foil 32 are insulated with an insulating resin (liquid crystalline aromatic polyester 3).
3), and the through holes 32a of the Fe / Ni-based alloy foil 32 were filled with the insulating resin (see FIG. 20).

【0043】つぎに、貫通孔32aと同じ位置に直径1
50μmの貫通孔31aをYAGレーザーで形成した
(図21参照)。これら各貫通孔31aの内部に、金属
板(開孔直径200μm,厚み100μm)を用いて、
Ni粉末が15重量%混合されたSn−Sbはんだペー
スト(日本ゲンマ社製)を印刷充填した。さらに、各貫
通孔31aの両端開口をプレスし(10MPa、30
℃、2分)、上記ペーストを圧入したのち、過剰量の金
属粉末をバフ研磨により取り除いた。つぎに、加圧下で
250℃まで加温することにより電気導通路35を得た
(図22参照)。
Next, at the same position as the through hole 32a, the diameter 1
A 50 μm through hole 31a was formed with a YAG laser (see FIG. 21). Using a metal plate (opening diameter 200 μm, thickness 100 μm) inside each of the through holes 31 a,
A Sn-Sb solder paste (manufactured by Nippon Genma Co., Ltd.) mixed with 15% by weight of Ni powder was printed and filled. Further, the openings at both ends of each through hole 31a are pressed (10 MPa, 30 MPa).
After 2 minutes), the paste was press-fitted, and excess metal powder was removed by buffing. Next, the electric conduction path 35 was obtained by heating to 250 ° C. under pressure (see FIG. 22).

【0044】つぎに、上記積層物の両面に、厚み35μ
mの銅箔34aを加熱加圧して(3MPa、330℃、
10分)積層し(図23参照)、つぎに、両面の銅箔3
4a層にエッチング法により回路34を形成し、回路配
線基板31を作製した(図24参照)。この実施例3で
は、この回路配線基板31を2枚作製した。
Next, on both sides of the laminate, a thickness of 35 μm was applied.
m copper foil 34a is heated and pressurized (3 MPa, 330 ° C.,
10 minutes) laminated (see FIG. 23), and then the copper foil 3 on both sides
The circuit 34 was formed on the layer 4a by the etching method, and the circuit wiring board 31 was manufactured (see FIG. 24). In Example 3, two circuit wiring boards 31 were manufactured.

【0045】つぎに、図25に示す厚み50μmの液晶
性芳香族ポリエステル36(クラレ社製FAグレード)
を1枚の回路配線基板31の片側に加熱加圧接着(2M
Pa、290℃、10分)したのち、所定位置に回路3
4まで達する直径150μmの貫通孔36aをYAGレ
ーザーで形成した(図26参照)。つぎに、上記貫通孔
36aに、Ni粉末が15重量%混合されたSn−Sb
はんだペースト(日本ゲンマ社製)を印刷充填し、24
0℃,1分でリフローしてバンプ37を形成した(図2
7参照)。そののち、もう一枚の回路配線基板31を位
置合わせして重ね、加熱加圧(2MPa、290℃、1
0分)により一体化し、4層回路基板を作製した(図2
8参照)。
Next, a 50 μm thick liquid crystalline aromatic polyester 36 (Kuraray FA grade) shown in FIG.
To one side of one circuit wiring board 31 by heating and pressing (2M
Pa, 290 ° C., 10 minutes)
A through hole 36a having a diameter of 150 μm reaching up to 4 was formed with a YAG laser (see FIG. 26). Next, in the through hole 36a, Sn-Sb mixed with 15% by weight of Ni powder was used.
Print and fill with solder paste (Nippon Genma Co., Ltd.)
The bumps 37 were formed by reflow at 0 ° C. for 1 minute (FIG. 2).
7). After that, another circuit wiring board 31 is aligned and stacked, and heated and pressed (2 MPa, 290 ° C., 1
0 minutes) to produce a four-layer circuit board (FIG. 2).
8).

【0046】[0046]

【比較例1】まず、3,3′,4,4′−テトラカルボ
キシジフタルエーテル酸二無水物、2,2−ビス−4−
(4−アミノキシ)フェニルプロパンをモル比で1:1
となるようにN−メチルピロリドン中で重合し、ポリア
ミド酸溶液(固形分20重量%)を得た。これを塗工,
乾燥し、さらに300℃で処理して熱可塑性ポリイミド
フィルムを作製した。作製されたフィルムの250℃で
の弾性率は11MPaであった。
Comparative Example 1 First, 3,3 ', 4,4'-tetracarboxydiphthalether dianhydride, 2,2-bis-4-
(4-aminoxy) phenylpropane in a molar ratio of 1: 1
Was polymerized in N-methylpyrrolidone to obtain a polyamic acid solution (solid content: 20% by weight). Coating this,
It dried and processed at 300 degreeC, and the thermoplastic polyimide film was produced. The elastic modulus at 250 ° C. of the produced film was 11 MPa.

【0047】ついで、厚み100μmのFe/Ni系合
金箔(Ni:36重量%,Fe:64重量%、熱膨張率
1.5ppm/℃)に、直径300μm,ピッチ500
μmの貫通孔をドリルであけた。つぎに、Fe/Ni系
合金箔の両面に、厚み18μmの銅箔を厚み50μmの
接着シート(上記熱可塑性ポリイミドフィルムからな
る)を介して加熱加圧して(10MPa、250℃、3
0分)接着したが、この接着シートを構成する熱可塑性
ポリイミドを上記貫通孔に充分に充填することはできな
かった。
Then, a 100 μm thick Fe / Ni-based alloy foil (Ni: 36% by weight, Fe: 64% by weight, thermal expansion coefficient: 1.5 ppm / ° C.) was coated with a diameter of 300 μm and a pitch of 500 μm.
A through hole of μm was drilled. Next, on both surfaces of the Fe / Ni-based alloy foil, a copper foil having a thickness of 18 μm was heated and pressed through an adhesive sheet (comprising the thermoplastic polyimide film) having a thickness of 50 μm (10 MPa, 250 ° C., 3 MPa).
0 minutes), but the thermoplastic polyimide constituting this adhesive sheet could not be sufficiently filled in the through holes.

【0048】[0048]

【比較例2】液晶性芳香族ポリエステル(クラレ社製:
OCグレード、ガラス転移温度300℃、330℃で弾
性率は0.1MPa以下である)に直径150μmの貫
通孔をYAGレーザーで形成した。ついで、これら各貫
通孔の内部に、金属板(開孔直径200μm,厚み10
0μm)を用いて、Ni粉末が15重量%混合されたS
n−Sbはんだペースト(日本ゲンマ社製)を印刷充填
した。さらに、各貫通孔の両端開口をプレスして(10
MPa、30℃、2分)、上記ペーストを圧入したの
ち、過剰量の金属粉末をバフ研磨により取り除いた。つ
ぎに、加圧下で250℃まで加温することにより電気導
通路を得た。つぎに、上記積層物の両面に、厚み35μ
mの銅箔を加熱加圧して(2MPa、340℃、10
分)積層し、そののち、両面の銅箔層にエッチング法に
より回路を形成して回路配線基板を得た。この比較例2
では、この回路配線基板を2枚作製した。
Comparative Example 2 Liquid crystalline aromatic polyester (manufactured by Kuraray:
An OC grade, a glass transition temperature of 300 ° C., an elastic modulus at 330 ° C. and an elastic modulus of 0.1 MPa or less) were used to form a 150 μm diameter through-hole with a YAG laser. Next, a metal plate (opening diameter 200 μm, thickness 10 μm) is provided inside each of these through holes.
0 μm), S powder containing 15% by weight of Ni powder was used.
An n-Sb solder paste (manufactured by Nippon Genma Co., Ltd.) was printed and filled. Further, the openings at both ends of each through hole are pressed (10
(MPa, 30 ° C., 2 minutes), and after press-fitting the paste, excess metal powder was removed by buffing. Next, an electric conduction path was obtained by heating to 250 ° C. under pressure. Next, 35 μm thick on both sides of the laminate.
m copper foil is heated and pressurized (2 MPa, 340 ° C., 10
Minutes) Lamination, and then, a circuit was formed on the copper foil layers on both sides by an etching method to obtain a circuit wiring board. Comparative Example 2
Then, two circuit wiring boards were manufactured.

【0049】つぎに、厚み50μmの液晶性芳香族ポリ
エステル(クラレ社製:FAグレード)を1枚の回路配
線基板の片側に加熱加圧接着(0.2MPa、285
℃、10分)したのち、所定位置に回路まで達する直径
150μmの貫通孔をYAGレーザーで形成した。つぎ
に、上記貫通孔に、Ni粉末が15重量%混合されたS
n−Pbはんだペースト(日本ゲンマ社製)を印刷充填
し、240℃,1分でリフローしてバンプ形成した。そ
ののち、もう一枚の回路配線基板を位置合わせして重
ね、加熱加圧(1MPa、290℃、10分)により一
体化し、4層回路基板を作製した。
Next, a liquid crystalline aromatic polyester (manufactured by Kuraray Co., Ltd .: FA grade) having a thickness of 50 μm was adhered to one side of one circuit wiring board under heat and pressure (0.2 MPa, 285 mm).
(° C., 10 minutes), and a through hole having a diameter of 150 μm reaching a circuit at a predetermined position was formed with a YAG laser. Next, in the above-mentioned through-hole, S in which 15% by weight of Ni powder was mixed
An n-Pb solder paste (manufactured by Nippon Genma Co., Ltd.) was printed and filled, and reflowed at 240 ° C. for 1 minute to form bumps. Thereafter, another circuit wiring board was aligned and stacked, and integrated by heating and pressing (1 MPa, 290 ° C., 10 minutes) to produce a four-layer circuit board.

【0050】上記のようにして作製した実施例1〜3品
および比較例2品について温度衝撃試験(液層:−65
℃⇔125℃、各10分)を行い、基板の厚み方向の電
気導通を調べた。その結果を下記の表1に示す。
A temperature shock test (liquid layer: -65) was conducted on the products of Examples 1 to 3 and Comparative Example 2 produced as described above.
C. (125 ° C., 10 minutes each), and the electrical conduction in the thickness direction of the substrate was examined. The results are shown in Table 1 below.

【0051】[0051]

【表1】 [Table 1]

【0052】上記結果から明らかなように、比較例1品
のように、接着シートを構成する熱可塑性ポリイミドの
弾性率が250℃で11MPaである場合には、Fe/
Ni系合金箔の両面に銅箔を接着シートを介して加熱加
圧して接着しても、上記熱可塑性ポリイミドをFe/N
i系合金箔の貫通孔に充分に充填することができなかっ
た。また、比較例2品のように、液晶性芳香族ポリエス
テルの内部に芯材を配設していない場合には、実施例1
〜3品に比べて、基板の厚み方向の電気導通が劣ること
が判る。
As is apparent from the above results, when the elastic modulus of the thermoplastic polyimide constituting the adhesive sheet is 11 MPa at 250 ° C. as in Comparative Example 1, the Fe /
Even if a copper foil is adhered to both surfaces of a Ni-based alloy foil by applying heat and pressure through an adhesive sheet, the thermoplastic polyimide is made of Fe / N.
The through holes of the i-based alloy foil could not be sufficiently filled. Further, when the core material was not provided inside the liquid crystalline aromatic polyester as in the product of Comparative Example 2, the product of Example 1 was used.
It can be seen that the electrical conductivity in the thickness direction of the substrate is inferior to those of the three products.

【0053】[0053]

【発明の効果】以上のように、本発明の回路配線基板に
よれば、金属層の両面にそれぞれ絶縁樹脂を積層し加熱
加圧することにより金属層の両面を被覆するとともに金
属層の第1の貫通孔の内周面を閉塞する上記絶縁樹脂か
らなる絶縁樹脂層として、それ自体の弾性率が、積層加
熱加圧する温度において7MPa以下である絶縁樹脂層
を用いているため、これを構成する絶縁樹脂を金属層の
両面にプレス積層すると、上記絶縁樹脂で金属層の両面
と第1の貫通孔の内周面を確実に絶縁することができ
る。しかも、プレス積層工程のあとで導体層を貼り合わ
せる際にも、上記絶縁樹脂が再溶融し、充分な接着力を
発揮することができる。さらに、上記の絶縁樹脂層に厚
み方向の電気導通路を形成するために用いる金属材料の
硬化温度や、上記の絶縁樹脂層に電気回路配線用の導体
層を積層する温度や、回路配線基板同士を積層する温度
や、さらに、電子部品搭載時のはんだリフロー温度にお
ける、上記の絶縁樹脂層の熱膨張や収縮による寸法変化
を、上記金属層によって抑止することができる。したが
って、回路配線基板の反りや厚み方向の電気導通路の変
形を抑え、回路接続位置を安定させることにより、より
電気接続信頼性の高い回路配線基板を提供することがで
きる。
As described above, according to the circuit wiring board of the present invention, the insulating resin is laminated on both surfaces of the metal layer, and both surfaces of the metal layer are coated by heating and pressing, and the first layer of the metal layer is formed. As the insulating resin layer made of the above insulating resin that closes the inner peripheral surface of the through hole, the insulating resin layer having an elastic modulus of 7 MPa or less at the temperature of laminating heating and pressing is used. When the resin is press-laminated on both surfaces of the metal layer, both surfaces of the metal layer and the inner peripheral surface of the first through hole can be reliably insulated by the insulating resin. In addition, even when the conductor layers are bonded after the press laminating step, the insulating resin is re-melted, and sufficient adhesive strength can be exhibited. Further, the curing temperature of a metal material used to form a thickness-direction electrical conduction path in the insulating resin layer, the temperature at which a conductor layer for electric circuit wiring is laminated on the insulating resin layer, The dimensional change due to the thermal expansion and contraction of the insulating resin layer at the temperature at which the insulating layer is laminated and at the solder reflow temperature at the time of mounting the electronic component can be suppressed by the metal layer. Therefore, it is possible to provide a circuit wiring board with higher electrical connection reliability by suppressing warping of the circuit wiring board and deformation of the electric conduction path in the thickness direction and stabilizing the circuit connection position.

【0054】また、本発明の多層回路配線基板は、上記
の回路配線基板を用いており、上記の優れた効果を奏す
る。また、本発明の多層回路配線基板の製法によれば、
上記の優れた効果を奏する多層回路配線基板を製造する
ことができる。
Further, the multilayer circuit wiring board of the present invention uses the above-mentioned circuit wiring board, and exhibits the above-mentioned excellent effects. Further, according to the method for manufacturing a multilayer circuit wiring board of the present invention,
A multilayer circuit wiring board exhibiting the above-described excellent effects can be manufactured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層回路配線基板の一実施の形態を示
す断面図である。
FIG. 1 is a sectional view showing an embodiment of a multilayer circuit wiring board of the present invention.

【図2】回路配線基板の製造工程を示す断面図である。FIG. 2 is a cross-sectional view illustrating a manufacturing process of the circuit wiring board.

【図3】上記回路配線基板の製造工程を示す断面図であ
る。
FIG. 3 is a cross-sectional view illustrating a manufacturing process of the circuit wiring board.

【図4】上記回路配線基板の製造工程を示す断面図であ
る。
FIG. 4 is a cross-sectional view showing a manufacturing process of the circuit wiring board.

【図5】上記回路配線基板の製造工程を示す断面図であ
る。
FIG. 5 is a cross-sectional view showing a manufacturing process of the circuit wiring board.

【図6】上記回路配線基板の製造工程を示す断面図であ
る。
FIG. 6 is a cross-sectional view showing a manufacturing process of the circuit wiring board.

【図7】上記多層回路配線基板の製造工程を示す断面図
である。
FIG. 7 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board.

【図8】上記多層回路配線基板の製造工程を示す断面図
である。
FIG. 8 is a sectional view showing a manufacturing process of the multilayer circuit wiring board.

【図9】上記多層回路配線基板の製造工程を示す断面図
である。
FIG. 9 is a cross-sectional view illustrating a step of manufacturing the multilayer circuit wiring board.

【図10】実施例2の多層回路配線基板の製造工程を示
す断面図である。
FIG. 10 is a cross-sectional view illustrating a step of manufacturing the multilayer circuit wiring board according to the second embodiment.

【図11】上記実施例2の多層回路配線基板の製造工程
を示す断面図である。
FIG. 11 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the second embodiment.

【図12】上記実施例2の多層回路配線基板の製造工程
を示す断面図である。
FIG. 12 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the second embodiment.

【図13】上記実施例2の多層回路配線基板の製造工程
を示す断面図である。
FIG. 13 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the second embodiment.

【図14】上記実施例2の多層回路配線基板の製造工程
を示す断面図である。
FIG. 14 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the second embodiment.

【図15】上記実施例2の多層回路配線基板の製造工程
を示す断面図である。
FIG. 15 is a cross-sectional view illustrating a step of manufacturing the multilayer circuit wiring board of the second embodiment.

【図16】上記実施例2の多層回路配線基板の製造工程
を示す断面図である。
FIG. 16 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the second embodiment.

【図17】上記実施例2の多層回路配線基板の製造工程
を示す断面図である。
FIG. 17 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the second embodiment.

【図18】上記実施例2の多層回路配線基板を示す断面
図である。
FIG. 18 is a cross-sectional view illustrating the multilayer circuit wiring board according to the second embodiment.

【図19】実施例3の多層回路配線基板の製造工程を示
す断面図である。
FIG. 19 is a cross-sectional view illustrating a step of manufacturing the multilayer circuit wiring board of the third embodiment.

【図20】上記実施例3の多層回路配線基板の製造工程
を示す断面図である。
FIG. 20 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the third embodiment.

【図21】上記実施例3の多層回路配線基板の製造工程
を示す断面図である。
FIG. 21 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the third embodiment.

【図22】上記実施例3の多層回路配線基板の製造工程
を示す断面図である。
FIG. 22 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the third embodiment.

【図23】上記実施例3の多層回路配線基板の製造工程
を示す断面図である。
FIG. 23 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the third embodiment.

【図24】上記実施例3の多層回路配線基板の製造工程
を示す断面図である。
FIG. 24 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the third embodiment.

【図25】上記実施例3の多層回路配線基板の製造工程
を示す断面図である。
FIG. 25 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the third embodiment.

【図26】上記実施例3の多層回路配線基板の製造工程
を示す断面図である。
FIG. 26 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the third embodiment.

【図27】上記実施例3の多層回路配線基板の製造工程
を示す断面図である。
FIG. 27 is a cross-sectional view showing a step of manufacturing the multilayer circuit wiring board of the third embodiment.

【図28】上記実施例3の多層回路配線基板を示す断面
図である。
FIG. 28 is a sectional view showing the multilayer circuit wiring board of the third embodiment.

【図29】従来例を示す断面図である。FIG. 29 is a sectional view showing a conventional example.

【図30】上記従来例の作製方法を示す断面図である。FIG. 30 is a cross-sectional view showing a manufacturing method of the conventional example.

【図31】他の従来例を示す断面図である。FIG. 31 is a sectional view showing another conventional example.

【符号の説明】[Explanation of symbols]

1 回路配線基板 1a 第2の貫通孔 2 金属層 2a 第1の貫通孔 3 絶縁樹脂層 4 電気回路配線 DESCRIPTION OF SYMBOLS 1 Circuit wiring board 1a 2nd through hole 2 Metal layer 2a 1st through hole 3 Insulating resin layer 4 Electric circuit wiring

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 1/09 H05K 1/09 A 3/46 3/46 T S (72)発明者 大田 真也 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 (72)発明者 桶結 卓司 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 Fターム(参考) 4E351 AA01 BB01 BB24 BB26 BB31 CC11 DD24 GG06 5E315 AA05 AA11 BB01 BB14 CC16 CC21 DD07 DD13 DD17 DD20 GG03 GG07 5E317 AA24 BB01 BB05 BB18 CC25 CC53 CD21 CD27 CD32 GG11 GG16 5E346 AA12 AA15 CC08 CC10 CC31 CC32 CC37 CC40 CC41 DD12 EE06 EE09 FF07 FF15 FF17 FF18 GG15 HH08 HH11 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 1/09 H05K 1/09 A 3/46 3/46 TS (72) Inventor Shinya Ota Ibaraki, Osaka 1-1-2 Shimohozumi, Ichito Nitto Denko Corporation (72) Inventor Takuji Okei 1-1-2 Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation F-term (reference) 4E351 AA01 BB01 BB24 BB26 BB31 CC11 DD24 GG06 5E315 AA05 AA11 BB01 BB14 CC16 CC21 DD07 DD13 DD17 DD20 GG03 GG07 5E317 AA24 BB01 BB05 BB18 CC25 CC53 CD21 CD27 CD32 GG11 GG16 5E346 AA12 AA15 CC08 CC10 CC31 CC32 CC37 CC06 CC41 DD17 FFFFFFH FFFFFFFFH

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 厚み方向に形成された複数の第1の貫通
孔が所定間隔で設けられている金属層と、この金属層の
両面にそれぞれ絶縁樹脂を積層し加熱加圧することによ
り金属層の両面を被覆するとともに上記第1の貫通孔の
内周面を閉塞する上記絶縁樹脂からなる絶縁樹脂層と、
上記絶縁樹脂層の両面にそれぞれ形成された電気回路配
線とからなり、上記第1の貫通孔を閉塞する上記絶縁樹
脂層の部分にその貫通孔より小さい第2の貫通孔を略同
心的に設け、この第2の貫通孔を利用して上記絶縁樹脂
層の両面にそれぞれ形成された電気回路配線を導通させ
た回路配線基板であって、上記絶縁樹脂の弾性率が、積
層加熱加圧する温度において7MPa以下であることを
特徴とする回路配線基板。
1. A metal layer in which a plurality of first through holes formed in a thickness direction are provided at predetermined intervals, and an insulating resin is laminated on both surfaces of the metal layer and heated and pressed to form a metal layer. An insulating resin layer made of the insulating resin covering both surfaces and closing an inner peripheral surface of the first through hole;
A second through hole smaller than the through hole is provided substantially concentrically in a portion of the insulating resin layer that closes the first through hole, the second through hole comprising electric circuit wiring formed on both surfaces of the insulating resin layer. A circuit wiring board which electrically connects electric circuit wirings formed on both surfaces of the insulating resin layer using the second through-holes, wherein the elastic modulus of the insulating resin is at a temperature at which the laminate is heated and pressed. A circuit wiring board having a pressure of 7 MPa or less.
【請求項2】 上記積層加熱加圧温度が180℃以上で
ある請求項1記載の回路配線基板。
2. The circuit wiring board according to claim 1, wherein said laminating heating / pressing temperature is 180 ° C. or higher.
【請求項3】 上記第2の貫通孔が、金属材料で閉塞さ
れた電気導通路に形成され、かつ、上記第2の貫通孔の
両端開口が電気回路配線で閉塞されている請求項1また
は2記載の回路配線基板。
3. The second through hole is formed in an electric conduction path closed with a metal material, and both ends of the second through hole are closed with electric circuit wiring. 2. The circuit wiring board according to 2.
【請求項4】 上記金属層の熱膨張係数が、20〜25
0℃の範囲で20ppm/℃以下である請求項1〜3の
いずれか一項に記載の回路配線基板。
4. The thermal expansion coefficient of the metal layer is 20 to 25.
The circuit wiring board according to claim 1, wherein the temperature is 20 ppm / ° C. or less in a range of 0 ° C. 5.
【請求項5】 上記金属層がFe/Ni系合金箔であ
り、Ni含有量が31〜50重量%の範囲で、かつ、そ
の厚みが10〜500μmの範囲である請求項1〜4の
いずれか一項に記載の回路配線基板。
5. The metal layer according to claim 1, wherein the metal layer is an Fe / Ni-based alloy foil, the Ni content is in the range of 31 to 50% by weight, and the thickness is in the range of 10 to 500 μm. The circuit wiring board according to claim 1.
【請求項6】 上記金属材料が300℃以下で溶融する
はんだ材料を含んでいる請求項3記載の回路配線基板。
6. The circuit wiring board according to claim 3, wherein the metal material includes a solder material that melts at 300 ° C. or less.
【請求項7】 上記絶縁樹脂層が、その熱分解温度以下
で繰り返し溶融する熱可塑性樹脂を主成分としている請
求項1〜6のいずれか一項に記載の回路配線基板。
7. The circuit wiring board according to claim 1, wherein the insulating resin layer is mainly composed of a thermoplastic resin that repeatedly melts at a temperature lower than its thermal decomposition temperature.
【請求項8】 上記絶縁樹脂層が、熱可塑性液晶ポリマ
ーである請求項1〜7のいずれか一項に記載の回路配線
基板。
8. The circuit wiring board according to claim 1, wherein the insulating resin layer is a thermoplastic liquid crystal polymer.
【請求項9】 請求項1〜8のいずれか一項に記載され
た回路配線基板が所定位置で対向され、その状態で絶縁
接着剤層を介して積層され、かつ、上記絶縁接着剤層の
所定位置に導電路が形成され、上記導電路により上記対
向する回路配線基板の電気回路配線が厚み方向に導通し
ていることを特徴とする多層回路配線基板。
9. The circuit wiring board according to claim 1, wherein the circuit wiring board is opposed at a predetermined position, and is laminated with an insulating adhesive layer interposed therebetween in that state. A multilayer circuit wiring board, wherein a conductive path is formed at a predetermined position, and the electric circuit wiring of the opposing circuit wiring board is conducted in the thickness direction by the conductive path.
【請求項10】 請求項1〜8のいずれか一項に記載さ
れた回路配線基板を複数枚準備するとともに各回路配線
基板の間に配設される絶縁接着剤層を準備する工程と、
上記絶縁接着剤層の所定位置に貫通孔を形成する工程
と、上記絶縁接着剤層の貫通孔の内部に金属材料を充填
する工程と、貫通孔の内部に金属材料を充填した絶縁接
着剤層を介して上記複数枚の回路配線基板を一括積層さ
せる工程とを備えたことを特徴とする多層回路配線基板
の製造方法。
10. A step of preparing a plurality of circuit wiring boards according to claim 1 and preparing an insulating adhesive layer disposed between the circuit wiring boards.
A step of forming a through hole at a predetermined position of the insulating adhesive layer, a step of filling a metal material inside the through hole of the insulating adhesive layer, and an insulating adhesive layer filled with a metal material inside the through hole And a step of collectively laminating the plurality of circuit wiring boards through the method.
JP2000268157A 2000-09-05 2000-09-05 Circuit wiring board and multilayer circuit wiring board using the same as well as its manufacturing method Pending JP2002076557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000268157A JP2002076557A (en) 2000-09-05 2000-09-05 Circuit wiring board and multilayer circuit wiring board using the same as well as its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000268157A JP2002076557A (en) 2000-09-05 2000-09-05 Circuit wiring board and multilayer circuit wiring board using the same as well as its manufacturing method

Publications (1)

Publication Number Publication Date
JP2002076557A true JP2002076557A (en) 2002-03-15

Family

ID=18754966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000268157A Pending JP2002076557A (en) 2000-09-05 2000-09-05 Circuit wiring board and multilayer circuit wiring board using the same as well as its manufacturing method

Country Status (1)

Country Link
JP (1) JP2002076557A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7301108B2 (en) 2002-02-05 2007-11-27 International Business Machines Corporation Multi-layered interconnect structure using liquid crystalline polymer dielectric
JP2010108576A (en) * 2008-10-31 2010-05-13 Nitto Denko Corp Suspension substrate with circuit
JP2010108575A (en) * 2008-10-31 2010-05-13 Nitto Denko Corp Suspension substrate with circuit
JP2011077270A (en) * 2009-09-30 2011-04-14 Sumitomo Chemical Co Ltd Metal base circuit board

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7301108B2 (en) 2002-02-05 2007-11-27 International Business Machines Corporation Multi-layered interconnect structure using liquid crystalline polymer dielectric
US7777136B2 (en) 2002-02-05 2010-08-17 International Business Machines Corporation Multi-layered interconnect structure using liquid crystalline polymer dielectric
US7981245B2 (en) 2002-02-05 2011-07-19 International Business Machines Corporation Multi-layered interconnect structure using liquid crystalline polymer dielectric
JP2010108576A (en) * 2008-10-31 2010-05-13 Nitto Denko Corp Suspension substrate with circuit
JP2010108575A (en) * 2008-10-31 2010-05-13 Nitto Denko Corp Suspension substrate with circuit
US8587904B2 (en) 2008-10-31 2013-11-19 Nitto Denko Corporation Suspension board with circuit having a light emitting device exposed from a surface thereof opposite to that on which a slider is mounted
US8593823B2 (en) 2008-10-31 2013-11-26 Nitto Denko Corporation Suspension board with circuit
US8767352B2 (en) 2008-10-31 2014-07-01 Nitto Denko Corporation Suspension board with circuit having an opening extending therethrough in the thickness direction for light emitted from a light emitting device
JP2011077270A (en) * 2009-09-30 2011-04-14 Sumitomo Chemical Co Ltd Metal base circuit board

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