JP3051700B2 - Manufacturing method of the head protection multilayer wiring board - Google Patents

Manufacturing method of the head protection multilayer wiring board

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Publication number
JP3051700B2
JP3051700B2 JP9201653A JP20165397A JP3051700B2 JP 3051700 B2 JP3051700 B2 JP 3051700B2 JP 9201653 A JP9201653 A JP 9201653A JP 20165397 A JP20165397 A JP 20165397A JP 3051700 B2 JP3051700 B2 JP 3051700B2
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Prior art keywords
wiring board
wiring circuit
insulating
resin
step
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JPH1145955A (en
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桂 林
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京セラ株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、例えば、多層配線基板及び半導体素子収納用パッケージなどに適し、特に絶縁基板内部に電気素子が内蔵されてなる多層配線基板の製造方法に関するものである。 The present invention relates to, for example, suitable such multilayer wiring board and the semiconductor device package for housing, a method for manufacturing a multilayer wiring board comprising a built-in particular an insulating substrate inside the electric element.

【0002】 [0002]

【従来技術】従来より、電子機器は小型化が進んでいるが、近年携帯情報端末の発達や、コンピューターを持ち運んで操作する、いわゆるモバイルコンピューティングの普及によってさらに小型、薄型且つ高精細の多層配線基板が求められる傾向にある。 Of the Prior Art Conventionally, the electronic apparatus is progressing miniaturization, development and the recent portable information terminals, operated carrying your computer, even smaller the spread of so-called mobile computing, thin and high-definition multi-layer wiring the substrate tends to be required.

【0003】従来のプリント配線基板では、プリプレグと呼ばれる有機樹脂を含む平板の表面に銅箔を接着した後、これをエッチングして微細な回路を形成し、これを積層した後、所望位置にマイクロドリルでスルーホールの穴明けを行い、そのホール内壁にメッキ法により金属を付着させてスルーホール導体を形成して各層間の電気的な接続を行っている。 [0003] In the conventional printed wiring board, after bonding the copper foil on the surface of plates containing organic resin called prepreg, after which is etched to form a fine circuit, a laminate of this micro the desired position perform drilling of through holes by drilling, by attaching metal to form through-hole conductors are made electrical connection between layers by plating on the hole inner wall.

【0004】ところが、この方法では、スルーホール導体は配線基板全体にわたり貫通したものであるために、 [0004] However, since in this method, through-hole conductors is obtained by penetrating throughout the wiring board,
積層数が増加するに伴い、スルーホール数が増加すると、配線に必要なスペースが確保できなくなるという問題が生じ、電子機器の軽量、小型化に伴うプリント基板の薄層化、小型化、軽量化に対しては、対応できないのが現状である。 As the number of stacked layers increases, the number of through holes is increased, there is a problem in that space required can not be ensured on the wiring, lightweight electronic devices, thinning of a printed circuit board with the miniaturization, size reduction, weight reduction for, I can not support at present.

【0005】そこで、最近では、絶縁層に対して形成したビアホール内に金属粉末を充填してビアホール導体を形成した後、他の絶縁層を積層して多層化した配線基板が提案されている。 [0005] Therefore, recently, after forming the via-hole conductors by filling a metal powder in the via holes formed on the insulating layer, a wiring board having a multilayer structure by stacking another insulating layer has been proposed.

【0006】また、従来のプリント配線基板に対して、 [0006] In addition, for the conventional printed wiring board,
半導体素子やコンデンサ素子、抵抗素子などを実装する場合には、配線基板の表面に形成された配線回路層に対してこれらの電気素子を半田等により実装し、実装した素子を樹脂によってモールドする方法、絶縁基板の表面に凹部を形成して、その凹部内に素子を収納して樹脂モールドしたり、蓋体によって凹部を気密に封止する方法がある。 Semiconductor devices and the capacitor element, when implementing such resistance elements, how these electrical elements mounted by soldering or the like to the wiring circuit layer formed on the surface of the wiring board, molding the mounting the device by resin , by forming a concave portion on the surface of the insulating substrate, or a resin mold accommodating the element in its recess, there is a method of sealing a recess hermetically by the lid.

【0007】 [0007]

【発明が解決しようとする課題】しかしながら、ビアホール導体を金属粉末の充填によって形成する方法は、ビアホール導体の小径化が可能であるとともに、任意の位置に配設できる点で配線基板の小型化に対しては有効であるが、配線基板をより多層化したとしても、その配線基板に搭載する素子は、配線基板の表面にしか実装することができないために、配線基板の小型化には自ずと限界があった。 [SUMMARY OF THE INVENTION However, the via-hole conductors way be formed by filling the metal powder, together with a possible diameter of the via-hole conductors, the miniaturization of the wiring board in that it can provided at an arbitrary position Although effective for, even a wiring board and more multilayered, components mounted on the wiring board, because it can not be implemented only on the surface of the wiring substrate, a limit to the miniaturization of the wiring substrate was there.

【0008】従って、本発明は、半導体素子や電子部品(コンデンサ素子、抵抗素子、フィルター素子、発振素子など)の電気素子を搭載する多層配線基板において、 Accordingly, the present invention relates to a semiconductor device and electronic component (a capacitor element, a resistor element, a filter element, such as an oscillation element) in the multilayer wiring board for mounting an electrical device,
基板の小型化と、素子の実装密度を高めることのできる多層配線基板を容易に作製することのできる素子内蔵多層配線基板の製造方法を提供することを目的とするものである。 And downsizing of the substrate, it is an object to provide a manufacturing method of the head protection multilayer wiring board capable of manufacturing a multilayer wiring board capable of enhancing the mounting density of the elements easily.

【0009】 [0009]

【課題を解決するための手段】本発明者は、電気素子を搭載した配線基板の小型化について検討を重ねた結果、 The present inventors SUMMARY OF THE INVENTION As a result of studying on miniaturization of a wiring board mounted with electric elements,
配線基板内に、電気素子を実装収納するための空隙部を形成することにより、配線基板のより多くの電気素子を搭載した小型の配線基板を提供できること、さらには、 In the wiring substrate, by forming a gap portion for mounting accommodating the electric element, it can be provided a small-sized wiring board having more electrical elements of the wiring substrate, and further,
配線基板を作製するにあたり、金属箔からなる配線回路層を転写シートからの転写によって形成する際に、転写シート上の銅箔に予め電気素子を半田などで接続した後に、空隙部を形成した絶縁層に転写することで、絶縁層に何ら影響を及ぼすことなく、素子を内蔵した配線基板を作製できることを見いだし、本発明に至った。 In fabricating the wiring substrate, when forming the transcription of the wiring circuit layer made of a metal foil from the transfer sheet, after pre-connected electrical devices solder or the like to a copper foil on the transfer sheet, to form an air gap insulation by transferring the layer, without any influence on the insulating layer, found to be able to produce a wiring board with a built-in element, it has led to the present invention.

【0010】即ち、本発明の素子内蔵多層配線基板の製造方法は、転写シートの表面に形成された配線回路層に電気素子を実装する実装工程と、少なくとも熱硬化性樹脂からなる第1の絶縁層にキャビティを形成するキャビティ形成工程と、前記第1の絶縁層の前記キャビティ内に前記電気素子が収納されるように、前記転写シートから前記配線回路層と前記電気素子を前記第1の絶縁層に転写する転写工程と、転写工程後の前記第1の絶縁層の上下面に、少なくとも熱硬化性樹脂を含む第2および第3の絶縁層を積層圧着する積層工程と、該積層物を一括して熱硬化させる工程と、を具備することを特徴とするものである。 [0010] That is, the manufacturing method of the head protection multilayer wiring board of the present invention includes a mounting step of mounting an electrical element on the wiring circuit layer formed on the surface of the transfer sheet, a first insulating made of at least a thermosetting resin a cavity forming step of forming a cavity in the layer, the first so that the electric element in said cavity of the insulating layer is housed, said first insulating the electrical element and the wiring circuit layer from the transfer sheet a transfer step of transferring the layer, the upper and lower surfaces of the first insulating layer after the transfer step, a laminating step of laminating crimping the second and third insulating layers including at least a thermosetting resin, the laminated product it is characterized in that it comprises a and a step of thermally curing collectively.

【0011】 [0011]

【発明の実施の形態】以下、本発明を図面をもとに説明する。 BEST MODE FOR CARRYING OUT THE INVENTION The following describes the present invention based on the drawings. 図1は、本発明の素子内蔵多層配線基板を製造するための製造工程を説明するための図である。 Figure 1 is a diagram for explaining a manufacturing process for manufacturing a device built multilayer wiring board of the present invention.

【0012】図1によれば、まず、図1(a)に示すように、熱硬化性樹脂を含む軟質(Bステージ状態)の第1の絶縁シート1を作製する。 According to FIG. 1, first, as shown in FIG. 1 (a), to produce a first insulation sheet 1 a soft (B stage state) containing a thermosetting resin. また、この絶縁シート1 In addition, the insulating sheet 1
には、所望により厚み方向に貫通するスルーホールを形成し、そのスルーホール内に金属粉末を含む導体ペーストをスクリーン印刷や吸引処理しながら充填して、ビアホール導体2を形成する。 The optionally forming a through hole penetrating in the thickness direction, a conductive paste containing a metal powder into the through-holes are filled with screen printing or suction process to form a via hole conductors 2. また、この絶縁シート1の所定箇所に電気素子を収納するための空隙部3を形成する。 Further, to form an air gap 3 for accommodating an electric element in a predetermined position of the insulating sheet 1.

【0013】次に、図1(b)に示すように、絶縁シート1の表面に配線回路層4を形成するとともに、絶縁シート1の空隙部に電気素子5を実装収納する。 [0013] Next, as shown in FIG. 1 (b), to form the wiring circuit layers 4 on the surface of the insulating sheet 1, the electric element 5 is mounted accommodated in the gap portion of the insulating sheet 1. 配線回路層4は、1)絶縁シート1の表面に金属箔を貼り付けた後、エッチング処理して回路パターンを形成する方法、 The wiring circuit layers 4, 1) after attaching a metal foil on the surface of the insulating sheet 1, a method of forming a circuit pattern by etching,
2)絶縁シート1表面にレジストを形成して、メッキにより形成する方法、3)転写フィルム表面に金属箔を貼り付け、金属箔をエッチング処理して回路パターンを形成した後、この金属箔からなる回路パターンを絶縁シート1表面に転写させる方法等が挙げられる。 2) forming a resist on the insulating sheet 1 surface, a method of forming by plating, 3) adhered to a metal foil on the transfer film surface, after forming a circuit pattern of the metal foil by etching, comprising the metal foil the method or the like to transfer the circuit pattern on the insulating sheet 1 surface thereof.

【0014】本製造方法においては、配線回路層4と、 [0014] In this manufacturing method, the wiring circuit layers 4,
配線回路層4に電気素子5を実装した構造物を転写フィルムから絶縁シート1に転写させる。 The structure in the wiring circuit layers 4 mounting the electric element 5 from the transfer film is transferred onto the insulating sheet 1. その具体的な方法を図1(b1)〜(b3)に示す。 The specific method is shown in FIG. 1 (b1) ~ (b3). この方法によれば、 According to this method,
例えば、樹脂や金属からなる転写フィルム6の表面に金属箔を接着した後、エッチングして配線回路層4を形成する(図1(b1))。 For example, after bonding the metal foil to the surface of the transfer film 6 made of resin or metal, it is etched to form a wiring circuit layers 4 (FIG. 1 (b1)). その後、その配線回路層4に、 Then, the wiring circuit layers 4,
電気素子5を半田、TAB、ワイヤーボンディングにより実装する(図1(b2))。 The electric element 5 soldering, TAB, implemented by wire bonding (Fig. 1 (b2)).

【0015】その後、電気素子5が実装された転写フィルム6を絶縁シート1に対して、電気素子5が絶縁シート1の空隙部3に収納されるように積層して圧着した後、転写フィルム6を剥がして(図1(b3))、配線回路層4と電気素子5とを絶縁シート1に転写させて、 [0015] Then, the insulating transfer film 6 to the electric element 5 is mounted sheet 1, after the electric element 5 is crimped stacked so is accommodated in the gap portion 3 of the insulation sheet 1, the transfer film 6 the peeled (FIG. 1 (b3)), the wiring circuit layers 4 and the electric element 5 is transferred to the insulating sheet 1,
図1(b)に示すような電気素子5が空隙部3に実装収納された単層の配線層を形成することができる。 Figure 1 (b) the electrical device 5, as shown in it is possible to form a wiring layer of a single layer implemented housed in the gap portion 3. この時、絶縁シート1は、未硬化または半硬化状態であり軟質であることから、配線回路層4を圧着することにより、絶縁シート1の表面に埋め込むことができるとともに、絶縁シート1に形成されたビアホール導体2を緻密化することができる。 At this time, the insulating sheet 1, since it is uncured or semi-cured state soft, by crimping the wiring circuit layers 4, it is possible to embed the surface of the insulating sheet 1, it is formed in the insulating sheet 1 and the via-hole conductors 2 can be densified.

【0016】また、上記の例では、基本的には、電気素子5を実装する配線回路層4は、電気素子5とともに、 Further, in the above example, basically, the wiring circuit layers 4 to implement the electrical element 5, together with the electric element 5,
同時に転写させるものであるが、電気素子5の実装に関与しない配線回路層(図示せず)は、電気素子5と配線回路層4とともに同時するか、または個別に前述した1)〜3)のいずれの方法で形成してもよい。 But it is intended to be simultaneously transferred, the wiring circuit layer that is not involved in the implementation of the electric element 5 (not shown), either simultaneously with the electric element 5 with the wiring circuit layers 4, or separately described above 1) to 3) of it may be formed by any method. また、空隙部3内に収納された電気素子5は、配線回路層4に実装された状態でエポキシ樹脂等により封止してもよい。 The electric element 5 housed in the gap portion 3 may be sealed by epoxy resin or the like in a state of being mounted on the wiring circuit layers 4.

【0017】次に、上記のように空隙部3内に電気素子5が実装収納された絶縁シート1の上下面に、軟化状態(Bステージ状態)の第2および第3の絶縁シート7、 Next, the upper and lower surfaces of the insulation sheet 1 is electric element 5 into the gap portion 3 mounted housing as described above, the second and third insulating sheet 7 of softened (B stage state),
8を積層圧着して、絶縁シート1、7、8中の熱硬化性樹脂が硬化するに十分な温度に加熱して一括して完全硬化させる。 8 are laminated crimped to completely cure collectively by heating to a temperature sufficient to cure the thermosetting resin in the insulating sheet 1,7,8. なお、絶縁シート7、8には、配線回路層9、10やビアホール導体11、12を前述した方法により適宜形成してもよい。 Note that the insulating sheet 7 and 8 may be suitably formed by the method of the wiring circuit layers 9 and 10 and via conductors 11 and 12 described above. このようにして、図1(c) Thus, FIG. 1 (c)
に示すように、絶縁基板13内に電気素子5を内蔵する多層配線基板を形成することができる。 As shown, it is possible to form a multilayer wiring board having a built-in electrical element 5 in the insulating substrate 13.

【0018】また、本発明によれば、上記素子内蔵多層配線基板の製造方法を基礎として、あらゆる形態の多層配線基板を作製することができる。 Further, according to the present invention, on the basis of the manufacturing method of the element built-in multilayer wiring board, it is possible to create a multilayer wiring board of any form. 例えば、図2に示すように、多層配線基板の絶縁基板32内において、IC For example, as shown in FIG. 2, the insulating substrate 32 of the multilayer wiring board, IC
素子33やコンデンサ34等のなどの電気素子を収納する空隙部35、36を同一面内、または異なる層内に空隙部37を複数箇所形成して、これら複数の電気素子を実装収納させることができる。 Same plane a gap portion 35 for accommodating the electric element such as such as elements 33 and capacitor 34, or in different layers with an air gap portion 37 and a plurality of locations forming, be implemented housing the plurality of electrical elements it can. また、絶縁基板32の表面にも、他の電気素子38、39を表面実装することができる。 Moreover, even the surface of the insulating substrate 32, other electric elements 38 and 39 can be surface-mounted. その結果、表面のみならず、絶縁基板内部にも電気素子を高密度に実装した多層配線基板を作製することができる。 As a result, not only the surface, it is possible to manufacture a multilayer wiring board densely packed electrical device also inside the insulating substrate.

【0019】上記製造方法において、用いられる熱硬化性樹脂を含有する絶縁シートは、熱硬化性有機樹脂、または熱硬化性有機樹脂とフィラーなどの組成物を混練機や3本ロールなどの手段によって十分に混合し、これを圧延法、押し出し法、射出法、ドクターブレード法などによってシート状に成形する。 In the above manufacturing method, an insulating sheet containing a thermosetting resin to be used is, by means of a thermosetting organic resin, or a composition such as a thermosetting organic resin and a filler such as kneader or three-roll mix thoroughly, rolling method this extrusion method, an injection method and formed into a sheet by a doctor blade method. そして、所望により熱処理して熱硬化性樹脂を半硬化させる。 The semi-curing the desired heat treated thermosetting resin. 半硬化には、樹脂が完全硬化するに十分な温度よりもやや低い温度に加熱する。 The semi-cured, the resin is heated to a temperature slightly lower than the temperature sufficient to complete cure.

【0020】そして、この状態の絶縁層に対するスルーホール(ビアホール)および空隙部の形成は、ドリル、 [0020] Then, formation of the through hole (via hole) and the void portion to the insulating layer in this state, the drill,
パンチング、サンドブラスト、あるいは炭酸ガスレーザ、YAGレーザ、及びエキシマレーザ等の照射による加工など公知の方法が採用される。 Punching, sandblast or carbon dioxide laser,, YAG laser, and a known method such as processing by the irradiation of an excimer laser or the like is employed.

【0021】なお、絶縁シートを形成する熱硬化性樹脂としては、絶縁材料としての電気的特性、耐熱性、および機械的強度を有する熱硬化性樹脂であれば特に限定されるものでなく、例えば、アラミド樹脂、フェノール樹脂、エポキシ樹脂、イミド樹脂、フッ素樹脂、フェニレンエーテル樹脂、ビスマイレイドトリアジン樹脂、ユリア樹脂、メラミン樹脂、シリコーン樹脂、ウレタン樹脂、不飽和ポリエステル樹脂、アリル樹脂等が、単独または組み合わせて使用できる。 [0021] As the thermosetting resin constituting the insulating sheet, electric properties as an insulating material, heat resistance, and not limited in particular as long as the thermosetting resin having mechanical strength, e.g. , aramid resin, phenol resin, epoxy resin, imide resin, fluororesin, polyphenylene ether resin, bis Mai laid triazine resins, urea resins, melamine resins, silicone resins, urethane resins, unsaturated polyester resins, allyl resins, and, alone or in in combination it can be used.

【0022】また、上記の絶縁シート1中には、絶縁基板あるいは配線基板全体の強度を高めるために、有機樹脂に対してフィラーを複合化させることもできる。 Further, during the above-mentioned insulating sheet 1, in order to increase the strength of the entire insulating substrate or wiring board, fillers may also be conjugated to an organic resin. 有機樹脂と複合化されるフィラーとしては、SiO 2 、Al 2 The filler with an organic resin is complexed, SiO 2, Al 2
3 、ZrO 2 、TiO 2 、AlN、SiC、BaTi O 3, ZrO 2, TiO 2 , AlN, SiC, BaTi
3 、SrTiO 3 、ゼオライト、CaTiO 3 、ほう酸アルミニウム等の無機質フィラーが好適に用いられる。 O 3, SrTiO 3, zeolite, CaTiO 3, inorganic fillers such as aluminum borate is suitably used.
また、ガラスやアラミド樹脂からなる不織布、織布などに上記樹脂を含浸させて用いてもよい。 It may also be used in non-woven fabric made of glass or aramid resin, such as woven fabric impregnated with the resin. なお、有機樹脂とフィラーとは、体積比率で15:85〜50:50の比率で複合化されるのが適当である。 Note that the organic resin and a filler, 15 in volume ratio: 85 to 50: it is suitable for being complexed with 50 ratio of.

【0023】これらの電気素子を収納するための空隙部を形成する絶縁シートは、上記の種々の材質の中でも空隙部をパンチング又はレーザーで容易に加工できる点から、エポキシ樹脂、イミド樹脂、フェニレンエーテル樹脂と、シリカまたはアラミド不織布との混合物であることが最も望ましい。 The insulating sheet forming the void portion for accommodating these electrical devices, the air gap among various materials of the terms that can be readily processed by punching or laser, epoxy resin, imide resin, polyphenylene ether a resin, and most preferably a mixture of silica or aramide nonwoven fabric.

【0024】一方、ビアホール導体2に充填される金属ペーストは、銅粉末、銀粉末、銀被覆銅粉末、銅銀合金などの、平均粒径が0.5〜50μmの金属粉末を含む。 On the other hand, the metal paste filled in the via-hole conductor 2 includes copper powder, silver powder, silver-coated copper powder, such as copper-silver alloy, an average particle size of the metal powder 0.5 to 50 [mu] m. 金属粉末の平均粒径が0.5μmよりも小さいと、 If the average particle size of the metal powder is less than 0.5 [mu] m,
金属粉末同士の接触抵抗が増加してスルーホール導体の抵抗が高くなる傾向にあり、50μmを越えるとスルーホール導体の低抵抗化が難しくなる傾向にある。 Tends to resistance increases the through-hole conductors contact resistance of the metal powder particles is increased, there is a tendency to lower resistance is difficult hole conductors exceeds 50 [mu] m.

【0025】また、導体ペーストは、前述したような金属粉末に対して、前述したような結合用有機樹脂や溶剤を添加混合して調製される。 Further, the conductive paste, the metal powder as described above, is prepared by adding and mixing a binding organic resins and solvents as described above. ペースト中に添加される溶剤としては、用いる結合用有機樹脂が溶解可能な溶剤であればよく、例えば、イソプロピルアルコール、テルピネオール、2−オクタノール、ブチルカルビトールアセテート等が用いられる。 The solvent added in the paste may be a solvent capable of bonding an organic resin is dissolved using, for example, isopropyl alcohol, terpineol, 2-octanol, butyl carbitol acetate or the like is used.

【0026】上記の導体ペースト中の結合用有機樹脂としては、前述した種々の絶縁シートを構成する有機樹脂の他、セルロースなども使用される。 [0026] As binding organic resin in the above conductive paste, other organic resin constituting the various insulating sheet described above are also used, such as cellulose. この有機樹脂は、 The organic resin,
前記金属粉末同士を互いに接触させた状態で結合するとともに、金属粉末を絶縁シートに接着させる作用をなしている。 With bound being in contact with said metal powder particles to one another, and has a function of adhering the metal powder to the insulating sheet. この有機樹脂は、金属ペースト中において、 The organic resin is in a metal paste,
0.1乃至40体積%、特に0.3乃至30体積%の割合で含有されることが望ましい。 0.1 to 40 vol%, it is desirable that the content at a rate of preferably 0.3 to 30 vol%. これは、樹脂量が0. This is, the amount of resin is 0.
1体積%よりも少ないと、金属粉末同士を強固に結合することが難しく、低抵抗金属を絶縁層に強固に接着させることが困難となり、逆に40体積%を越えると、金属粉末間に樹脂が介在することになり粉末同士を十分に接触させることが難しくなり、スルーホール導体の抵抗が大きくなるためである。 When the amount is less than 1 vol%, it is difficult to strongly bond the metal powder particles, it is difficult to firmly bond the low-resistance metal in the insulating layer, exceeds 40 volume percent Conversely, the resin between the metal powder There it becomes difficult to sufficiently contact the powder particles will be interposed, because the resistance of the through-hole conductors increases.

【0027】配線回路層としては、銅、アルミニウム、 [0027] As the wiring circuit layer, copper, aluminum,
金、銀の群から選ばれる少なくとも1種、または2種以上の合金からなることが望ましく、特に、銅、または銅を含む合金が最も望ましい。 Gold, at least one selected from the group consisting of silver, or desirably composed of two or more alloys, in particular, an alloy containing copper or copper, is most preferable. また、場合によっては、導体組成物として回路の抵抗調整のためにNi−Cr合金などの高抵抗の金属を混合、または合金化してもよい。 In some cases, the high resistance metal, such as Ni-Cr alloy mixture, or may be alloyed for resistance adjustment circuit as a conductor composition.
さらには、配線層の低抵抗化のために、前記低抵抗金属よりも低融点の金属、例えば、半田、錫などの低融点金属を導体組成物中の金属成分中に2〜20重量%の割合で含んでもよい。 Furthermore, in order to reduce the resistance of the wiring layers, than said low resistance metal having a low melting point metal, for example, solder, a low-melting-point metal such as tin in a metal component in the conductor composition of 2-20 wt% including at the rate may be.

【0028】配線回路層4と絶縁シート1との密着強度を高める上では、絶縁シート1の配線回路層4の形成箇所および/または転写フィルム表面の配線回路層4表面の表面を0.1μm以上、特に0.3μm〜3μm、最適には0.3〜1.5μmに粗面加工することが望ましい。 [0028] The wiring circuit layer 4 in increasing the adhesion strength between the insulating sheet 1, the area where the wiring circuit layers 4 of the insulation sheet 1 and / or transfer wiring circuit layer on the film surface 4 of the surface of the surface than 0.1μm , in particular 0.3 to 3 [mu] m, and optimally it is desirable to roughening to 0.3 to 1.5 .mu.m. また、ビアホール導体の両端を金属箔からなる配線回路層によって封止する上では、配線回路層4の厚みは、5〜40μmが適当である。 Further, on the both ends of the via-hole conductor is sealed by a wiring circuit layer made of a metal foil, the thickness of the wiring circuit layers 4, 5 to 40 m is appropriate.

【0029】このようにして、本発明によれば、簡単な積層方法を用いて、複数の絶縁層が積層されてなる絶縁基板内部に電気素子を実装収納することができ、これにより多層配線基板の電気素子を高密度に実装することができ、多層配線基板の小型化を図ることができる。 [0029] Thus, according to the present invention, by using a simple lamination method, it is possible to a plurality of insulating layers implement housing the electrical element on an insulating substrate inside are laminated, thereby the multilayer wiring board can implement the electrical elements at a high density, it is possible to reduce the size of the multilayer wiring board.

【0030】 [0030]

【実施例】(1) アラミド樹脂の不織布に対してイミド樹脂を50体積%の割合で含浸した厚さ100μmのプリプレグに、炭酸ガスレーザーで直径0.1mmのビアホールを形成し、そのホール内に銀をメッキした銅粉末を含む銅ペーストを充填してビアホール導体を形成した。 EXAMPLES] (1) a prepreg having a thickness of 100μm impregnated with imide resin in a proportion of 50% by volume based on aramid resin of the nonwoven fabric, to form a via hole having a diameter of 0.1mm at a carbon dioxide gas laser, in its hole to form a via hole conductor by filling a copper paste containing copper powder plated with silver. また、このプリプレグにレーザーを用いて半導体素子や電子部品を設置するための12mm×12mmの大きさの空隙部を形成した。 Further, to form a void portion of the size of 12 mm × 12 mm for mounting the semiconductor devices and electronic components using a laser to the prepreg.

【0031】(2)一方、イミド樹脂50体積%、シリカ粉末50体積%の割合となるように、ワニス状態の樹脂と粉末を混合しドクターブレード法により、厚さ75 [0031] (2) On the other hand, imide resin 50% by volume, as a percentage of the silica powder 50% by volume, by a doctor blade method by mixing the resin and powder varnish state, 75 thickness
mmの絶縁シートを作製し、その絶縁シートにパンチングで直径0.1mmのビアホールを形成し、そのホール内に銀をメッキした銅粉末を含む銅ペーストを充填してビアホール導体を形成した。 To prepare a mm of the insulating sheet, the insulating sheet punching by forming a via hole having a diameter of 0.1mm, the formed via-hole conductor by filling a copper paste containing copper powder plated with silver in its hole.

【0032】(3)また、一方、ポリエチレンテレフタレート(PET)樹脂からなる転写シートの表面に接着剤を塗布し、厚さ12μm、表面粗さ0.8μmの銅箔を一面に接着した。 [0032] (3) Further, whereas, an adhesive is applied to the surface of the transfer sheet made of polyethylene terephthalate (PET) resin was adhered thickness 12 [mu] m, a copper foil surface roughness 0.8μm on one side. そして、フォトレジスト(ドライフィルム)を塗布し露光現像を行った後、これを塩化第二鉄溶液中に浸漬して非パターン部をエッチング除去して配線回路層を形成した。 Then, after the coating is exposed and developed photoresist (dry film) was formed the wiring circuit layers which the pattern portion is immersed in a ferric chloride solution is removed by etching. なお、作製した配線回路層は、 The wiring circuit layer prepared is
線幅が20μm、配線と配線との間隔が20μmの微細なパターンである。 Line width 20 [mu] m, distance between the wiring and the wiring is a fine pattern of 20 [mu] m. その後、この配線回路層にIC素子をフリップチップ接続し、ポリイミド樹脂で封止した。 Thereafter, the IC device is flip-chip connected to the wiring circuit layer, sealed with a polyimide resin.

【0033】(4)そして、(1)で作製したプリプレグに対して、(2)で電気素子を実装した転写シートを、プリプレグの空隙部に電気素子が収納されるように位置決めして50kg/cm 2の圧力を加えて圧着した後、転写フィルムを剥離して、配線回路層とIC素子をプリプレグに転写した。 [0033] (4) Then, with respect to the prepreg prepared in (1), and positioned to the transfer sheet mounted with electric elements and an electric element in the gap portion of the prepreg is housed in (2) 50 kg / after crimping by applying a pressure of cm 2, and peeling off the transfer film, the wiring circuit layer and the IC element and transferred to the prepreg.

【0034】(5)(2)で作製した絶縁シートの表面に、(3)と同様にして金属箔からなる配線回路層を形成したPET樹脂フィルムから、配線回路層を転写させた。 [0034] (5) on the surface of an insulating sheet prepared in (2), from the PET resin film was formed the wiring circuit layer made of a metal foil in the same manner as in (3), is transferred to the wiring circuit layer. (6)空隙部にIC素子が収納されたプリプレグを中心に、その上下面に(5)のようにして配線回路層が転写された絶縁シートを上下各2層づつ積層し50kg/c (6) around a prepreg IC element is accommodated in the gap portion, the upper and lower surfaces and a manner wiring circuit layer is stacked one by upper and lower two layers an insulation sheet which has been transferred as (5) 50 kg / c
2の圧力で圧着し、200℃で1時間加熱して完全硬化させて多層配線基板を作製した。 Crimp a pressure of m 2, and to produce a multilayer wiring board by fully cured by heating for 1 hour at 200 ° C..

【0035】得られた多層配線基板に対して、断面における配線回路層やビアホール導体の形成付近を観察した結果、IC素子と配線回路層、ビアホール導体と配線回路層とは良好な接続状態であり、各配線間の導通テストを行った結果、配線の断線も認められなかった。 [0035] the obtained multilayer wiring board, result of observation of the vicinity of the formation of the wiring circuit layers and via hole conductors in the cross-section, IC element and the wiring circuit layer, and the via-hole conductor and the wiring circuit layer has a good connection state , as a result of the continuity test between the wires, it was not observed disconnection of the wiring. また、 Also,
IC素子の動作においても何ら問題はなかった。 There was no any problem in the operation of the IC element. 得られた多層配線基板を湿度85%、温度85℃の高温多湿雰囲気に100時間放置したが、目視で判別できる程度の変化は生じていなかった。 The resulting multi-layer wiring board humidity of 85%, was allowed to stand for 100 hours in hot and humid atmosphere at 85 ° C., to the extent that can be distinguished visually change did not occur.

【0036】 [0036]

【発明の効果】以上詳述したとおり、本発明によれば、 As described above in detail, according to the present invention,
電気素子を絶縁基板の内部に形成した空隙部に実装収納することにより、転写フィルム上の銅箔から形成した配線回路層に対して半導体素子や各種電子部品等の電気素子を実装した後、空隙部を形成した絶縁層の表面に転写して、電気素子を空隙部に収納することにより、電気素子を絶縁基板内に内蔵させることができ、これにより多層配線基板に積層一体化することにより高密度、高精細、且つ多機能の配線基板を容易に形成できる。 By implementing housing the electrical element in the gap portion formed in the insulating substrate, after mounting the electric elements such as semiconductor devices and various electronic components on the wiring circuit layer formed of copper foil on the transfer film, voids parts is transferred to form the surface of the insulating layer, by accommodating the electric element in the gap portion, an electric element can be incorporated in the insulating substrate, thereby high by integrally laminating a multilayer wiring board density, high resolution, and a wiring board multifunctional can be easily formed.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の素子内蔵多層配線基板の製造方法の一実施例を説明するための工程図である。 1 is a process diagram for explaining an embodiment of a manufacturing method of the head protection multilayer wiring board of the present invention.

【図2】本発明の素子内蔵多層配線基板において、電気素子を内蔵した空隙部を複数形成した多層配線基板を説明するための概略断面図である。 In the head protection multilayer wiring board of the present invention; FIG is a schematic cross-sectional view for explaining a multilayer wiring board in which a plurality forming a space portion with a built-in electrical devices.

【符号の説明】 DESCRIPTION OF SYMBOLS

1,7,8 絶縁シート 2,11,12 ビアホール導体 3,35,36,37 空隙部 4,9,10 配線回路層 5,33,34,37、38 電気素子 6 転写フィルム 13,31,32 絶縁基板 1,7,8 insulating sheet 2,11,12 hole conductor 3,35,36,37 gap portions 4, 9, 10 wiring circuit layer 5,33,34,37,38 electric elements 6 transfer film 13,31,32 insulating substrate

Claims (1)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】転写シートの表面に形成された配線回路層に電気素子を実装する実装工程と、少なくとも熱硬化性樹脂からなる第1の絶縁層にキャビティを形成するキャビティ形成工程と、前記第1の絶縁層の前記キャビティ内に前記電気素子が収納されるように、前記転写シートから前記配線回路層と前記電気素子を前記第1の絶縁層に転写する転写工程と、転写工程後の前記第1の絶縁層の上下面に、少なくとも熱硬化性樹脂を含み、少なくとも配線回路層が形成された第2および第3の絶縁層を積層圧着する積層工程と、該積層物を一括して熱硬化させる工程と、を具備することを特徴とする素子内蔵多層配線基板の製造方法。 And 1. A mounting step of mounting an electrical element on the wiring circuit layer formed on the surface of the transfer sheet, and the cavity forming step of forming a cavity in the first insulating layer comprising at least a thermosetting resin, said first wherein such electrical devices are housed in the cavity of the first insulating layer, and a transfer step of transferring from the transfer sheet to the electrical element and the wiring circuit layer on said first insulating layer, wherein after the transferring step the upper and lower surfaces of the first insulating layer includes at least thermosetting resin, and collectively the laminating step of laminating crimping the second and third insulating layers, at least the wiring circuit layer is formed, the laminated product heat manufacturing method of the head protection multilayer wiring substrate characterized by comprising the step of curing, the.
JP9201653A 1997-07-28 1997-07-28 Manufacturing method of the head protection multilayer wiring board Expired - Fee Related JP3051700B2 (en)

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