JP4837072B2 - Mounting structure - Google Patents

Description

  The present invention relates to a mounting structure that can mount an electronic component such as an LSI chip on the surface and includes an electric element built-in substrate in which an electric element such as a capacitor is built in an insulating substrate.

  In recent years, with the widespread use of communication devices, electronic devices that are required to operate at high speed have come to be widely used, and further, packages that can operate at high speed have been demanded. In order to perform such a high-speed operation, it is necessary to incorporate a passive electric element such as a capacitor inside the insulating substrate to reduce the inductance of the passive electric element and the wiring portion.

  As a method for coping with such a problem, for example, in Japanese Patent Application Laid-Open No. 11-220262, in a circuit component built-in module and a method for manufacturing the same, an insulating layer constituting an insulating substrate includes all inorganic fillers and thermosetting resins. A wiring board formed of a mixture has been proposed.

Japanese Patent Laid-Open No. 11-220262

  However, in the circuit board disclosed in Japanese Patent Laid-Open No. 11-220262, since the absolute strength of the board is weak and the rigidity is low, for example, when a semiconductor element is mounted on the surface of the wiring board by a flip chip method, the wiring board is deformed. However, there is a problem that the flip chip portion is warped.

  Further, as a method for increasing the strength, it has been proposed that the insulating substrate is constituted by a so-called prepreg in which a glass cloth is impregnated with resin. However, the fibrous body is made of a very limited substance such as glass, and therefore, there is a case where a difference in thermal expansion from an electric element such as a capacitor element incorporated in the prepreg becomes large. The connectivity with the wiring circuit layer in the wiring board changes, or the wiring board is deformed by the stress generated by the difference in thermal expansion between the two, which causes the flatness of the wiring board surface to be lost, and the semiconductor element is flip-chiped. There was a problem that it could not be implemented.

  Therefore, the present invention provides an excellent mounting property and mounting reliability even in the case where a semiconductor element or the like is flip-chip mounted on the surface of a wiring board in which an electric element such as a capacitor is built in an insulating substrate. In addition, an object of the present invention is to obtain a mounting structure including a wiring board with a built-in electric element having excellent connection reliability between the built-in electric element and a wiring circuit layer provided on the wiring board.

A mounting structure according to an embodiment of the present invention includes a stacked body including a plurality of insulating layers formed of an organic material, a positive electrode via-hole conductor and a negative electrode via-hole formed along the thickness direction of the insulating layer. conductor and said stored inside the formed cavity of the insulating layer, and an electrical element having positive and negative electrodes on the top surface, the positive electrode land provided on the upper surface of the laminate
And a negative electrode land, and the surface of the electric element built-in substrate so as to be electrically connected to the electric element built-in substrate via the positive electrode land and the negative electrode land. In the mounting structure including the electronic component mounted on the electronic component, the electrical element is located in a region immediately below the electronic component, and the positive electrode of the electrical element is connected to the via-hole conductor for the positive electrode. The positive electrode via-hole conductor is electrically connected to the positive electrode land, and the negative electrode of the electric element is connected to the negative electrode via-hole conductor. The negative electrode via-hole conductor is electrically connected to the negative electrode land, and is electrically connected to the negative electrode land .

  According to the present invention, in a mounting structure including a wiring board incorporating an electric element such as a capacitor element, the semiconductor element is flip-chip mounted on the surface layer portion of the wiring board, and at the same time, the capacitor element is built in the inner insulating layer. A mounting structure including a low-inductance wiring board can be manufactured.

It is a schematic sectional drawing of the wiring board with a built-in electric element of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS It is for demonstrating the capacitor | condenser element used by this invention, Comprising: (a) is a schematic perspective view, (b) is a pattern figure of the internal electrode for positive electrodes, (c) is an internal electrode pattern figure for negative electrodes. . FIG. 4A is a pattern diagram of a first conductor layer and FIG. 4B is a pattern diagram of a second conductor layer in the wiring board of the present invention. It is process drawing in order to manufacture the wiring board with a built-in electric element of the present invention.

  An electrical element built-in wiring board according to an embodiment of the present invention will be described in detail with reference to FIG. In the wiring board A according to the present invention, a cavity 2 is formed inside an insulating substrate 1, and a capacitor element 3 is built in the cavity 2. Further, a semiconductor element 4 is mounted as an electronic component immediately above the capacitor element 3 of the wiring board A.

  In the present invention, the insulating substrate 1 in the wiring board A is configured by a first insulating layer (hereinafter simply referred to as a CPC layer) 1a made of a mixture of a thermosetting resin and an inorganic filler in a portion in which the capacitor element 3 is embedded. In the fibrous body of at least one layer, heat is applied to the surface side of the insulating substrate 1 where the semiconductor element 4 is mounted and / or the back side where the connection terminals such as solder ball pads and connection pins are provided. A second insulating layer (hereinafter simply referred to as a prepreg layer) 1b formed by impregnating a curable resin is laminated.

(CPC layer)
The CPC layer 1a containing the capacitor element 3 is composed of a composite of a thermosetting resin and an inorganic filler. Examples of the inorganic filler include SiO ₂ , Al ₂ O ₃ , AlN, and Si ₃ N _4. At least one selected from the group can be preferably used. The inorganic filler is desirably contained in a proportion of 35 to 70% by volume with respect to the thermosetting resin, and the average particle size of the inorganic filler to be used is optimally in the range of 1.0 to 20 μm. This CPC layer has a thickness of about 50 to 150 μm per layer, and is appropriately laminated according to the size of an electric element such as a built-in capacitor element to have a predetermined thickness.

Further, this CPC layer takes advantage of the ability to arbitrarily control the thermal expansion coefficient, and the difference in thermal expansion of −65 to 250 ° C. with respect to the built-in electric element is 7 × 10 ⁻⁶ / ° C. or less, particularly 5.5 or less. It is necessary to. This is because even if an electrical element is built in the CPC layer, if this thermal expansion difference is large, the stress generated by this thermal expansion difference becomes large, which makes flip chip mounting difficult due to deformation of the wiring board, etc. This is because the connectivity with the wiring circuit layer in the wiring board is impaired, and the characteristics of the electric element cannot be obtained.

(Prepreg layer)
On the other hand, the prepreg layer 1b is obtained by impregnating a fibrous body and a thermosetting resin into the fibrous body, the thickness per layer is about 150 μm or less, the fibrous body is 40 to 60% by volume, and the thermosetting is performed. The conductive resin is composed of 60 to 40% by volume.

  As the fibrous body, at least one selected from the group of glass and aramid resin is used. The fiber body has a wire diameter of preferably 10 μm or less in order to increase the strength.

  The fibrous body may be uniformly dispersed, but is preferably made of woven fabric or non-woven fabric in order to increase the rigidity of the substrate.

The thermosetting resin contained in the CPC layer and prepreg layer is preferably at least one selected from the group consisting of an APPE (allylated polyphenylene ether) resin, an epoxy resin, and a cyanate resin. The APPE resin is particularly preferable because it has a low relative dielectric constant, a low dielectric loss, a low water absorption rate, and a high glass transition point, and thus has a particularly high heat resistance. Further, the mixture may contain a dispersant or a coupling agent in order to improve the wettability with the filler.

  The capacitor element 3 incorporated in the CPC layer preferably includes two or more positive electrodes and two or more negative electrodes. An example of such a capacitor element 3 is shown in the schematic perspective view of FIG.

The capacitor element 3 of FIG. 2 is composed of a multilayer ceramic capacitor composed of a rectangular laminate formed by laminating ceramic dielectric layers 5 mainly composed of BaTiO ₃ , Four positive electrodes 6a and four negative electrodes 6b are independently and equally arranged on the outer surface. In the capacitor element of FIG. 2A, the negative electrode 6b is formed at the center of each side, and the positive electrode 6a is formed at each corner.

  Further, between the ceramic dielectric layers 5 of the laminated body, a positive electrode internal electrode 7a having a pattern as shown in FIG. 2B and a negative electrode internal electrode 7b having a pattern as shown in FIG. Are alternately formed, the positive internal electrode 7a is electrically connected to the positive electrode 6a, and the negative internal electrode 7b is electrically connected to the negative electrode 6b at the end face of the laminate.

  On the other hand, a first conductor layer 8 and a second conductor layer 9 are formed in the prepreg layer 1b between the capacitor element 3 having the above structure built in the CPC layer 1a and the surface of the electronic component mounting surface. ing. Then, as shown in the pattern diagram of FIG. 3A, the first conductor layer 8 vertically penetrates the four positive electrodes 6a of the capacitor element 3 and the insulating layer directly above the positive electrode 6a. They are electrically connected via the formed via-hole conductor 10.

  Similarly, as shown in the pattern diagram shown in FIG. 3B, the second conductor layer 9 has four negative electrodes 6b of the capacitor element 3 and an insulating layer vertically above the negative electrode 6b. It is electrically connected through a via-hole conductor 11 formed so as to penetrate therethrough. The first conductor layer 8 has an opening 12 in which a conductor is formed so as not to come into contact with the via-hole conductor 11 that connects the negative electrode 6b and the second conductor layer 9.

  The first conductor layer 8 connected to the positive electrode 6a of the capacitor element 3 is further provided with a via-hole conductor 13 over the electronic component mounting surface, and a positive electrode land 14 provided on the substrate surface. Similarly, in the second conductor layer 9 connected to the negative electrode 6b of the capacitor element 3, a via-hole conductor 15 is further formed over the electronic component mounting surface, and is provided on the substrate surface. The negative electrode land 16 is connected.

  The bumps of the semiconductor element 4 mounted on the surface of the insulating substrate 1 are electrically connected to the positive electrode land 14 and the negative electrode land 16.

In the wiring board with a built-in electric element of the present invention, the difference in thermal expansion coefficient between the first insulating layer and the second insulating layer constituting the substrate is 8.6 × 10 ⁻⁶ / ° C. or less. 3 × 10 ⁻⁶ / ° C. or less is desirable.

(Production method)
Next, the manufacturing method of the electric element built-in wiring board of the present invention will be described. First, for forming the CPc layer, an uncured insulating sheet made of a mixed material of a thermosetting resin such as epoxy resin or polyphenylene ether resin and an inorganic filler such as silica or alumina is prepared. For the prepreg layer, an uncured insulating sheet is produced by impregnating a fiber body made of woven or non-woven fabric such as glass fiber or aramid fiber with a thermosetting resin such as epoxy resin.

  First, as shown in the process diagram of FIG. 4, a cavity 21 containing a capacitor element is formed in the CPC layer insulating sheet 20 by punching or the like (a). On the other hand, via holes 23 are formed in the prepreg layer insulating sheet 22 by a laser processing method, and the via holes 23 are filled with a conductive paste containing conductive powder such as Cu powder to form via hole conductors 24 (b). ). Thereafter, the conductor layer 25 is formed on the surface of the prepreg layer insulating sheet 22 (c). For example, the conductor layer 25 is formed by attaching a metal foil such as a Cu foil or an Al foil to the surface of the insulating sheet, and then forming a conductor layer having a predetermined pattern by the steps of resist application, exposure, development, etching, and resist removal. There is a method, or a method in which the metal foil is attached to the surface of a resin film in advance and a conductor layer having a predetermined pattern is formed in the same manner as described above and transferred to the surface of the insulating sheet. Among these, the latter method is more preferable in that the insulating sheet is not exposed to an etching solution and the insulating sheet is not deteriorated.

  And while installing the capacitor | condenser element 26 in the cavity 21 of the insulating sheet 20 for CPC layers, and applying the manufacturing method of said (b) (c) above and below this insulating sheet 20, the said via-hole conductor 27 and conductor layer 28, prepreg layer insulating sheets 30a, 30b, 30c, 30d and 30e on which pads 29 for connection with semiconductor elements are formed are laminated, and this laminate is thermosetting in the CPC insulating sheet and prepreg layer insulating sheet. By heating at a temperature sufficient to cure the resin, a wiring board having a built-in capacitor element as shown in FIG. 1 can be produced.

  In order to electrically connect the positive electrode and the negative electrode of the capacitor element 26 disposed in the CPC layer insulating sheet 20 to the via hole conductor 27 of the prepreg layer insulating sheet 30, the capacitor of the via hole conductor 27 is used. By applying solder that can be melted at the thermosetting temperature to the connection portion with the element 26 and / or the surface of the positive electrode and the negative electrode of the capacitor element 26, the connection between the capacitor element and the via-hole conductor can be reliably performed. it can.

Example (1) The pattern of the positive electrode internal electrode and the negative electrode internal electrode as shown in FIG. 2 was screen-printed on the surface of a plurality of BaTiO ₃ -based ceramic dielectric sheets using an Ag—Pd metal paste. . Thereafter, these sheets were laminated and adhered under a temperature of 55 ° C. and a pressure of 150 kg / cm ² , cut with a cutter in a green state, and then fired at a temperature of 1220 ° C. in an air atmosphere to produce a capacitor body.

  Then, an Ag—Pd paste is applied to the positive electrode forming portion and the negative electrode forming portion on the outer surface of the capacitor body and baked at a temperature of 850 ° C., and shown in FIG. 2 having a plurality of positive electrodes and negative electrodes. An 8-terminal multilayer ceramic capacitor was prepared.

This capacitor element has a thermal expansion coefficient of 10.2 × 10 ⁻⁶ / ° C. at −65 to 250 ° C., a size of 1.6 × 1.6 × 0.59 (mm ³ ), and a capacitance of 0. .22 μF, self-inductance is 80 (pH), and four positive electrodes and four negative electrodes are formed.

  (2) A plurality of insulating sheets A having a thickness of 150 μm are prepared by a doctor blade method by mixing a resin and a powder in a varnish state so that the proportion of silica powder is 50% by volume with respect to a PPE (polyphenylene ether) resin. In these insulating sheets A, a cavity of 1.6 mm length × 1.6 mm width slightly larger than the size of the capacitor to be accommodated was formed by trepan processing using a carbon dioxide gas laser.

  Similarly, a via hole is formed by a carbon dioxide laser, and the via hole is filled with a conductive paste containing conductive powder such as Cu powder to form a via hole conductor. As a via hole conductor for connecting a conductor layer and a bump of a semiconductor element, and a via hole conductor for connecting a capacitor element and a conductor layer, a conductor paste containing copper powder having an average particle diameter of 5 μm plated with silver on the surface Filled to form a via-hole conductor. In addition, as a via-hole conductor, 252 via-hole conductors were formed according to the number of bumps of the semiconductor element.

  (3) An insulating sheet B made of a prepreg of 52 to 68% by volume of A-PPE (thermosetting polyphenylene ether) resin (curing temperature = 220) and 32 to 48% by volume of glass cloth was prepared. Similarly, a via hole 23 is formed in a part of the prepreg by trepan processing using a carbon dioxide laser, and the via hole 23 is filled with a conductive paste containing conductive powder such as Cu powder to form a via hole conductor 24.

  (4) On the other hand, an adhesive was applied to the surface of a transfer sheet made of polyethylene terephthalate (PET) resin, and a copper foil having a thickness of 12 μm and a surface roughness of 0.8 μm was adhered to one surface. And after apply | coating a photoresist (dry film) and performing exposure development, this was immersed in the ferric chloride solution, the non-pattern part was etched away, and the conductor layer for positive electrodes and the conductor layer for negative electrodes were formed. . In addition, a wiring circuit layer having a fine pattern with a line width of 20 μm and a distance between the wirings of 20 μm was also formed.

(5) Then, after the conductor layer side of the transfer sheet is pressure-bonded to the insulating sheet B with a pressure of 30 kg / cm ² on the surface of the insulating sheet B produced in (3), the transfer sheet is peeled off to insulate the conductor layer. Transferred to sheet B.

  (6) Next, the insulating sheet A formed with the cavity produced in (2) is laminated by the thickness of the capacitor element, and the laminated ceramic capacitor chip produced in (1) is temporarily installed in the cavity. The surrounding gap was temporarily fixed by filling 40% by volume of epoxy resin and 60% by volume of silica.

  (7) And the insulating sheet B which has the conductor layer and via-hole conductor which were produced through (3) and (4) was temporarily laminated | stacked on the surface and back surface of the insulating sheet A which accommodated this capacitor | condenser element.

  (8) Then, the laminate was heated at 220 ° C. for 1 hour to be completely cured to produce a multilayer wiring board. In addition, the gap of the insulating sheet contracted by the flow of the resin due to heating, the insulating layer and the capacitor chip were in close contact, and the gap between the chip and the insulating layer was almost eliminated. Thus, a capacitor built-in wiring board having a total thickness of 1.2 mm was produced.

  And the following examination was performed with respect to the produced wiring board with a built-in capacitor.

  And the linear thermal expansion coefficient of -65-250 degreeC of the whole produced board | substrate was measured. In addition, the Si chip on which the Au stud bump was formed was flip-chip mounted on a substrate heated at about 60 ° C., and the conduction resistance around the circuit board pad and the circuit on the Si chip side was measured to confirm the presence or absence of conduction. Further, the mechanical strength of the entire wiring board was measured using an Instron evaluation apparatus.

Further, using an impedance analyzer, the frequency characteristic of the impedance is measured at a frequency of 1.0 MHz to 1.8 MHz, the capacitance value of the capacitor at 1 MHz is measured at the same time, and f ₀ = 1 / (2π (L (C) ^1/2 ) (where, f ₀ : resonance frequency (Hz), C: capacitance (F), L: inductance (H)), the inductance was calculated from the resonance frequency.

  In addition, this measurement also measured the impedance after 300 cycles of room temperature and thermal shock tests. Further, the change in characteristics was measured by changing the thickness of the insulating layer on the upper surface of the capacitor element as shown in Table 1. In the thermal shock test, carbon dioxide was used as a refrigerant, an electric heater was used as a heating source, and a temperature cycle of −55 to 125 ° C. was applied 100 times every 5 minutes in a chamber at a pressure of 1 atm.

(Comparative Example 1)
A wiring board was produced using only the insulating sheet made of the mixture of the thermosetting resin (3) and the inorganic filler in the example, and the same evaluation as above was performed.

(Comparative Example 2)
In the examples, the arrangement of the insulating sheet A and the insulating sheet B was completely reversed, and a wiring board was produced in the same manner except that the capacitor element was built in the insulating sheet B, and the same evaluation as described above was performed. .

  As is apparent from the results of Table 1, based on the present invention, an insulating layer made of prepreg on the surface layer portion of the wiring board, and an inner layer portion containing the capacitor element are made of an insulating layer made of a mixture of an inorganic filler and a thermosetting resin. The wiring board of the present invention formed by (CPC) has a high mechanical strength of 300 MPa or more and can be flip-chip mounted. In addition, the change in inductance due to the capacitor element was also highly reliable with no change after initial characteristics at room temperature and after the thermal shock test.

A wiring board 1 insulating board 1a first insulating layer 1b second insulating layer 2 cavity 3 capacitor element 4 semiconductor element 5 ceramic dielectric layer 6a positive electrode 6b negative electrode 7a positive electrode internal electrode 7b negative electrode internal electrode 8 first Conductor layer
9 Second conductor layer 10, 11, 17 Via hole conductor

Claims (3)

A laminate composed of a plurality of insulating layers formed of an organic material, a positive electrode via-hole conductor and a negative electrode via-hole conductor formed along the thickness direction of the insulating layer, and formed inside the insulating layer is housed in the cavity, an electrical device having a positive electrode and a negative electrode on the upper surface, the positive electrode land and a negative electrode land provided on the upper surface of the laminate, and electrical element embedded substrate equipped with,
An electronic component mounted on the surface of the electric element built-in substrate so as to be electrically connected to the electric element built-in substrate through the positive electrode land and the negative electrode land ,
The electrical element is located in a region directly below the electronic component;
The positive electrode of the electric element is electrically connected to the positive electrode via-hole conductor on the electric element, and the positive electrode via-hole conductor is electrically connected to the positive electrode land. And
The negative electrode of the electrical element is electrically connected to the negative electrode via-hole conductor on the electrical element, and the negative electrode via-hole conductor is electrically connected to the negative electrode land. mounting structure, characterized in that there. The electric element has a plurality of the positive electrode and the negative electrode on the upper surface,
The mounting structure according to claim 1, wherein the positive electrode and the negative electrode are alternately arranged along an outer periphery of the electric element . The mounting structure according to claim 1 , wherein the positive electrode via-hole conductor is linearly formed in a region between the positive electrode and the positive electrode land .

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