JP3893088B2 - Manufacturing method of substrate for semiconductor package - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor package substrate on which a semiconductor chip is mounted.
[0002]
[Prior art]
When mounting a semiconductor chip on a printed wiring board (motherboard), in most cases, the stress generated by the difference in thermal expansion between the semiconductor chip and the printed wiring board is relieved, or a semiconductor chip consisting of a narrow pitch electrode is printed. For the purpose of widening the electrode pitch so that it can be mounted on a board, mounting is performed via a semiconductor package substrate (hereinafter referred to as “package substrate”).
[0003]
In such a package substrate, a plurality of individual package substrates are arranged on one sheet, the individual package substrates and the front and back wiring patterns are connected by gold plating leads and via holes, and then a desired solder resist Then, by electrolytic gold plating using the gold plating leads, electrolytic Ni— is applied to the bonding pads on the semiconductor chip mounting side exposed from the solder resist of each individual package substrate and the external connection pads on the motherboard mounting side. Manufactured by applying Au plating or the like. And after mounting a semiconductor chip on each individual package board | substrate in the sheet | seat obtained by such a manufacturing method, resin-sealing the said semiconductor chip, it divides | segments into an individual semiconductor package.
[0004]
A package substrate obtained by the manufacturing method of the above embodiment and an example of the manufacturing method (here, a double-sided board is taken as an example) will be described with reference to FIGS.
FIG. 2 shows a plan view of an individual package substrate. FIG. 2A shows a semiconductor chip mounting surface, a via hole 9 for connecting the front and back wiring layers, and a bonding connected to the electrodes of the semiconductor chip by wire bonding. For the gold plating, which has a pad 13 and a wiring pattern 8 for connecting the via hole 9 and the bonding pad 13, all the bonding pads 13 are used when electrolytic gold plating is applied to the bonding pad 13 or the like later. The lead 14 and the power supply pad 14a are connected. Further, (b) is a mounting surface on the mother board, and a large number of external connection pads 10 as the bottom land of the via hole 9 are arranged.
[0005]
Subsequently, a manufacturing method of the package substrate having the above-described configuration will be described with reference to schematic cross-sectional explanatory views of the via hole 9 forming portion.
First, as shown in FIG. 3A, an insulating substrate 3 having conductors 2 on both sides of the insulating layer 1 is prepared. Next, the surface side conductor 2a in the via hole forming portion is removed to form the window portion 4 (see FIG. 3B), and the exposed insulating layer 1 is irradiated with laser to reach the back side conductor 2b. 5 is drilled (see FIG. 3C). Next, after the inside of the non-through hole 5 is cleaned by a desmear process, an electroless metal plating film 6 and an electrolytic metal plating film 7 are deposited on the front and back surfaces (see FIG. 3D). Next, by a general photo process, the via hole 9 connecting the front and back wiring layers, the wiring pattern 8 connecting the via hole 9 and the bonding pad 13 (see FIG. 2A), and the bottom land of the via hole 9 are connected. A package substrate 11a on which the external connection pads 10 are formed is obtained (see FIG. 3E).
[0006]
However, since the package substrate obtained by the above manufacturing method forms a pattern by etching after depositing the electroless metal plating film 6 and the electrolytic metal plating film 7 for forming the via holes on the entire front and back conductor surfaces, Although a via hole excellent in performance can be obtained, it is difficult to form a fine pattern (fine wiring), and there is a problem that it is impossible to meet the demand for a compact and high-density wiring of the package substrate. Moreover, since the electroless metal plating film 7 lacking in flatness is formed on the bonding pad that requires flatness and the external connection pad, the wire bonding property of the semiconductor chip and the mountability of the semiconductor package on the motherboard are reduced. There was concern.
[0007]
As a method for avoiding such a problem, Japanese Patent Laid-Open No. 2002-26515 discloses the following method. First, an insulating substrate having conductors on the front and back sides of the insulating layer is prepared, and wiring patterns are formed on the front and back sides. Next, after a non-through hole is drilled at a desired position on the surface-side wiring pattern, an electroless metal plating film is deposited on the entire surface (including the inside of the non-through hole), and then the non-through hole is formed. An electrolytic metal plating film is deposited only on the hole and its periphery. Finally, excess electroless metal plating film is removed by flash etching.
[0008]
With such a manufacturing method, the front and back wiring pattern formation is performed in the state of the conductor layer previously laminated on the insulating substrate, and the electroless metal plating film and the electrolytic metal plating film are only on the via hole forming portion. Therefore, the formation of the fine pattern and the formation of the via hole having excellent connection reliability can be achieved at the same time. In addition, when the package substrate as shown in FIG. 2 is manufactured by the above manufacturing method, the electrolytic metal plating film is not formed on the bonding pad and the external connection pad, so that the wire bonding property of the semiconductor chip and the motherboard of the semiconductor package can be achieved. The concern about the decrease in mountability can be avoided.
[0009]
[Problems to be solved by the invention]
However, the above manufacturing method has the following problems. That is, since the electroless metal plating film at the time of forming the via hole is formed on the entire surface-side wiring pattern layer that has been patterned in advance, only the flash etching is performed between the wiring patterns, particularly the fine pattern (wiring pattern width / In the surface of the insulating layer existing between the wiring pattern gap = 20 μm / 20 μm or less), the catalyst at the time of forming the electroless metal plating film is likely to remain, and there is a possibility that the insulating characteristics may be deteriorated. In order to remove them, a separate process is required, which complicates the manufacturing process, resulting in problems such as an increase in manufacturing cost and a decrease in yield.
[0010]
It is an object of the present invention to provide a method of manufacturing a package substrate that can easily obtain a package substrate having excellent insulation characteristics without requiring separate processing in order to avoid a decrease in insulation characteristics between wiring patterns. Objective.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor package substrate manufacturing method according to the present invention provides a semiconductor package substrate in which bonding pads and external connection pads of a semiconductor chip are connected by via holes for interlayer connection and leads for gold plating. A method of forming a non-through hole reaching a lower layer conductor from a desired position of a conductor layer laminated at least on the outermost layer, and conducting the non-through hole by an electroless metal plating film forming process. and performing, after the electroless metal plating film forming process, forming a connected wiring pattern and a gold plating leads on the outermost layer, after the wiring pattern formation, a portion of the non-through holes and excluding the periphery of precipitation and forming a plating resist, after the plating resist formation, utilizing a gold-plated leads, the electroless metal plating therearound with the blind holes That process and a method for manufacturing a semiconductor package substrate, characterized in that it contains a step of removing the plating resist.
[0012]
By manufacturing the package substrate by the above manufacturing method, the electroless metal plating film in forming the via hole is not formed on the insulating layer between the wiring patterns. There is no fear of remaining, and a package substrate having excellent insulating characteristics can be easily obtained. In addition, since the wiring pattern can be formed before the convex portion of the via hole by the electrolytic metal plating film is formed, the pattern can be formed by a general dry film, and an increase in manufacturing cost can be suppressed.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to a schematic cross-sectional explanatory view of a via hole forming portion shown in FIG. Note that the package substrate to be manufactured is the same as that shown in FIG.
[0014]
First, as shown in FIG. 1A, an insulating substrate 3 having conductors 2 (thickness 3 to 18 μm) on both sides of an insulating layer 1 (thickness 20 to 400 μm) is prepared. As the insulating layer 1, a fiber substrate compatible with laser processing in which thin fibers such as glass fiber and aramid fiber are uniformly woven is impregnated with epoxy resin, BT (bismaleimide triazine) resin, polyimide resin, etc .; Or the thing without the said fiber base material; Or resin etc. which contained the inorganic filler are mentioned. Moreover, as the conductor 2, general copper foil etc. are mentioned. Next, the surface side conductor 2a of the via hole forming portion is removed by etching to form a window portion 4 (see FIG. 1B), and the insulating layer 1 exposed from the window portion 4 is irradiated with a laser (for example, a carbon dioxide laser). By doing so, the non-through hole 5 reaching the back-side conductor 2b is formed (see FIG. 1C). Next, after the inside of the non-through hole 5 is cleaned by a desmear process, an electroless metal plating film 6 (for example, an electroless copper plating film) is formed on the front and back surfaces to conduct the non-through hole (FIG. 1D). Next, the front and back wiring patterns are formed by a general photoetching process, and a wiring pattern including the gold plating leads 14 and the bonding pads 13 (see FIG. 2A) is formed (see FIG. 2). 1 (e)). Next, a plating resist 12 is formed on the portion excluding the non-through hole 5 and its periphery (see FIG. 1 (f)), and then electrolytic metal plating (for example, using the gold plating lead 14 and the power supply pad 14a) (Electrolytic copper plating) treatment is performed to deposit an electrolytic metal plating film 7 (for example, an electrolytic copper plating film) around the non-through hole and the periphery thereof (see FIG. 1G). Next, by removing the plating resist 12 formed on the front and back surfaces, a via hole 9 for connecting the front and back wiring layers, and a wiring pattern 8 for connecting the via hole 9 and the bonding pad 13 (see FIG. 2A). Then, a package substrate 11 on which the external connection pads 10 as the bottom lands of the via holes 9 are formed is obtained (see FIG. 1H).
[0015]
In the description of the present invention, a package substrate having wiring patterns on both sides has been described. However, the number of layers is not limited to this, and bonding pads and external connection pads are connected by gold plating leads and via holes. If it is the structure which was made, it can also be set as the multilayered structure of three or more layers.
[0016]
In addition, the package substrate has been described using the package substrate in which the electrodes of the semiconductor chip and the bonding pads of the package substrate are connected by wire bonding, but the flip chip mounting type package in which both are connected via bumps or the like It goes without saying that the same effect can be obtained even with a substrate.
[0017]
【The invention's effect】
If a semiconductor package substrate in which a bonding pad of a semiconductor chip and an external connection pad are connected by a gold plating lead for interlayer connection and a via hole is manufactured by the method of the present invention, the insulating characteristics between fine patterns are excellent. A package substrate can be easily manufactured.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional explanatory diagram for explaining a manufacturing process of a package substrate of the present invention.
FIG. 2 is a schematic plan view for explaining the form of a package substrate.
FIG. 3 is a schematic cross-sectional explanatory diagram for explaining a conventional manufacturing process of a package substrate.
[Explanation of symbols]
1: Insulating layer 2: Conductor 2a: Front side conductor 2b: Back side conductor 3: Insulating substrate 4: Window portion 5: Non-through hole 6: Electroless metal plating film 7: Electrolytic metal plating film 8: Wiring pattern 9: Via hole 10: External connection pads 11, 11a: Package substrate 12: Plating resist 13: Bonding pad 14: Gold plating lead 14a: Power supply pad

Claims (1)

A method of manufacturing a substrate for a semiconductor package, wherein a bonding pad and an external connection pad of a semiconductor chip are connected by a via hole for interlayer connection and a gold plating lead, and at least a desired conductor layer laminated on the outermost layer A step of drilling a non-through hole reaching a lower conductor from a position, a step of conducting the non-through hole conduction process by an electroless metal plating film formation process, and after the electroless metal plating film formation process , A step of forming a wiring pattern connected to the gold plating lead, a step of forming a plating resist in a portion excluding the non-through hole and its periphery after the formation of the wiring pattern, and a step for forming a gold plating after the formation of the plating resist Using a lead, and including a step of depositing electrolytic metal plating around the non-through hole and its periphery, and a step of stripping the plating resist The method of manufacturing a semiconductor package substrate, wherein.

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