JP4682477B2 - Electronic component mounting substrate and manufacturing method thereof - Google Patents

Electronic component mounting substrate and manufacturing method thereof Download PDF

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Publication number
JP4682477B2
JP4682477B2 JP2001234163A JP2001234163A JP4682477B2 JP 4682477 B2 JP4682477 B2 JP 4682477B2 JP 2001234163 A JP2001234163 A JP 2001234163A JP 2001234163 A JP2001234163 A JP 2001234163A JP 4682477 B2 JP4682477 B2 JP 4682477B2
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electrode
electronic component
electrodes
terminal
substrate
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JP2003046029A (en
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斌 岩下
晴彦 牧野
英俊 草野
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Description

【０００１】
【発明の属する技術分野】
この発明は超高周波領域で動作させる半導体チップを実装した高周波対応の実装基板に適用して好適な電子部品実装基板及びその製造方法に関する。
詳しくは、絶縁性の担持部材に担持された所定の回路配線電極及び端子電極を備え、しかも、所定の厚みでサイドエッジが垂直に切り立った電極を構成して、当該回路配線電極及び端子電極のインピーダンス特性（表皮効果）を改善できるようにすると共に、薄型の実装に優れ、かつ、高周波特性に優れた電子部品実装基板等を提供できるようにしたものである。
【０００２】
【従来の技術】
近年、情報通信分野ではマルチメディアの発達に伴い通信機能に加えて多種多様な機能を備えた携帯電話機や携帯ゲーム機等が使用される場合が多くなってきた。これらの携帯端末装置等には通信機能や情報検索機能などを実現する多数の電子部品や配線パターンを実装したモールド樹脂封止基板が使用される場合が多い。モールド樹脂封止基板に実装される半導体チップにはクロック信号で動作するデジタル回路が多く適用され、その動作の高速化が進んでいる。
【０００３】
この種のデジタル回路搭載のモールド樹脂封止基板には軽量化及び小型化に加えて高周波対応性が要求されるが、従来から両面銅箔を有した有機基板が使用されている。有機基板はガラスエポキシプリプレイグと呼ばれるガラス繊維布に半硬化状態のエポキシ樹脂を塗布したものである。
【０００４】
図９は従来例に係るＣＳＰ（チップ・サイズ・パッケージ）タイプのモールド樹脂封止基板１０の構成例を示す断面図である。図９に示すモールド樹脂封止基板１０はワイヤーボンディング可能な半導体チップ１を実装したものであり、チップ実装用の有機基板８を有している。この有機基板８の表面には所定の回路電極パターン３が設けられており、この回路電極パターン３上には半導体チップ１が実装されている。半導体チップ１は一方で端子電極５Ａに金線４Ａにより接続され、他方で端子電極５Ｂに金線４Ｂにより接続されている。
【０００５】
有機基板８の裏面には複数の端子電極５Ｃ，５Ｄ等が設けられており、上述の端子電極５Ａと端子電極５Ｃとがスルーホール７Ａにより電気的に接続されており、同様にして端子電極５Ｂと端子電極５Ｄとがスルーホール７Ｂにより電気的に接続されている。
【０００６】
この回路電極パターン３、半導体チップ１の全部及び端子電極５Ａ，５Ｂの一部を覆うように封止部材２により絶縁封止されている。これらの回路電極パターン３、端子電極５Ａ，５Ｂ及び端子電極５Ｃ，５Ｄは両面銅箔付きの有機基板８を使用して形成されたものである。
【０００７】
この製造方法によれば、図１０Ａにおいて、まず、両面銅箔付きの有機基板８の上下銅箔で導通を取るために、レーザ光あるいはドリルを使用してビアホール（Ｖia Ｈole）が開孔され、その後、ビアホール内に銅メッキ（スルーホールメッキ）が施される。
【０００８】
そして、有機基板８の一方の面の銅箔５にレジストのパターニング処理をした後に、図１０Ｂにおいて、レジスト膜６をマスクにして不要な銅箔５をエッチング除去することにより端子電極５Ａ〜５Ｂや、マウント部を含む回路電極パターン３を形成（素子分離）する。
【０００９】
その後、有機基板８の他方の面の銅箔５にレジストのパターニング処理をした後に、レジスト膜をマスクにして不要な銅箔５をエッチング除去することにより端子電極５Ｃや５Ｄを形成する。その後、半導体チップ１がマウントされてワイヤボンディングされる。完成後のモールド樹脂封止基板１０は、外部のプリント配線基板に対して半導体チップ１の搭載面と反対側の端子電極５Ｃ，５Ｄ等で接続するようになされる。
【００１０】
【発明が解決しようとする課題】
ところで、従来方式のモールド樹脂封止基板１０の製造方法によれば、両面銅箔付きの有機基板８の一方の面に回路電極パターン３や、マウント部、複数の端子電極５Ａ，５Ｂなどを形成し、その裏面に端子電極５Ｃ，５Ｄ等を形成していた。このため、次のような問題がある。
【００１１】
▲１▼ 有機基板８の表裏の端子電極５Ａと端子電極５Ｃとを電気的に接続するスルーホール７Ａや、端子電極５Ｂと端子電極５Ｄとを接続するためのスルーホール７Ｂが必要となる。
【００１２】
▲２▼ 図１０Ｂの波線円内図に示すように、レジスト膜６下がオーバーエッチングによって銅箔５の側面（エッチング面）が垂直に切り立つことなく、その側面が内部にえぐれた鼓状にラインエッジが仕上がってしまうおそれがある。これは配線パターンが微細化するほど著しい。因みに４０μｍのパターン幅に対して約５μｍのオーバーエッチが生じることが確認されている。
【００１３】
▲３▼ 銅箔をエッチングして配線パターン等を作成する方法では、サイドエッチの量をコントロールすることが困難なことから、加工精度の高いＣＳＰタイプのモールド樹脂封止基板等の製造に妨げとなる。因みにファインパターンの作成要求に対して銅箔エッチングでは限界があり、ライン＆スペース（Ｌ／Ｓ）で３０μｍは困難な状況である。
【００１４】
▲４▼ 銅箔をエッチングして得た配線パターンは、その残りしろが安定せず、表皮効果の点でインピーダンス特性にばらつきを生ずるおそれがある。これを改善するために整合回路などを別途設けなくてはならなくなる。
【００１５】
そこで、この発明はこのような従来の課題を解決したものであって、回路配線電極及び端子電極のインピーダンス特性（表皮効果）を改善できるようにすると共に、高周波対応の電子部品を高密度に実装できるようにした電子部品実装基板及びその製造方法を提供することを目的とする。
【００１６】
【課題を解決するための手段】
上述した課題は、メッキ及びエッチング可能な導電性の基材の両面に非メッキ部材を形成する工程と、所定の回路電極をパターニングした第１のマスク部材を前記導電性の基材の一方の面に位置合わせする工程と、所定数の端子電極をパターニングした第２のマスク部材を前記導電性の基材の他方の面に位置合わせする工程と、前記導電性の基材の一方の面の非メッキ部材に前記第１のマスク部材を通して、ダイパッド部と配線電極を含む回路配線電極のパターンを露光し、同時に、前記導電性の基材の他方の面の非メッキ部材に前記第２のマスク部材を通して端子電極のパターンを露光する工程と、前記回路配線電極と前記端子電極の各パターンを開口する非メッキ部材をマスクにして電解メッキ法により前記導電性の基材に導電部材をメッキし、該メッキ電流を調整して前記回路電極及び端子電極の厚みを制御して、前記導電性の基材の両面に所定の回路配線電極及び端子電極を形成する工程と、前記基材の回路配線電極形成面側の全面に絶縁樹脂シートからなる担持部材を接合する工程と、前記担持部材及び回路配線電極を有する回路電極基板から前記導電性の基材を、当該基材の前記担持部材が接合された面と反対側の面から、当該面の一部の領域を当該基材の厚さ方向全域でエッチングにより除去して前記ダイパッド部に接合される電子部品の実装空間を形成するとともに、当該エッチング時に、前記配線電極を外部リード端子としての前記端子電極に連結する前記導電性の基材の一部を前記実装空間の周囲に残す工程とを含む電子部品実装基板の製造方法によって解決される。
【００１７】
本発明に係る電子部品実装基板の製造方法によれば、銅箔をエッチングして形成された配線パターンに比べて所定の厚みでサイドエッジが垂直に切り立った回路配線電極及び端子電極を形成することができ、当該回路配線電極及び端子電極のインピーダンス特性（表皮効果）を改善することができる。これと共に、高周波対応の電子部品を高密度に実装することができる。従って、薄型の実装に優れ、かつ、高周波特性に優れた電子部品実装基板を提供することができる。
【００１９】
また、銅箔をエッチングして配線パターンを形成する場合に比べて所定の厚みでパターンエッジの整った回路配線電極や端子電極などを再現性良く形成することができる。特に回路配線電極のサイドエッジを垂直に切り立つように形成できることからインピーダンス特性（表皮効果）を改善することができる。
【００２０】
しかも、安定した回路配線電極及び端子電極の形状が得られるので、容易に回路設計を行うことができる。回路配線電極及び端子電極のインピーダンス特性が優れているので、高精度のインダクタンスや静電容量を作成することもできる。従来方式のようなスルーホールメッキ無しに端子電極を作成することができる。これにより、高周波特性に優れた電子部品実装基板を製造することができる。
【００２１】
【発明の実施の形態】
続いて、この発明に係る電子部品実装基板及びその製造方法の一実施の形態について、図面を参照しながら説明をする。
【００２２】
（１）第１の実施形態
図１は本発明に係る第１の実施形態としての電子部品実装基板１００の構成例を示す断面図である。
この実施形態では絶縁性の担持部材に担持された所定の回路配線電極及び端子電極を備え、しかも、所定の厚みでサイドエッジが垂直に切り立った電極を構成して、当該回路配線電極及び端子電極のインピーダンス特性（表皮効果）を改善できるようにすると共に、薄型の実装に優れ、かつ、高周波特性に優れた電子部品実装基板等を提供できるようにしたものである。
【００２３】
図１に示す電子部品実装基板１００はＵＦＰＬ（ウルトラ・ファインピッチ・リードフレーム）プロセス技術により作られた半導体（ＬＳＩ）チップ等を実装する高周波対応の半導体チップ実装基板に適用して好適であり、少なくとも、支持補強材を兼ねた絶縁性の担持部材２２を有している。
【００２４】
担持部材２２には少なくとも有機絶縁材料が使用される。この例で担持部材２２は熱硬化型ＰＰＥ（ポリフェニレンエーテル）をシート化して接着硬化したものである。この他に、耐熱性が必要な時はポリイミド系の担持部材２２が使用される。動作周波数の低い電子部品実装基板１００ではエポキシ系の担持部材２２が使用される。高周波用の担持部材２２と使い分けするようになされる。
【００２５】
この担持部材２２には回路配線電極１３が担持されている。回路配線電極１３は銅箔のエッチングによる配線パターンではなく、電気メッキによって形成された配線電極１３Ａ，１３Ｃ及びダイパッド部１３Ｂを有している。ダイパッド部１３Ｂには電子部品の一例となるワイヤーボンディング可能な半導体チップが接着剤１８を介在して接合されている。電子部品はこれに限られることはなく、面接合可能なフリップチップ方式の半導体チップであってもよい。
【００２６】
この半導体チップ１１又は／及び配線電極１３Ａ，１３Ｃには複数の端子電極１５Ａ，１５Ｂ等が接続されている。端子電極１５Ａ，１５Ｂは外部のプリント配線基板等に接続する際に使用される。この半導体チップ１１は一方の側で金線１４Ａを介在して端子電極（外部リード）１５Ａに接続されており、他方の側で金線１４Ｂを介在して端子電極１５Ｂに接続されている。電子部品実装基板１００によっては数十〜数百本の端子電極１５Ａ，１５Ｂが設けられる。
【００２７】
この例で配線電極１３Ａ，１３Ｃは半導体チップの接続方式によって、例えば、ワイヤボンディング方式の場合は金、ニッケル及び銅から構成され、フリップチップ方式の場合は金及び銅から構成される。
【００２８】
この端子電極１５Ａ，１５Ｂの一部、ダイパッド部１３Ｂ及び配線電極１３Ａ，１３Ｃの全部が電解メッキ法により形成されて成るものである。例えば、配線電極１３Ａ，１３Ｃ及び端子電極１５Ａ，１５Ｂはメッキ及びエッチング可能な導電性の基材の両面に選択的に形成された非メッキ部材をマスクにして該基材の両面に同時に導電部材をメッキした後、該基材を選択的にエッチング除去して形成されたものである。
【００２９】
この高周波対応の電子部品実装基板１００で半導体チップの実装領域は、封止部材が充填されず空間のまま使用される。空気は誘電率εｒ＝１であることによる。もちろん、用途に応じて実装領域に絶縁性の封止部材を充填するようにしてもよい。その際にはモールド樹脂が使用される。
【００３０】
続いて、半導体チップ実装基板１００の製造方法について説明をする。図２〜図７は半導体チップ実装基板１００の形成例（その１〜６）を示す工程図である。
この例ではメッキ及びエッチング可能な導電性の基材の両面に非メッキ部材を選択的に形成し、その後、非メッキ部材をマスクにして基材の両面に同時に導電部材をメッキし所定の配線電極１３Ａ，１３Ｃ及び端子電極１５Ａ，１５Ｂを形成する。そして、基材の配線電極形成面側に絶縁性の担持部材２２を接合する場合を前提とする。電子部品はワイヤーボンド方式の半導体チップの場合を想定する。メッキは電解メッキでも無電解メッキでもよいが、無電解メッキは膜厚制御が難しいので、この例では電解メッキの場合を例に挙げる。
【００３１】
これを製造条件にして、まず、メッキ及びエッチング可能な導電性の基材の一例となる、図２Ａの断面図に示すような板厚ｔの銅合金板２０を準備する。銅合金板２０は通常のリードフレームと同様の素材のものを用いるとよい。銅合金板２０の板厚ｔは１００〜２００μｍ程度であり、この例ではｔ＝１００μｍの銅合金板２０を使用する。この銅合金板２０は電子部品実装基板１００を製造する過程で仮の基板として使用されると共に、その銅合金板２０の一部が端子電極１５Ａ，１５Ｂの心材を構成するようになされる。
【００３２】
このような銅合金板２０が準備できたら、配線電極１３Ａ，１３Ｃ、チップ用のダイパッド部１３Ｂを含む回路配線電極１３及び、所定数の端子電極１５Ａ，１５Ｂを形成するために、銅合金板２０の両面に非メッキ部材を選択的に形成する。例えば、図２Ｂにおいて、銅合金板２０の両面及び端面に非メッキ部材の一例となる膜厚１０μｍ〜４０μｍ程度のレジスト１６’を塗布する。写真法によりレジスト１６’をパターニングするためである。
【００３３】
ファインパターンの場合は、膜厚の薄いレジスト１６’を使用する。均一な厚みが得やすいことから、レジスト１６’にはドライフイルム化したものを使用するとよい。液状のレジストを使用しても同じ効果が得られる。配線電極１３Ａ，１３Ｃや端子電極１５Ａ，１５Ｂの幅形状はレジストパターンで決まる。この例ではドライフイルム化したレジスト１６’を使用する。メッキ後のばらつきの少ない設計通りの配線電極１３Ａ，１３Ｃや端子電極１５Ａ，１５Ｂを得ることができる。
【００３４】
その後、図２Ｃにおいて第１のマスク部材の一例となるレチクル（ガラス乾板）２６を銅合金板２０の一方の面に位置合わせする。レチクル２６には所定の配線電極１３Ａ，１３Ｃやダイパッド部１３Ｂ等の回路配線電極パターンを焼き付けたものである。銅合金板２０の他方の面には第２のマスク部材の一例となるレチクル２７を位置合わせする。レチクル２７には所定数の端子電極パターンを焼き付けたものである。
【００３５】
そして、銅合金板２０の一方の面のレジスト１６’にレチクル２６を通して回路配線電極パターンを露光し、同時に、この銅合金板２０の他方の面のレジスト１６’にレチクル２７を通して端子電極パターンを露光する。これは銅合金板２０の両面に同時に同じ金属がメッキされるようにするためである。このとき、両面露光機を使用してレジスト１６’を露光する。
【００３６】
銅合金板２０の端面のレジスト１６’も露光する。この端面にはメッキを施さないようにするためである。その後、レジスト１６’を現像した後に不要なレジスト膜を除去する。この露光処理によって、銅合金板２０の一方の面にレジストパターン１６が形成され、他方の面にレジストパターン１７が形成される。端面にもメッキ保護用のレジストパターン１７’が形成される。
【００３７】
このレジストパターン１６を銅合金板２０の上面から見ると例えば、図３Ａに示すようになる。図３Ａの平面図において、銅合金板２０の一方の面に、配線電極パターンＰ１，Ｐ３、ダイパッドパターンＰ２を反転したレジストパターン１６を形成することができる。
【００３８】
なお、この例では端子電極１５Ａ，１５Ｂとなる銅合金板２０の側壁にもレジスト膜１７’が形成される。これは端子電極１５Ａ，１５Ｂとなる銅合金板２０の側壁にはメッキを成長しないようにする。こうすることで、銅合金板エッチング時にエッチャントを端子電極１５Ａ、１５Ｂの端面へ浸食するようになされる。
【００３９】
図３Ｂは図３Ａに示した銅合金板２０のＸ１−Ｘ２矢視断面図である。図３Ｂにおいて、レジストパターン１７は端子電極パターンＰ４，Ｐ５を反転したものである。端子電極パターンＰ４、Ｐ５によって数十〜数百本の端子電極１５Ａ，１５Ｂを銅合金板２０から電気的に素子分離するようになされる。
【００４０】
図４Ａは図３Ａに示した銅合金板２０のＹ１−Ｙ２矢視断面図である。図４Ａにおいて、レジストパターン１６，１７は配線電極パターンＰ３及び端子電極パターンＰ５を反転したものである。このようなレジストパターン１６，１７が形成できたら、図４Ｂに示す電気メッキ装置３００に銅合金板２０をセットし、レジストパターン１６、１７等の各々をマスクにして銅合金板２０の両面に同時に導電部材をメッキし所定の配線電極１３Ａ，１３Ｃ、ダイパッド部１３Ｂ及び端子電極１５Ａ，１５Ｂを形成する。
【００４１】
電気メッキ装置３００には周知の電解メッキ方法が適用される。電気メッキ装置３００はメッキ容器２０１の中に電解液２０２、１組の陽極２０３Ａ，２０３Ｂ、その外部に直流電源２０４及び電流計２０５を有している。陽極２０３Ａ，２０３Ｂには所望の導電部材を用いてもよい。
【００４２】
メッキ母材となる銅合金板２０は直流電源２０４の−端子に接続され、陽極２０３Ａ，２０３Ｂは電流計２０５を通じて直流電源２０４の＋端子に接続して使用される。電解液２０２は導電部材によって取り替えるようになされる。例えば銅のメッキ時には電解液２０２として硫酸銅の水溶液が使用される。導電部材はエッチングマスク兼半田付け良好な金属材料が好ましい。この例で導電部材（メッキ部材）には金、ニッケル及び銅が使用される。
【００４３】
この例で半導体チップ１１がワイヤボンディング方式の場合はレジストパターン１６、１７をマスクにしてニッケル、金、ニッケル、銅の順に銅合金板２０にメッキがなされる。フリップチップ方式の場合は金、銅の順にメッキがなされる。このメッキの多層化によって表皮効果の良い配線電極１３Ａ，１３Ｃや端子電極１５Ａ，１５Ｂを形成することができる。
【００４４】
各々のメッキ部材におけるメッキ電流Ｉは電流計２０５を見ながら調整し、各々のメッキ部材の厚みを調整することにより、回路配線電極１３の全体の厚みを制御するようになされる。各々のメッキ部材の厚みはメッキ電流Ｉを多くし、通電時間を長くするとメッキ量を多くすることができる。
【００４５】
この例では、第１層目のＮｉメッキを５μｍ程度、Ａｕメッキを０．５μｍ程度、第２層目のＮｉメッキを５μｍ程度、Ｃｕメッキを３０μｍ程度となるようにメッキ電流を調整するようになされる。これにより、有機基板の銅箔により配線パターンを形成する場合に比べて厚みのある回路配線電極１３等を形成することができる。
【００４６】
このようにメッキ電流Ｉを制御し、その後、レジスト膜１６，１７等を除去すると、図５Ａに示すような銅合金板２０の一方の面に配線電極１３Ａ，１３Ｃ及びダイパッド部１３Ｂを含む回路配線電極１３を形成することができる。銅合金板２０の他方の面には図５Ｂに示すように端子電極１５Ａ，１５Ｂのみを形成することができる。この例では銅合金板２０の側壁にはメッキが成長されない。
【００４７】
この時点では回路配線電極１３、端子電極１５Ａ，１５Ｂは電気的な素子分離はなされていない。銅合金板２０で短絡された状態となっている。なお、図６Ａは図５Ａに示した回路電極基板２０’のＺ１−Ｚ２矢視断面図である。以後の形成例では電子部品実装基板１００の断面の形成工程について説明する。
【００４８】
つまり、図６Ａに示す銅合金板２０の一方の面にはその波線円内図に示すように、Ｎｉ／Ａｕ／Ｎｉ／Ｃｕを積層した回路配線電極１３を形成することができる。銅合金板２０の他方の面にもＮｉ／Ａｕ／Ｎｉ／Ｃｕを積層した端子電極１５Ａ，１５Ｂを形成することができる。
【００４９】
この例ではドライフイルム化したレジスト１６’を使用したので、メッキ後、ばらつきの少ない設計通りのパターン幅の配線電極１３Ａ，１３Ｃや端子電極１５Ａ，１５Ｂを得ることができた。しかも、配線電極１３Ａ，１３Ｃ下の銅合金板２０を所定の形状に残すことで端子電極１５Ａ，１５Ｂを補強することができた。ここで回路配線電極１３、端子電極１５Ａ，１５Ｂに係るパターンをメッキされた銅合金板２０を以後、回路電極基板２０’ともいう。
【００５０】
そして、図６Ｂにおいて回路電極基板２０’の配線電極形成面側に絶縁性の担持部材２２を形成する。ここでは担持部材２２として膜厚１５μｍ乃至３０μｍ程度の長尺状の樹脂シート部材を接着する。樹脂シート部材は１パッケージ化する際に分離するようになされる。
【００５１】
この担持部材２２には樹脂部材だけのシートでもプリプレーグされたものでも、どちらを使用してもよい。耐熱性が必要な時はポリイミド系の樹脂部材を使用する。高周波用には熱硬化型ＰＰＥ（ポリフェニレンエーテル）系の樹脂部材を使用する。一般用はエポキシ系と使い分けをし、シート化されたものを接着し、その後、樹脂部材を硬化する。
【００５２】
このような担持部材２２によって配線電極１３Ａ，１３Ｃ及びダイパッド部１３Ｂを含む回路配線電極１３が裏打ちされるので、これらの回路配線電極１３下（半導体チップ搭載側）の銅合金板２０を除去しても担持姿勢を保つことができる。
【００５３】
その後、図７Ａにおいて、担持部材付きの回路電極基板２０’から、仮の基板として使用していた銅合金板２０の一部又は全部を回路配線電極１３及び端子電極１５Ａ，１５Ｂの各々をマスクにして選択的にエッチングし除去する。このとき、銅のエッチングにはニッケルが犯されない薬品としてｐＨ（ペーハー）を調整した弱アルカリ水溶液を使用する。
【００５４】
例えば、銅の専用エッチャントにはアンモニアのペーハーを８．０乃至８．５程度に調整した水溶液が使用される。この弱アルカリ水溶液を４５℃にしてエッチングする。このエッチングにより、不要部分の銅合金板２０が除去され、配線電極１３Ａ，１３Ｃ及びダイパッド部１３Ｂを含む回路配線電極１３と、複数の端子電極１５Ａ，１５Ｂとが電気的に同時に素子分離される。
【００５５】
ニッケル層を有する電極構造のものは、ニッケルは弱アルカリ水溶液ではエッチングされないので、ニッケル面が現れたらエッチングを終了する。なお、回路配線電極１３が金−ニッケル構造となるものは銅のエッチングだけになる。
【００５６】
この素子分離によって回路配線電極１３Ｃ下に空間部２８が生ずる。これと共に回路配線電極１３が露出する。この銅合金板２０のエッチング終了後、ニッケルをエッチングして金面が現れるようにするとよい。回路電極基板形成後も、配線電極１３Ａ，１３Ｃや端子電極１５Ａ，１５Ｂにおいて同じ金面（層）を有するようになる。金面は半田ボンディングがし易くなるからである。ニッケルのエッチング液には専用酸性エッチャントを温度３５℃にして使用する。この際に金面が現れたらエッチングを終了する。
【００５７】
その後、回路電極基板２０’のダイパッド部１３Ｂ下に半導体チップ１１を実装する。この時点で回路配線電極１３を露出した回路電極基板２０’を天地反転させ、開口部分を上に向けるように姿勢を整えてもよい。ここでは接着剤１８を使用して回路配線電極１３のダイパッド部１３Ｂに半導体チップ１１をダイボンディングして接合される。
【００５８】
半導体チップ１１の一方のパッド電極１９Ａと配線電極１３Ａとの間は金線１４Ａにより例えば、熱圧着ボンディングし、半導体チップ１１の他方のパッド電極１９Ｂと配線電極１３Ｃとを他の金線１４Ｂにより熱圧着ボンディングする。その後、樹脂シート部材を切断して、担持部材付きのパッケージに分離する。
【００５９】
このとき、樹脂シート部材をチップ・サイズ・パッケージ数個からなる集合体に切断することもできる。この例では個々に樹脂シート部材を切断することにより、図１に示したような高周波対応の電子部品実装基板１００が完成する。
【００６０】
もちろん、半導体チップ１１の実装後の空間部２８に絶縁性の封止部材を形成してもよい。その場合には、封止部材にはエポキシ系のモールド樹脂が使用される。この封止工程では金線１４Ａ，１４Ｂが隠れる厚みを確保するように回路電極基板２０’の内側にモールド樹脂が封止される。
【００６１】
このようにして、本発明に係る第１の実施形態としての電子部品実装基板１００によれば、銅箔をエッチングして形成された配線パターンに比べて所定の厚みでサイドエッジが垂直に切り立った配線電極１３Ａ，１３Ｃ及び端子電極１５Ａ，１５Ｂを構成することができ、当該配線電極１３Ａ，１３Ｃ及び端子電極１５Ａ，１５Ｂのインピーダンス特性（表皮効果）を改善にすることができる。しかも、メッキにより配線電極１３Ａ，１３Ｃや端子電極１５Ａ，１５Ｂ等を再現性良く形成できることから、ライン＆スペース（Ｌ／Ｓ）で１０μｍ以下のパターニングが正確に安価に提供できるようになる。これにより、高周波対応の半導体チップを高密度に実装することができる。
【００６２】
また、電子部品実装基板１００の製造方法によれば、安定した配線電極１３Ａ，１３Ｃ及び端子電極１５Ａ，１５Ｂの形状が得られるので、容易に回路設計を行うことができる。配線電極１３Ａ，１３Ｃ及び端子電極１５Ａ，１５Ｂのインピーダンス特性が優れているので、高精度のインダクタンスや静電容量を作成することもできる。従来方式のようなスルーホールメッキ工程無しに端子電極１５Ａ，１５Ｂを作成することができる。これにより、薄型の実装に優れ、かつ、高周波特性に優れた半導体チップ実装基板を製造することができる。
【００６３】
（２）第２の実施形態
図８は本発明に係る第２の実施形態としての電子部品実装基板２００の構成例を示す断面図である。この実施形態では電子部品に関してワイヤーボンディング可能な半導体チップ１１に代えて面接合可能なフリップチップ方式の半導体チップ３１を適用したものである。
【００６４】
図８に示す電子部品実装基板２００は高周波対応実装基板に適用して好適であり、第１の実施形態と同様にして支持補強材を兼ねた絶縁性の担持部材２２を有している。担持部材２２には少なくとも有機絶縁材料が使用される。この例で担持部材２２は熱硬化型ＰＰＥ（ポリフェニレンエーテル）をシート化して接着硬化したものである。この他に、耐熱性が必要な時はポリイミド系の担持部材２２が使用される。動作周波数の低い電子部品実装基板ではエポキシ系の担持部材２２が使用される。高周波用の担持部材２２と使い分けするようになされる。
【００６５】
この担持部材２２には所定数の端子電極１５Ａ，１５Ｂ及び所定の回路配線電極３３Ａ〜３３Ｇが担持されている。この回路配線電極３３Ａ〜３３Ｇ下には電子部品の一例となるフリップチップ方式の半導体チップ３１が実装されている。半導体チップ３１は複数のバンプ電極（エリアバンプ）３４Ａ〜３４Ｇ等を有している。
【００６６】
この半導体チップ３１のバンプ電極３４Ａは回路配線電極３３Ａに接続され、そのバンプ電極３４Ｂは回路配線電極３３Ｂに接続され、バンプ電極３４Ｃは回路配線電極３３Ｃに接続され、バンプ電極３４Ｄは回路配線電極３３Ｄに接続され、バンプ電極３４Ｅは回路配線電極３４Ｅに接続され、バンプ電極３４Ｆは回路配線電極３３Ｆに接続され、バンプ電極３４Ｇは回路配線電極３４Ｇに各々接続されている。各々の回路配線電極３３Ａ〜３３Ｇは端子電極１５Ａ，１５Ｂ等に接続されている。電子部品実装基板２００によっては数十〜数百本の端子電極１５Ａ，１５Ｂが設けられる。
【００６７】
回路配線電極３３Ａ〜３３Ｇは、端子電極１５Ａ，１５Ｂと共にメッキ及びエッチング可能な導電性の基材の一例となる銅合金板２０の一方の面に所望の導電部材がメッキにより形成され、その後、この銅合金板２０を選択的にエッチング除去して同時に形成されたものである。回路配線電極３３Ａ〜３３Ｇの全部、端子電極１５Ａ，１５Ｂの一部は電解メッキ法により形成されている。
【００６８】
この回路配線電極３３Ａ〜３３Ｇは膜厚０．５μｍ程度の金及び膜厚３０μｍ程度の銅が順にメッキされており、端子電極１５Ａ，１５Ｂは銅合金板２０のエッチング残留物を芯材となされ、この芯材の一方の面側には同様の膜厚の金及び銅の順にメッキされて成る。
【００６９】
このように形成すると、銅合金板２０を担持部材形成工程に至るまでの仮の基板として使用できる他に、その銅合金板２０のエッチング残留部分を使用した端子電極１５Ａ，１５Ｂを構成することができる。
【００７０】
しかも、回路配線電極３３Ａ〜３３Ｇのサイドエッジを垂直に切り立つように整形することができ、有機基板の銅箔をエッチングして配線パターン形成する場合に比べてラインエッジが整った高精度の回路配線電極３３Ａ〜３３Ｇ及び、表皮効果に優れた配線電極３３Ａ〜３３Ｇが得られ、超高周波動作に最適となる。端子電極１５Ａ，１５Ｂも、ある程度の高さを確保することができ、内部抵抗に低い電極を得ることができる。
【００７１】
この電子部品実装基板２００で半導体チップ３１の実装領域は空間のまま使用される。空気は誘電率εｒ＝１であることによる。もちろん用途に応じて絶縁性の封止部材を充填してもよい。その際には封止部材にはモールド樹脂が使用される。
【００７２】
このように、本発明に係る第２の実施形態としての電子部品実装基板２００によれば、銅箔をエッチングして配線パターンを形成する場合に比べて所定の厚みでパターンエッジの整った回路配線電極３３Ａ〜３３Ｇや端子電極１５Ａ、１５Ｂなどを同時に形成することができる。特に回路配線電極３３Ａ〜３３Ｇのサイドエッジを垂直に切り立つように形成できることから表皮効果を均一にすることができる。
【００７３】
しかも、電子部品実装基板２００によれば、有機絶縁材料から成る担持部材２２が使用されるので、超高周波回路に適用して好適な高周波特性に優れた、フリップチップ方式の半導体チップ実装の高周波対応実装基板を製造することができる。
【００７４】
【発明の効果】
以上説明したように本発明に係る電子部品実装基板によれば、絶縁性の担持部材に担持された所定の回路配線電極及び端子電極を備え、この回路配線電極及び端子電極はメッキ及びエッチング可能な導電性の基材の両面に選択的に形成された非メッキ部材をマスクにしてその基材の両面に同時に導電部材をメッキした後、その基材を選択的にエッチング除去して形成されたものである。
【００７５】
この構成によって、銅箔をエッチングして形成された配線パターンに比べて所定の厚みでサイドエッジが垂直に切り立った回路配線電極及び端子電極構造を具現化ができ、当該回路配線電極及び端子電極のインピーダンス特性（表皮効果）を均一にすることができる。これと共に、高周波対応の電子部品を高密度に実装することができる。従って、薄型の実装に優れ、かつ、高周波特性に優れた電子部品実装基板を提供することができる。
【００７６】
本発明に係る電子部品実装基板の製造方法によれば、導電性の基材の両面に非メッキ部材を選択的に形成し、その後、非メッキ部材をマスクにして基材の両面に同時に導電部材をメッキし所定の回路配線電極及び端子電極を形成し、更に、この基材の回路配線電極形成面側に絶縁性の担持部材を接合し、その後、担持部材及び回路配線電極を有する回路電極基板から導電性の基材をエッチングにより全部又は一部を除去するようになされる。
【００７７】
この構成によって、銅箔をエッチングして配線パターンを形成する場合に比べて所定の厚みでパターンエッジの整った回路配線電極や端子電極などを再現性良く形成することができる。特に回路配線電極のサイドエッジを垂直に切り立つように形成できることからインピーダンス特性（表皮効果）を均一にすることができる。
【００７８】
しかも、安定した回路配線電極及び端子電極の形状が得られるので、容易に回路設計を行うことができる。回路配線電極及び端子電極のインピーダンス特性が優れているので、高精度のインダクタンスや静電容量を作成することもできる。
【００７９】
この発明は超高周波領域で動作させる半導体チップを実装した高周波対応実装基板に適用して極めて好適である。
【図面の簡単な説明】
【図１】本発明に係る第１の実施形態としての電子部品実装基板１００の構成例を示す断面図である。
【図２】Ａ〜Ｃは半導体チップ実装基板１００の形成例（その１）を示す工程図である。
【図３】Ａ及びＢは半導体チップ実装基板１００の形成例（その２）を示す工程図である。
【図４】Ａ及びＢは半導体チップ実装基板１００の形成例（その３）を示す工程図である。
【図５】Ａ及びＢは半導体チップ実装基板１００の形成例（その４）を示す工程図である。
【図６】Ａ及びＢは半導体チップ実装基板１００の形成例（その５）を示す工程図である。
【図７】Ａ及びＢは半導体チップ実装基板１００の形成例（その６）を示す工程図である。
【図８】本発明に係る第２の実施形態としての電子部品実装基板２００の構成例を示す断面図である。
【図９】従来例に係るモールド樹脂封止基板１０の構成例を示す断面図である。
【図１０】Ａ及びＢはモールド樹脂封止基板１０のエッチング時の形成例を示す工程図である。
【符号の説明】
１１，３１・・・半導体チップ（電子部品）、１３・・・回路配線電極、１３Ａ，１３Ｃ，３３Ａ〜３３Ｇ・・・配線電極、１３Ｂ・・・ダイパッド部、１４Ａ，１４Ｂ・・・金線、１５Ａ，１５Ｂ・・・端子電極、１６，１７・・・レジスト膜（非メッキ部材）、２０・・・銅合金板（導電性の基材）、２２・・・担持部材、２６，２７・・・レチクル（第１，第２のマスク部材）、３４Ａ〜３４Ｇ・・・バンプ電極、１００，２００・・・電子部品実装基板、３００・・・電気メッキ装置[0001]
BACKGROUND OF THE INVENTION
The present invention is an electronic component mounting board suitable for application to a high-frequency mounting board on which a semiconductor chip that operates in an ultra-high frequency region is mounted. And its It relates to a manufacturing method.
Specifically, a predetermined circuit wiring electrode and a terminal electrode supported by an insulating supporting member are provided, and an electrode having a predetermined thickness and a side edge is vertically formed, and the circuit wiring electrode and the terminal electrode In addition to being able to improve impedance characteristics (skin effect), it is possible to provide an electronic component mounting board that is excellent in thin mounting and excellent in high frequency characteristics.
[0002]
[Prior art]
In recent years, with the development of multimedia in the information communication field, mobile phones and portable game machines having various functions in addition to communication functions have been increasingly used. In these portable terminal devices and the like, a mold resin encapsulated substrate on which a large number of electronic components and wiring patterns for realizing a communication function and an information search function are mounted is often used. Many digital circuits that operate with a clock signal are applied to a semiconductor chip mounted on a mold resin sealing substrate, and the operation speed is increasing.
[0003]
This type of digital circuit-mounted mold resin-encapsulated substrate is required to be compatible with high frequencies in addition to being reduced in weight and size, but conventionally an organic substrate having a double-sided copper foil has been used. The organic substrate is obtained by applying a semi-cured epoxy resin to a glass fiber cloth called glass epoxy prepreg.
[0004]
FIG. 9 is a cross-sectional view showing a configuration example of a CSP (chip size package) type mold resin sealing substrate 10 according to a conventional example. A mold resin sealing substrate 10 shown in FIG. 9 is mounted with a semiconductor chip 1 capable of wire bonding, and has an organic substrate 8 for chip mounting. A predetermined circuit electrode pattern 3 is provided on the surface of the organic substrate 8, and the semiconductor chip 1 is mounted on the circuit electrode pattern 3. The semiconductor chip 1 is connected to the terminal electrode 5A on the one hand by a gold wire 4A, and on the other hand to the terminal electrode 5B by a gold wire 4B.
[0005]
A plurality of terminal electrodes 5C, 5D and the like are provided on the back surface of the organic substrate 8, and the terminal electrode 5A and the terminal electrode 5C are electrically connected through the through-hole 7A. Similarly, the terminal electrode 5B is provided. And the terminal electrode 5D are electrically connected by a through hole 7B.
[0006]
The circuit electrode pattern 3, all of the semiconductor chip 1, and part of the terminal electrodes 5A and 5B are insulated and sealed by a sealing member 2. These circuit electrode pattern 3, terminal electrodes 5A and 5B, and terminal electrodes 5C and 5D are formed using an organic substrate 8 with double-sided copper foil.
[0007]
According to this manufacturing method, in FIG. 10A, first, a via hole is opened using a laser beam or a drill in order to establish conduction between the upper and lower copper foils of the organic substrate 8 with double-sided copper foil, Thereafter, copper plating (through-hole plating) is performed in the via hole.
[0008]
Then, after patterning the resist on the copper foil 5 on one surface of the organic substrate 8, in FIG. 10B, the unnecessary copper foil 5 is removed by etching using the resist film 6 as a mask, whereby the terminal electrodes 5A-5B and Then, the circuit electrode pattern 3 including the mount portion is formed (element isolation).
[0009]
Then, after patterning a resist on the copper foil 5 on the other surface of the organic substrate 8, unnecessary copper foil 5 is removed by etching using the resist film as a mask to form terminal electrodes 5C and 5D. Thereafter, the semiconductor chip 1 is mounted and wire-bonded. The completed mold resin sealing substrate 10 is connected to an external printed wiring board through terminal electrodes 5C, 5D, etc. on the side opposite to the mounting surface of the semiconductor chip 1.
[0010]
[Problems to be solved by the invention]
By the way, according to the manufacturing method of the mold resin sealing substrate 10 of the conventional system, the circuit electrode pattern 3, the mount part, the plurality of terminal electrodes 5A, 5B, etc. are formed on one surface of the organic substrate 8 with the double-sided copper foil. However, the terminal electrodes 5C, 5D and the like are formed on the back surface. For this reason, there are the following problems.
[0011]
(1) A through hole 7A for electrically connecting the terminal electrodes 5A and 5C on the front and back sides of the organic substrate 8 and a through hole 7B for connecting the terminal electrode 5B and the terminal electrode 5D are required.
[0012]
(2) As shown in the wavy circle diagram of FIG. 10B, the side surface (etched surface) of the copper foil 5 is not vertically cut off due to over-etching under the resist film 6, and the side surface is lined in a drum shape. The edge may be finished. This is more remarkable as the wiring pattern becomes finer. Incidentally, it has been confirmed that overetching of about 5 μm occurs for a pattern width of 40 μm.
[0013]
(3) In the method of etching a copper foil to create a wiring pattern or the like, it is difficult to control the amount of side etching, which hinders the production of CSP type mold resin encapsulated substrates with high processing accuracy. Become. Incidentally, there is a limit in copper foil etching for fine pattern creation requirements, and 30 μm is difficult in line and space (L / S).
[0014]
{Circle around (4)} The remaining wiring pattern obtained by etching the copper foil is not stable, and there is a possibility that the impedance characteristic varies in terms of the skin effect. In order to improve this, a matching circuit or the like must be provided separately.
[0015]
Therefore, the present invention solves such a conventional problem, and improves impedance characteristics (skin effect) of circuit wiring electrodes and terminal electrodes, and also mounts high frequency compatible electronic components at high density. Electronic component mounting board made possible And its An object is to provide a manufacturing method.
[0016]
[Means for Solving the Problems]
The above-described problems include a step of forming a non-plated member on both surfaces of a conductive substrate that can be plated and etched, and a first mask member patterned with a predetermined circuit electrode on one surface of the conductive substrate. , A step of aligning a second mask member patterned with a predetermined number of terminal electrodes with the other surface of the conductive substrate, and a non-surface of one surface of the conductive substrate. Through the first mask member through the plating member Including die pad and wiring electrode Circuit wiring electrode of A terminal electrode is exposed through the second mask member to the non-plated member on the other surface of the conductive substrate at the same time as the pattern is exposed. of A step of exposing a pattern, and the circuit wiring electrode And said Terminal electrode Each Pattern Open Using the non-plated member as a mask, the conductive substrate is formed by electrolytic plating. Conductive member Plating, adjusting the plating current to control the thickness of the circuit electrode and terminal electrode, On both sides of the conductive substrate A step of forming predetermined circuit wiring electrodes and terminal electrodes, and a circuit wiring electrode forming surface side of the substrate; The whole surface Isolated on Made of resin sheet A step of bonding a supporting member, and the conductive base material from a circuit electrode substrate having the supporting member and a circuit wiring electrode; From the surface of the substrate opposite to the surface to which the support member is bonded, a partial region of the surface is spread over the entire thickness direction of the substrate. Remove by etching In addition to forming a mounting space for electronic components to be bonded to the die pad portion, a part of the conductive base material that connects the wiring electrode to the terminal electrode as an external lead terminal is etched in the mounting space. Leave around And a manufacturing method of an electronic component mounting substrate including a process.
[0017]
Electronic component mounting substrate according to the present invention Manufacturing method According to the present invention, the circuit wiring electrode and the terminal electrode having a predetermined thickness and a side edge vertically vertical compared to a wiring pattern formed by etching a copper foil Formation The impedance characteristics (skin effect) of the circuit wiring electrode and the terminal electrode can be improved. At the same time, high-frequency electronic components can be mounted with high density. Therefore, it is possible to provide an electronic component mounting board that is excellent in thin mounting and excellent in high-frequency characteristics.
[0019]
Also, Compared with the case where a copper foil is etched to form a wiring pattern, circuit wiring electrodes and terminal electrodes having a predetermined pattern edge and a predetermined thickness can be formed with good reproducibility. In particular, the impedance characteristic (skin effect) can be improved because the side edges of the circuit wiring electrodes can be formed vertically.
[0020]
In addition, since stable circuit wiring electrodes and terminal electrode shapes can be obtained, circuit design can be easily performed. Since the impedance characteristics of the circuit wiring electrode and the terminal electrode are excellent, it is possible to create a highly accurate inductance and capacitance. Terminal electrodes can be formed without through-hole plating as in the conventional method. Thereby, the electronic component mounting board | substrate excellent in the high frequency characteristic can be manufactured.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Subsequently, an embodiment of an electronic component mounting board and a manufacturing method thereof according to the present invention will be described with reference to the drawings.
[0022]
(1) First embodiment
FIG. 1 is a cross-sectional view showing a configuration example of an electronic component mounting board 100 as a first embodiment according to the present invention.
In this embodiment, a predetermined circuit wiring electrode and a terminal electrode supported by an insulating supporting member are provided, and an electrode with a predetermined thickness and a side edge is vertically formed, and the circuit wiring electrode and the terminal electrode are configured. In addition to improving the impedance characteristics (skin effect), it is possible to provide an electronic component mounting board or the like that is excellent in thin mounting and excellent in high-frequency characteristics.
[0023]
The electronic component mounting substrate 100 shown in FIG. 1 is suitable for application to a high-frequency compatible semiconductor chip mounting substrate for mounting a semiconductor (LSI) chip or the like made by a UFPL (ultra fine pitch lead frame) process technology. At least an insulating support member 22 that also serves as a support reinforcing material is provided.
[0024]
At least an organic insulating material is used for the support member 22. In this example, the supporting member 22 is a sheet of thermosetting PPE (polyphenylene ether) that is adhesively cured. In addition, when a heat resistance is required, a polyimide-based support member 22 is used. In the electronic component mounting substrate 100 having a low operating frequency, an epoxy-based carrier member 22 is used. The high-frequency carrier member 22 is selectively used.
[0025]
A circuit wiring electrode 13 is supported on the support member 22. The circuit wiring electrode 13 has wiring electrodes 13A and 13C and a die pad portion 13B formed by electroplating instead of a wiring pattern formed by etching a copper foil. A semiconductor chip capable of wire bonding, which is an example of an electronic component, is bonded to the die pad portion 13B with an adhesive 18 interposed therebetween. The electronic component is not limited to this, and may be a flip chip type semiconductor chip capable of surface bonding.
[0026]
A plurality of terminal electrodes 15A, 15B and the like are connected to the semiconductor chip 11 and / or the wiring electrodes 13A, 13C. The terminal electrodes 15A and 15B are used when connecting to an external printed wiring board or the like. The semiconductor chip 11 is connected to a terminal electrode (external lead) 15A via a gold wire 14A on one side, and connected to the terminal electrode 15B via a gold wire 14B on the other side. Depending on the electronic component mounting substrate 100, several tens to several hundreds of terminal electrodes 15A and 15B are provided.
[0027]
In this example, the wiring electrodes 13A and 13C are made of gold, nickel and copper in the case of the wire bonding method, and made of gold and copper in the case of the flip chip method.
[0028]
Part of the terminal electrodes 15A, 15B, the die pad portion 13B, and the wiring electrodes 13A, 13C are all formed by electrolytic plating. For example, the wiring electrodes 13A and 13C and the terminal electrodes 15A and 15B are formed by using a non-plated member selectively formed on both surfaces of a conductive base material that can be plated and etched as a mask, and simultaneously applying the conductive members on both surfaces of the base material. After plating, the base material is selectively removed by etching.
[0029]
In the high-frequency compatible electronic component mounting substrate 100, the semiconductor chip mounting area is used without being filled with the sealing member. This is because air has a dielectric constant εr = 1. Of course, an insulating sealing member may be filled in the mounting region depending on the application. In that case, a mold resin is used.
[0030]
Next, a method for manufacturing the semiconductor chip mounting substrate 100 will be described. 2 to 7 are process diagrams showing examples of forming the semiconductor chip mounting substrate 100 (Nos. 1 to 6).
In this example, a non-plated member is selectively formed on both surfaces of a conductive substrate that can be plated and etched, and then the conductive member is simultaneously plated on both surfaces of the substrate using the non-plated member as a mask. 13A and 13C and terminal electrodes 15A and 15B are formed. And the case where the insulating support member 22 is joined to the wiring electrode formation surface side of the base material is assumed. The electronic component is assumed to be a wire bond type semiconductor chip. The plating may be electrolytic plating or electroless plating. However, since electroless plating is difficult to control the film thickness, in this example, the case of electrolytic plating is taken as an example.
[0031]
Using this as a manufacturing condition, first, a copper alloy plate 20 having a thickness t as shown in the cross-sectional view of FIG. 2A, which is an example of a conductive base material that can be plated and etched, is prepared. The copper alloy plate 20 may be made of the same material as that of a normal lead frame. The thickness t of the copper alloy plate 20 is about 100 to 200 μm. In this example, the copper alloy plate 20 with t = 100 μm is used. The copper alloy plate 20 is used as a temporary substrate in the process of manufacturing the electronic component mounting substrate 100, and a part of the copper alloy plate 20 constitutes the core material of the terminal electrodes 15A and 15B.
[0032]
When such a copper alloy plate 20 is prepared, the copper alloy plate 20 is formed in order to form the wiring electrodes 13A and 13C, the circuit wiring electrode 13 including the die pad portion 13B for the chip, and the predetermined number of terminal electrodes 15A and 15B. A non-plated member is selectively formed on both sides of the substrate. For example, in FIG. 2B, a resist 16 ′ having a film thickness of about 10 μm to 40 μm, which is an example of a non-plated member, is applied to both surfaces and end surfaces of the copper alloy plate 20. This is because the resist 16 'is patterned by a photographic method.
[0033]
In the case of a fine pattern, a thin resist 16 'is used. Since it is easy to obtain a uniform thickness, it is preferable to use a resist film 16 ′ having a dry film shape. The same effect can be obtained even when a liquid resist is used. The width shapes of the wiring electrodes 13A and 13C and the terminal electrodes 15A and 15B are determined by the resist pattern. In this example, a resist 16 'formed into a dry film is used. Wiring electrodes 13A and 13C and terminal electrodes 15A and 15B as designed with little variation after plating can be obtained.
[0034]
Thereafter, a reticle (glass dry plate) 26 as an example of the first mask member in FIG. 2C is aligned with one surface of the copper alloy plate 20. The reticle 26 is formed by printing circuit wiring electrode patterns such as predetermined wiring electrodes 13A and 13C and a die pad portion 13B. A reticle 27 as an example of a second mask member is aligned with the other surface of the copper alloy plate 20. A predetermined number of terminal electrode patterns are baked on the reticle 27.
[0035]
Then, the circuit wiring electrode pattern is exposed to the resist 16 'on one side of the copper alloy plate 20 through the reticle 26, and at the same time, the terminal electrode pattern is exposed to the resist 16' on the other side of the copper alloy plate 20 through the reticle 27. To do. This is because the same metal is plated on both surfaces of the copper alloy plate 20 at the same time. At this time, the resist 16 ′ is exposed using a double-side exposure machine.
[0036]
The resist 16 ′ on the end surface of the copper alloy plate 20 is also exposed. This is because the end face is not plated. Thereafter, after the resist 16 ′ is developed, an unnecessary resist film is removed. By this exposure process, a resist pattern 16 is formed on one surface of the copper alloy plate 20, and a resist pattern 17 is formed on the other surface. A resist pattern 17 'for plating protection is also formed on the end surface.
[0037]
When this resist pattern 16 is viewed from the upper surface of the copper alloy plate 20, for example, it is as shown in FIG. 3A. In the plan view of FIG. 3A, a resist pattern 16 can be formed on one surface of the copper alloy plate 20 by inverting the wiring electrode patterns P1, P3 and the die pad pattern P2.
[0038]
In this example, a resist film 17 ′ is also formed on the side wall of the copper alloy plate 20 that becomes the terminal electrodes 15A and 15B. This prevents the plating from growing on the side wall of the copper alloy plate 20 that becomes the terminal electrodes 15A and 15B. By doing so, the etchant is eroded to the end faces of the terminal electrodes 15A and 15B during the etching of the copper alloy plate.
[0039]
3B is a cross-sectional view of the copper alloy plate 20 shown in FIG. In FIG. 3B, the resist pattern 17 is obtained by inverting the terminal electrode patterns P4 and P5. Several tens to several hundreds of terminal electrodes 15A and 15B are electrically separated from the copper alloy plate 20 by the terminal electrode patterns P4 and P5.
[0040]
4A is a cross-sectional view taken along arrow Y1-Y2 of the copper alloy plate 20 shown in FIG. 3A. In FIG. 4A, resist patterns 16 and 17 are obtained by inverting the wiring electrode pattern P3 and the terminal electrode pattern P5. When such resist patterns 16 and 17 can be formed, the copper alloy plate 20 is set in the electroplating apparatus 300 shown in FIG. 4B, and the resist patterns 16 and 17 are used as masks on both sides of the copper alloy plate 20 simultaneously. The conductive member is plated to form predetermined wiring electrodes 13A and 13C, a die pad portion 13B, and terminal electrodes 15A and 15B.
[0041]
A known electrolytic plating method is applied to the electroplating apparatus 300. The electroplating apparatus 300 includes an electrolytic solution 202 in a plating container 201, a pair of anodes 203A and 203B, and a DC power supply 204 and an ammeter 205 outside thereof. A desired conductive member may be used for the anodes 203A and 203B.
[0042]
The copper alloy plate 20 serving as a plating base material is connected to the negative terminal of the DC power source 204, and the anodes 203A and 203B are connected to the positive terminal of the DC power source 204 through the ammeter 205. The electrolytic solution 202 is replaced by a conductive member. For example, an aqueous solution of copper sulfate is used as the electrolytic solution 202 during copper plating. The conductive member is preferably a metal material with good etching mask and soldering. In this example, gold, nickel and copper are used for the conductive member (plating member).
[0043]
In this example, when the semiconductor chip 11 is a wire bonding method, the copper alloy plate 20 is plated in the order of nickel, gold, nickel, and copper using the resist patterns 16 and 17 as a mask. In the case of the flip chip method, plating is performed in the order of gold and copper. Wiring electrodes 13A and 13C and terminal electrodes 15A and 15B having a good skin effect can be formed by multilayering the plating.
[0044]
The plating current I in each plating member is adjusted while looking at the ammeter 205, and the overall thickness of the circuit wiring electrode 13 is controlled by adjusting the thickness of each plating member. The thickness of each plated member increases the plating current I, and the plating amount can be increased by increasing the energization time.
[0045]
In this example, the plating current is adjusted so that the Ni plating of the first layer is about 5 μm, the Au plating is about 0.5 μm, the Ni plating of the second layer is about 5 μm, and the Cu plating is about 30 μm. Made. Thereby, compared with the case where a wiring pattern is formed with the copper foil of an organic substrate, the circuit wiring electrode 13 etc. with thickness can be formed.
[0046]
When the plating current I is controlled in this way and then the resist films 16, 17 and the like are removed, circuit wiring including wiring electrodes 13A, 13C and a die pad portion 13B on one surface of the copper alloy plate 20 as shown in FIG. 5A. The electrode 13 can be formed. Only the terminal electrodes 15A and 15B can be formed on the other surface of the copper alloy plate 20 as shown in FIG. 5B. In this example, the plating is not grown on the side wall of the copper alloy plate 20.
[0047]
At this time, the circuit wiring electrode 13 and the terminal electrodes 15A and 15B are not electrically separated. The copper alloy plate 20 is short-circuited. 6A is a cross-sectional view of the circuit electrode substrate 20 ′ shown in FIG. In the subsequent formation example, a process of forming a cross section of the electronic component mounting substrate 100 will be described.
[0048]
That is, the circuit wiring electrode 13 in which Ni / Au / Ni / Cu is laminated can be formed on one surface of the copper alloy plate 20 shown in FIG. Terminal electrodes 15A and 15B in which Ni / Au / Ni / Cu are laminated can also be formed on the other surface of the copper alloy plate 20.
[0049]
In this example, since the resist 16 ′ formed into a dry film is used, the wiring electrodes 13A and 13C and the terminal electrodes 15A and 15B having a pattern width as designed with little variation can be obtained after plating. Moreover, the terminal electrodes 15A and 15B could be reinforced by leaving the copper alloy plate 20 under the wiring electrodes 13A and 13C in a predetermined shape. Here, the copper alloy plate 20 plated with the patterns related to the circuit wiring electrode 13 and the terminal electrodes 15A and 15B is hereinafter also referred to as a circuit electrode substrate 20 ′.
[0050]
6B, an insulating carrier member 22 is formed on the wiring electrode formation surface side of the circuit electrode substrate 20 ′. Here, a long resin sheet member having a film thickness of about 15 μm to 30 μm is bonded as the supporting member 22. The resin sheet member is separated when forming one package.
[0051]
The carrier member 22 may be either a sheet made of a resin member or a prepreg sheet. When heat resistance is required, a polyimide resin member is used. For high frequency, a thermosetting PPE (polyphenylene ether) resin member is used. For general use, it is used separately from the epoxy system, and the sheet is bonded, and then the resin member is cured.
[0052]
Since the circuit wiring electrode 13 including the wiring electrodes 13A and 13C and the die pad portion 13B is lined by such a supporting member 22, the copper alloy plate 20 under these circuit wiring electrodes 13 (semiconductor chip mounting side) is removed. Also, the carrying posture can be maintained.
[0053]
Thereafter, in FIG. 7A, a part or all of the copper alloy plate 20 used as a temporary substrate from the circuit electrode substrate 20 ′ with the supporting member is used as a mask for each of the circuit wiring electrode 13 and the terminal electrodes 15A and 15B. Selectively etch away. At this time, a weak alkaline aqueous solution adjusted in pH (pH) is used as a chemical that does not violate nickel for etching copper.
[0054]
For example, an aqueous solution in which ammonia pH is adjusted to about 8.0 to 8.5 is used as a dedicated etchant for copper. This weak alkaline aqueous solution is etched at 45 ° C. By this etching, the unnecessary portion of the copper alloy plate 20 is removed, and the circuit wiring electrode 13 including the wiring electrodes 13A and 13C and the die pad portion 13B and the plurality of terminal electrodes 15A and 15B are electrically separated simultaneously.
[0055]
In the case of an electrode structure having a nickel layer, since nickel is not etched with a weak alkaline aqueous solution, the etching is terminated when a nickel surface appears. The circuit wiring electrode 13 having a gold-nickel structure is only copper etching.
[0056]
By this element separation, a space 28 is generated under the circuit wiring electrode 13C. At the same time, the circuit wiring electrode 13 is exposed. After the etching of the copper alloy plate 20, the nickel surface is preferably etched so that the gold surface appears. Even after the circuit electrode substrate is formed, the wiring electrodes 13A and 13C and the terminal electrodes 15A and 15B have the same gold surface (layer). This is because the gold surface is easily soldered. A special acidic etchant is used at a temperature of 35 ° C. for the nickel etching solution. If the gold surface appears at this time, the etching is finished.
[0057]
Thereafter, the semiconductor chip 11 is mounted under the die pad portion 13B of the circuit electrode substrate 20 ′. At this time, the circuit electrode substrate 20 ′ from which the circuit wiring electrode 13 is exposed may be turned upside down, and the posture may be adjusted so that the opening portion faces upward. Here, the semiconductor chip 11 is bonded to the die pad portion 13B of the circuit wiring electrode 13 by die bonding using the adhesive 18.
[0058]
Between one pad electrode 19A of the semiconductor chip 11 and the wiring electrode 13A, for example, thermocompression bonding is performed by a gold wire 14A, and the other pad electrode 19B and the wiring electrode 13C of the semiconductor chip 11 are heated by another gold wire 14B. Crimp bonding. Thereafter, the resin sheet member is cut and separated into a package with a supporting member.
[0059]
At this time, the resin sheet member can be cut into an assembly composed of several chips, sizes, and packages. In this example, the resin sheet member is individually cut to complete the electronic component mounting board 100 for high frequency as shown in FIG.
[0060]
Of course, an insulating sealing member may be formed in the space 28 after the semiconductor chip 11 is mounted. In that case, an epoxy mold resin is used for the sealing member. In this sealing step, the mold resin is sealed inside the circuit electrode substrate 20 ′ so as to ensure a thickness that hides the gold wires 14A and 14B.
[0061]
Thus, according to the electronic component mounting substrate 100 as the first embodiment of the present invention, the side edges are vertically cut with a predetermined thickness as compared with the wiring pattern formed by etching the copper foil. The wiring electrodes 13A and 13C and the terminal electrodes 15A and 15B can be configured, and the impedance characteristics (skin effect) of the wiring electrodes 13A and 13C and the terminal electrodes 15A and 15B can be improved. Moreover, since the wiring electrodes 13A and 13C and the terminal electrodes 15A and 15B can be formed with high reproducibility by plating, patterning of 10 μm or less can be provided accurately and inexpensively in line and space (L / S). Thereby, high-frequency compatible semiconductor chips can be mounted with high density.
[0062]
In addition, according to the method for manufacturing the electronic component mounting substrate 100, stable wiring electrodes 13A and 13C and terminal electrodes 15A and 15B can be obtained, so that circuit design can be easily performed. Since the impedance characteristics of the wiring electrodes 13A and 13C and the terminal electrodes 15A and 15B are excellent, high-precision inductance and capacitance can be created. The terminal electrodes 15A and 15B can be formed without a through-hole plating process as in the conventional method. Thereby, it is possible to manufacture a semiconductor chip mounting substrate excellent in thin mounting and excellent in high frequency characteristics.
[0063]
(2) Second embodiment
FIG. 8 is a cross-sectional view showing a configuration example of an electronic component mounting board 200 as a second embodiment according to the present invention. In this embodiment, a flip chip type semiconductor chip 31 capable of surface bonding is applied instead of the semiconductor chip 11 capable of wire bonding for electronic components.
[0064]
The electronic component mounting substrate 200 shown in FIG. 8 is suitable for application to a high frequency compatible mounting substrate, and has an insulating support member 22 that also serves as a support reinforcing material as in the first embodiment. At least an organic insulating material is used for the support member 22. In this example, the supporting member 22 is a sheet of thermosetting PPE (polyphenylene ether) that is adhesively cured. In addition, when a heat resistance is required, a polyimide-based support member 22 is used. An epoxy-based support member 22 is used for an electronic component mounting board having a low operating frequency. The high-frequency carrier member 22 is selectively used.
[0065]
A predetermined number of terminal electrodes 15A and 15B and predetermined circuit wiring electrodes 33A to 33G are supported on the supporting member 22. A flip chip type semiconductor chip 31 as an example of an electronic component is mounted under the circuit wiring electrodes 33A to 33G. The semiconductor chip 31 has a plurality of bump electrodes (area bumps) 34A to 34G.
[0066]
The bump electrode 34A of the semiconductor chip 31 is connected to the circuit wiring electrode 33A, the bump electrode 34B is connected to the circuit wiring electrode 33B, the bump electrode 34C is connected to the circuit wiring electrode 33C, and the bump electrode 34D is connected to the circuit wiring electrode 33D. The bump electrode 34E is connected to the circuit wiring electrode 34E, the bump electrode 34F is connected to the circuit wiring electrode 33F, and the bump electrode 34G is connected to the circuit wiring electrode 34G. Each of the circuit wiring electrodes 33A to 33G is connected to the terminal electrodes 15A, 15B and the like. Depending on the electronic component mounting substrate 200, several tens to several hundreds of terminal electrodes 15A and 15B are provided.
[0067]
The circuit wiring electrodes 33A to 33G are formed by plating a desired conductive member on one surface of a copper alloy plate 20 as an example of a conductive base material that can be plated and etched together with the terminal electrodes 15A and 15B. The copper alloy plate 20 is formed by selectively etching away the copper alloy plate 20. All of the circuit wiring electrodes 33A to 33G and part of the terminal electrodes 15A and 15B are formed by electrolytic plating.
[0068]
The circuit wiring electrodes 33A to 33G are plated with gold having a film thickness of about 0.5 μm and copper having a film thickness of about 30 μm in order, and the terminal electrodes 15A and 15B are formed by etching residues of the copper alloy plate 20 as core materials. One side of the core material is plated in the order of gold and copper having the same film thickness.
[0069]
If formed in this way, the copper alloy plate 20 can be used as a temporary substrate up to the supporting member forming step, and the terminal electrodes 15A and 15B using the etching residual portion of the copper alloy plate 20 can be configured. it can.
[0070]
In addition, the side edges of the circuit wiring electrodes 33A to 33G can be shaped so as to be vertically cut, and the circuit edges can be formed with higher precision than the case where the wiring pattern is formed by etching the copper foil of the organic substrate. The electrodes 33A to 33G and the wiring electrodes 33A to 33G having an excellent skin effect are obtained, and are optimal for super-high frequency operation. The terminal electrodes 15A and 15B can also ensure a certain height, and an electrode with low internal resistance can be obtained.
[0071]
In this electronic component mounting substrate 200, the mounting area of the semiconductor chip 31 is used as it is. This is because air has a dielectric constant εr = 1. Of course, an insulating sealing member may be filled according to the application. In that case, a mold resin is used for the sealing member.
[0072]
As described above, according to the electronic component mounting substrate 200 as the second embodiment of the present invention, the circuit wiring with a predetermined thickness and a predetermined pattern edge is formed as compared with the case where the wiring pattern is formed by etching the copper foil. The electrodes 33A to 33G and the terminal electrodes 15A and 15B can be formed at the same time. In particular, since the side edges of the circuit wiring electrodes 33 </ b> A to 33 </ b> G can be vertically formed, the skin effect can be made uniform.
[0073]
In addition, according to the electronic component mounting substrate 200, since the support member 22 made of an organic insulating material is used, the flip chip semiconductor chip mounting excellent in high frequency characteristics suitable for application to an ultrahigh frequency circuit can be used. A mounting substrate can be manufactured.
[0074]
【The invention's effect】
As described above, the electronic component mounting substrate according to the present invention includes the predetermined circuit wiring electrode and the terminal electrode carried on the insulating carrier member, and the circuit wiring electrode and the terminal electrode can be plated and etched. Using a non-plated member selectively formed on both sides of a conductive base material as a mask, plating the conductive member on both sides of the base material at the same time, and then selectively removing the base material by etching It is.
[0075]
With this configuration, it is possible to embody a circuit wiring electrode and terminal electrode structure having a predetermined thickness and a side edge vertically vertical compared to a wiring pattern formed by etching a copper foil. Impedance characteristics (skin effect) can be made uniform. At the same time, high-frequency electronic components can be mounted with high density. Therefore, it is possible to provide an electronic component mounting board that is excellent in thin mounting and excellent in high-frequency characteristics.
[0076]
According to the method for manufacturing an electronic component mounting substrate according to the present invention, the non-plated member is selectively formed on both surfaces of the conductive base material, and then the conductive member is simultaneously formed on both surfaces of the base material using the non-plated member as a mask. To form a predetermined circuit wiring electrode and terminal electrode, and further, an insulating support member is joined to the circuit wiring electrode forming surface side of the base material, and then a circuit electrode substrate having the support member and the circuit wiring electrode All or a part of the conductive substrate is removed by etching.
[0077]
With this configuration, it is possible to form circuit wiring electrodes, terminal electrodes, and the like with a predetermined thickness and with a good pattern reproducibility with a high reproducibility compared with the case of forming a wiring pattern by etching a copper foil. In particular, since the side edges of the circuit wiring electrodes can be formed vertically, impedance characteristics (skin effect) can be made uniform.
[0078]
In addition, since stable circuit wiring electrodes and terminal electrode shapes can be obtained, circuit design can be easily performed. Since the impedance characteristics of the circuit wiring electrode and the terminal electrode are excellent, it is possible to create a highly accurate inductance and capacitance.
[0079]
The present invention is extremely suitable when applied to a high-frequency mounting substrate on which a semiconductor chip that operates in an ultra-high frequency region is mounted.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration example of an electronic component mounting board 100 as a first embodiment according to the present invention.
FIGS. 2A to 2C are process diagrams showing a first example of forming a semiconductor chip mounting substrate 100; FIGS.
FIGS. 3A and 3B are process diagrams showing a second example of forming a semiconductor chip mounting substrate 100; FIGS.
FIGS. 4A and 4B are process diagrams showing a formation example (part 3) of the semiconductor chip mounting substrate 100; FIGS.
FIGS. 5A and 5B are process diagrams showing a formation example (No. 4) of the semiconductor chip mounting substrate 100; FIGS.
FIGS. 6A and 6B are process diagrams showing a formation example (No. 5) of the semiconductor chip mounting substrate 100; FIGS.
FIGS. 7A and 7B are process diagrams showing a formation example (No. 6) of the semiconductor chip mounting substrate 100; FIGS.
FIG. 8 is a cross-sectional view showing a configuration example of an electronic component mounting board 200 as a second embodiment according to the present invention.
FIG. 9 is a cross-sectional view showing a configuration example of a mold resin sealing substrate 10 according to a conventional example.
FIGS. 10A and 10B are process diagrams showing an example of forming a mold resin sealing substrate 10 during etching. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11, 31 ... Semiconductor chip (electronic component), 13 ... Circuit wiring electrode, 13A, 13C, 33A-33G ... Wiring electrode, 13B ... Die pad part, 14A, 14B ... Gold wire, 15A, 15B ... terminal electrode, 16, 17 ... resist film (non-plated member), 20 ... copper alloy plate (conductive base material), 22 ... support member, 26, 27 ... Reticle (first and second mask members), 34A to 34G ... bump electrodes, 100, 200 ... electronic component mounting substrate, 300 ... electroplating apparatus

Claims (6)

メッキ及びエッチング可能な導電性の基材の両面に非メッキ部材を形成する工程と、
所定の回路電極をパターニングした第１のマスク部材を前記導電性の基材の一方の面に位置合わせする工程と、
所定数の端子電極をパターニングした第２のマスク部材を前記導電性の基材の他方の面に位置合わせする工程と、
前記導電性の基材の一方の面の非メッキ部材に前記第１のマスク部材を通して、ダイパッド部と配線電極を含む回路配線電極のパターンを露光し、同時に、前記導電性の基材の他方の面の非メッキ部材に前記第２のマスク部材を通して端子電極のパターンを露光する工程と、
前記回路配線電極と前記端子電極の各パターンを開口する非メッキ部材をマスクにして電解メッキ法により前記導電性の基材に導電部材をメッキし、該メッキ電流を調整して前記回路電極及び端子電極の厚みを制御して、前記導電性の基材の両面に所定の回路配線電極及び端子電極を形成する工程と、
前記基材の回路配線電極形成面側の全面に絶縁樹脂シートからなる担持部材を接合する工程と、
前記担持部材及び回路配線電極を有する回路電極基板から前記導電性の基材を、当該基材の前記担持部材が接合された面と反対側の面から、当該面の一部の領域を当該基材の厚さ方向全域でエッチングにより除去して前記ダイパッド部に接合される電子部品の実装空間を形成するとともに、当該エッチング時に、前記配線電極を外部リード端子としての前記端子電極に連結する前記導電性の基材の一部を前記実装空間の周囲に残す工程と
を含む電子部品実装基板の製造方法。Forming a non-plated member on both sides of a conductive substrate that can be plated and etched;
Aligning a first mask member patterned with a predetermined circuit electrode with one surface of the conductive substrate;
Aligning a second mask member patterned with a predetermined number of terminal electrodes with the other surface of the conductive substrate;
A pattern of a circuit wiring electrode including a die pad portion and a wiring electrode is exposed through the first mask member to a non-plated member on one surface of the conductive base material, and at the same time, the other side of the conductive base material is exposed. a step of exposing a pattern of terminal electrodes through said second mask member to the non-plated member surface,
A conductive member is plated on the conductive substrate by electrolytic plating using a non-plated member opening each pattern of the circuit wiring electrode and the terminal electrode as a mask, and the plating current is adjusted to adjust the circuit electrode and the terminal. Controlling the thickness of the electrodes to form predetermined circuit wiring electrodes and terminal electrodes on both surfaces of the conductive substrate ; and
Bonding a supporting member made of an insulating resin sheet to the entire surface of the substrate on which the circuit wiring electrode is formed; and
The conductive base material from the circuit electrode substrate having the support member and the circuit wiring electrode, and a partial region of the surface from the surface of the base material opposite to the surface where the support member is bonded. The conductive material that is removed by etching in the entire thickness direction of the material to form a mounting space for the electronic component to be bonded to the die pad portion, and at the time of the etching, the wiring electrode is connected to the terminal electrode as an external lead terminal. And a step of leaving a part of the conductive substrate around the mounting space . 前記担持部材には有機樹脂材料が使用される
請求項１に記載の電子部品実装基板の製造方法。The manufacturing method of the electronic component mounting substrate according to claim 1, wherein an organic resin material is used for the supporting member. 前記導電性の基材を除去した後に、前記回路配線電極の前記ダイパッド部上に電子部品を実装する
請求項１または２に記載の電子部品実装基板の製造方法。The method of manufacturing an electronic component mounting substrate according to claim 1 , wherein an electronic component is mounted on the die pad portion of the circuit wiring electrode after the conductive base material is removed. 前記電子部品はワイヤーボンディング可能な半導体チップである
請求項３に記載の電子部品実装基板の製造方法。The manufacturing method of the electronic component mounting substrate according to claim 3, wherein the electronic component is a wire-bondable semiconductor chip. 前記電子部品は面接合可能なフリップチップ方式の半導体チップである
請求項３に記載の電子部品実装基板の製造方法。The method of manufacturing an electronic component mounting board according to claim 3, wherein the electronic component is a flip chip type semiconductor chip capable of surface bonding. 絶縁樹脂シートからなる担持部材と、A support member made of an insulating resin sheet;
前記担持部材の一方の面に担持された、ダイパッド部および複数の配線電極を含む回路配線電極と、A circuit wiring electrode supported on one surface of the supporting member, including a die pad portion and a plurality of wiring electrodes;
前記回路配線電極の前記ダイパッド部に接合され、各端子が前記複数の配線電極それぞれと電気的に接続された電子部品と、An electronic component bonded to the die pad portion of the circuit wiring electrode and each terminal electrically connected to each of the plurality of wiring electrodes;
前記複数の配線電極から前記電子部品の周囲に立設し、導電性の基材をウエットエッチングして分離されたときに残る湾曲側面、および、前記担持部材と反対の側に前記電子部品よりも突出した端面をそれぞれが有する複数のエッチング形成プラグと、Standing around the electronic component from the plurality of wiring electrodes, the curved side surface left when the conductive base material is separated by wet etching, and the side opposite to the supporting member than the electronic component A plurality of etched plugs each having a protruding end face;
前記複数のエッチング形成プラグの各端面に形成された外部リード電極としての複数の端子電極と、A plurality of terminal electrodes as external lead electrodes formed on each end face of the plurality of etching formed plugs;
を有する電子部品実装基板。An electronic component mounting board having:
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