JP2558574B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2558574B2 JP2558574B2 JP4109289A JP10928992A JP2558574B2 JP 2558574 B2 JP2558574 B2 JP 2558574B2 JP 4109289 A JP4109289 A JP 4109289A JP 10928992 A JP10928992 A JP 10928992A JP 2558574 B2 JP2558574 B2 JP 2558574B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- insulating layer
- copper
- semiconductor device
- thin plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
Description
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置に係り、パ
ワーデバイス、特にパワーモジュールの基板構造に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a power device, and more particularly to a substrate structure of a power module.
【０００２】[0002]
【従来の技術】従来、パワーモジュールは図２に示すよ
うに、半導体チップ４と金属基板１との電気的な絶縁性
を保つために内部でＡｌ2 Ｏ3 のようなセラミックス絶
縁層２を金属基板１上に半田付け３する構造が最も一般
的な方法として採用されている。2. Description of the Related Art Conventionally, as shown in FIG. 2, a power module is internally provided with a ceramic insulating layer 2 such as Al 2 O 3 in order to maintain electrical insulation between the semiconductor chip 4 and the metal substrate 1. The structure of soldering 3 on the substrate 1 is adopted as the most general method.
【０００３】[0003]
【発明が解決しようとする課題】この構造において、金
属基板１が銅でセラミックス絶縁層２がＡｌ2 Ｏ3 であ
る場合、Ａｌ2 Ｏ3 と銅の間には熱膨張係数において銅
はＡｌ2 Ｏ3 のほぼ３倍という大きな差があるため（Ａ
ｌ2 Ｏ3 は６．２×１０-6／℃、銅は１６．７×１０-6
／℃）、両者を接合する半田３の厚さが０．１〜０．２
ｍｍ程度ではＡｌ2 Ｏ3 絶縁層２上の半導体チップ４や
銅基板１の温度が１００℃以上に上昇した場合、銅の膨
張によって絶縁層２のＡｌ2 Ｏ3 に引張応力が加わり、
かつ半田層３が薄いために、この半田層３における引張
応力の緩和効果が小さく、Ａｌ2 Ｏ3 絶縁層２に割れを
生じるという問題がある。[Problems that the Invention is to Solve In this structure, when the metal substrate 1 is a ceramic insulating layer 2 with copper and Al 2 O 3, copper in the thermal expansion coefficient between the Al 2 O 3 and copper Al 2 There is a large difference of about 3 times that of O 3 (A
L 2 O 3 is 6.2 × 10 −6 / ° C., copper is 16.7 × 10 −6
/ ° C), the thickness of the solder 3 for joining the two is 0.1 to 0.2
When the temperature of the semiconductor chip 4 or the copper substrate 1 on the Al 2 O 3 insulating layer 2 rises to 100 ° C. or above, tensile stress is applied to the Al 2 O 3 of the insulating layer 2 due to the expansion of copper.
Moreover, since the solder layer 3 is thin, the effect of relaxing the tensile stress in the solder layer 3 is small, and there is a problem that the Al 2 O 3 insulating layer 2 is cracked.
【０００４】このような問題を解決するためには、半田
層３の厚さを大きくすることが最も効果的と考えられる
が、金属基板１と絶縁層２の半田付工程で単に半田を多
く供給しても、半田は周囲に流れ出すだけで半田層３の
厚みを増すことはできない。In order to solve such a problem, it is considered most effective to increase the thickness of the solder layer 3. However, a large amount of solder is simply supplied in the soldering process of the metal substrate 1 and the insulating layer 2. However, the thickness of the solder layer 3 cannot be increased because the solder only flows to the surroundings.
【０００５】[0005]
【課題を解決するための手段】この発明は上記のような
問題を解決すべく検討の結果、得られたものであって、
金属基板と絶縁層との半田層の厚さを実質的に大きくす
ることにより絶縁層の割れが発生せず、かつパワーサイ
クル寿命の長いパワーモジュールを提供しようとするも
のである。The present invention has been obtained as a result of investigations for solving the above-mentioned problems.
It is an object of the present invention to provide a power module that does not crack the insulating layer and has a long power cycle life by substantially increasing the thickness of the solder layer between the metal substrate and the insulating layer.
【０００６】即ち、この発明の半導体装置は熱膨張係数
の異なる材料からなる金属基板と絶縁層を半田層を介し
て接合し、上記絶縁層上に半導体チップを搭載した半導
体装置において、上記半田層を２層とし、この２層の半
田層の間に０．５ｍｍ厚以下の金属薄板を介在させたこ
と、さらにはこの０．５ｍｍ厚以下の金属薄板に複数個
の貫通孔を形成し、該貫通孔内に半田を埋め込んだこと
を特徴とするものである。That is, the semiconductor device of the present invention is a semiconductor device in which a metal substrate made of a material having a different coefficient of thermal expansion is joined to an insulating layer via a solder layer, and a semiconductor chip is mounted on the insulating layer. In two layers, a metal thin plate having a thickness of 0.5 mm or less is interposed between the two solder layers, and a plurality of through holes are formed in the metal thin plate having a thickness of 0.5 mm or less. It is characterized in that solder is embedded in the through hole.
【０００７】[0007]
【作用】この発明は熱膨張係数の異なる材料からなる金
属基板と絶縁層を半田付けし、該絶縁層上に半導体チッ
プを搭載して半導体装置を得るに際し、上記金属基板と
絶縁層を半田付けする半田層の間に金属薄板を介在させ
ることによって、金属基板と絶縁層間の半田層を実質的
に厚くすることを可能とし、これによって金属基板の熱
膨張を半田層において緩和せしめ、絶縁層にまで及ぶこ
とを防止することができるのである。According to the present invention, when a metal substrate and an insulating layer made of materials having different thermal expansion coefficients are soldered and a semiconductor chip is mounted on the insulating layer to obtain a semiconductor device, the metal substrate and the insulating layer are soldered. By interposing a thin metal plate between the solder layers, it is possible to substantially thicken the solder layer between the metal substrate and the insulating layer, thereby alleviating thermal expansion of the metal substrate in the solder layer, It is possible to prevent the extension.
【０００８】[0008]
【実施例】以下、この発明をその実施例を示す図に基い
て詳細に説明する。図１はこの発明の一実施例を示す断
面図であって、１が銅基板、２がＡｌ2 Ｏ3 セラミック
ス絶縁層、４は絶縁層２上に半田６にて搭載した半導体
チップである。そして銅基板１と絶縁層２とは銅基板５
を介在させて半田層３ａ、３ｂにて接合させたものであ
る。図１において、例えば半田層３ａ、３ｂを夫々０．
２ｍｍ厚とし、銅薄板５も同じく０．２ｍｍ厚に形成さ
せたとすると、絶縁層２上に搭載した半導体チップ４、
銅基板１および銅薄板５などの温度が１００℃以上に上
昇し、銅基板１が膨張しても銅薄板５はその厚さが薄い
ので銅の熱膨張係数そのままの膨張、収縮は起らずに銅
薄板５を挟む半田３ａ、３ｂの膨張、収縮特性の影響を
受けることになる。このため、実質的な半田層の厚さを
０．４〜０．６ｍｍと見做すことができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing its embodiments. FIG. 1 is a sectional view showing an embodiment of the present invention, in which 1 is a copper substrate, 2 is an Al 2 O 3 ceramic insulating layer, and 4 is a semiconductor chip mounted on the insulating layer 2 with solder 6. The copper substrate 1 and the insulating layer 2 are the copper substrate 5
And the solder layers 3a and 3b are bonded to each other. In FIG. 1, for example, the solder layers 3a and 3b are respectively connected to 0.
Assuming that the copper thin plate 5 has a thickness of 2 mm and the copper thin plate 5 also has a thickness of 0.2 mm, the semiconductor chip 4 mounted on the insulating layer 2,
Even if the temperature of the copper substrate 1 and the copper thin plate 5 rises to 100 ° C. or higher and the copper substrate 1 expands, the copper thin plate 5 has a small thickness, so that the thermal expansion coefficient of copper does not expand or contract as it is. The solder 3a and 3b sandwiching the copper thin plate 5 are affected by the expansion and contraction characteristics. Therefore, the substantial thickness of the solder layer can be regarded as 0.4 to 0.6 mm.
【０００９】この半田層は銅基板および絶縁層に比べて
軟かいこと、および上記のように半田層の厚さが大きい
ことから半田層の応力緩和効果が有効に作用し、銅基板
および絶縁層の膨張、収縮特性に十分対応することがで
き、この結果銅基板の熱膨張をこの半田層で緩和するこ
とができ、絶縁層に割れが生ずるのを防止することがで
きるのである。Since the solder layer is softer than the copper substrate and the insulating layer, and the thickness of the solder layer is large as described above, the stress relaxation effect of the solder layer effectively acts, and the copper substrate and the insulating layer are effective. The thermal expansion of the copper substrate can be alleviated by this solder layer, and cracking of the insulating layer can be prevented.
【００１０】上記したこの発明において、半田層３ａ、
３ｂの間に銅薄板５を介在させる方法としては、例えば
銅薄板５の両面に成形用半田を圧着しておいて半田付け
工程に供すればよい。In the above-mentioned invention, the solder layer 3a,
As a method of interposing the copper thin plate 5 between 3b, for example, molding solder may be pressure-bonded to both surfaces of the copper thin plate 5 and subjected to the soldering step.
【００１１】図３は、この発明の他の実施例を示す断面
図であって、半田層３ａ、３ｂの間に介在させる銅薄板
５に格子状に複数個の貫通孔5aを設けたものである。そ
して、銅基板１と絶縁層２との間に両面に半田３ａ、3b
を圧着させた銅薄板５を載置して銅基板１と絶縁層２を
半田接合させる時に銅薄板５の貫通孔５ａ内に半田を３
ｃのように埋め込むのである。このようにすると、銅薄
板５を含めた半田層３ａ、３ｂは、より半田の膨張、収
縮特性に近似することとなり、銅基板の熱膨張に対する
緩和効果もより大きくすることができる。FIG. 3 is a sectional view showing another embodiment of the present invention, in which a plurality of through holes 5a are provided in a grid pattern in a copper thin plate 5 interposed between the solder layers 3a and 3b. is there. Then, solder 3a, 3b is provided on both surfaces between the copper substrate 1 and the insulating layer 2.
When the copper thin plate 5 to which is pressure-bonded is placed and the copper substrate 1 and the insulating layer 2 are solder-bonded, solder is applied to the through holes 5a of the copper thin plate 5 with solder 3
It is embedded like c. By doing so, the solder layers 3a and 3b including the copper thin plate 5 become closer to the expansion and contraction characteristics of the solder, and the effect of relaxing the thermal expansion of the copper substrate can be further increased.
【００１２】この発明において半田層３ａ、３ｂの間に
介在させる銅薄板５の厚さは０．５ｍｍ以下とすること
が必要である。これは銅薄板の厚さが０．５ｍｍを超え
ると、銅薄板５の膨張、収縮が銅自体の熱膨張係数に基
くものとなって、半田層３ａ、３ｂの間に介在させるこ
の発明の効果を果さないためである。In the present invention, the thickness of the copper thin plate 5 interposed between the solder layers 3a and 3b needs to be 0.5 mm or less. This is because when the thickness of the copper thin plate exceeds 0.5 mm, the expansion and contraction of the copper thin plate 5 are based on the coefficient of thermal expansion of the copper itself, and the effect of the present invention to intervene between the solder layers 3a and 3b. This is because it does not fulfill.
【００１３】また、この発明は半田層３ａ、３ｂの間に
０．５ｍｍ以下の厚みの銅薄板を介在させて半田層の厚
さを実質的に厚くしたことによりパワーサイクルによる
半田疲労の発生サイクル数を大幅に伸長することができ
る。In addition, according to the present invention, a solder fatigue occurrence cycle due to a power cycle is achieved by interposing a copper thin plate having a thickness of 0.5 mm or less between the solder layers 3a and 3b to substantially increase the thickness of the solder layer. The number can be greatly extended.
【００１４】上記の実施例においては金属基板１として
銅基板を、絶縁層２としてＡｌ2 Ｏ3 セラミックスを、
また金属薄板５として銅薄板を用いて説明したが、金属
基板としては銅のほかにアルミニウムあるいは鉄、絶縁
層としてはＡｌＮセラミックスを用いることもできる。
金属薄板は半田付けしやすいことから銅薄板が最も好ま
しいが、このほかに半田付けしやすい材料としては金、
銀などがあり、また表面をメタライズした鉄薄板を用い
てもよい。In the above embodiment, the metal substrate 1 is a copper substrate, the insulating layer 2 is Al 2 O 3 ceramics,
Further, although a copper thin plate is used as the metal thin plate 5, aluminum or iron may be used as the metal substrate in addition to copper, and AlN ceramics may be used as the insulating layer.
Copper thin plate is the most preferable because it is easy to solder the metal thin plate, but other materials that are easy to solder are gold,
An iron thin plate that has silver or the like and whose surface is metallized may be used.
【００１５】以上は、この発明をパワーモジュールを例
にして説明したが、この発明はパワーモジュールに限定
されるものではなく、半田を接合材として使用する全て
のパワーデバイスに適用しうるものである。Although the present invention has been described above by taking the power module as an example, the present invention is not limited to the power module and can be applied to all power devices using solder as a bonding material. .
【００１６】[0016]
【発明の効果】以上説明したように、この発明は半導体
装置の製造において、熱膨張係数の異なる材料からなる
金属基板とセラミックス絶縁層を半田層にて接合する際
に、半田層を２層とし、この２層の半田層の間に０．５
ｍｍ厚以下の金属薄板を介在させたことによって、半田
層の厚さを実質的に厚くして温度上昇に伴なう金属基板
の熱膨張をこの半田層にて緩和させ、絶縁層が割れるな
ど金属基板の熱膨張により絶縁層に与える弊害を除去す
ることができるのである。As described above, according to the present invention, when a metal substrate made of a material having a different coefficient of thermal expansion and a ceramic insulating layer are joined by a solder layer, the solder layer is formed into two layers in the manufacture of a semiconductor device. , 0.5 between these two solder layers
By interposing a thin metal plate having a thickness of mm or less, the thickness of the solder layer is substantially increased, and the thermal expansion of the metal substrate due to the temperature rise is alleviated by this solder layer, and the insulating layer is cracked. It is possible to remove the harmful effect on the insulating layer due to the thermal expansion of the metal substrate.
【図１】この発明の一実施例を示す半導体装置の部分断
面図である。FIG. 1 is a partial cross-sectional view of a semiconductor device showing an embodiment of the present invention.
【図２】従来の半導体装置の部分断面図である。FIG. 2 is a partial cross-sectional view of a conventional semiconductor device.
【図３】この発明の他の実施例を示す半導体装置の部分
断面図である。FIG. 3 is a partial cross-sectional view of a semiconductor device showing another embodiment of the present invention.
１ 金属基板 ２ セラミックス絶縁層 ３ａ 半田層 ３ｂ 半田層 ３ｃ 半田層 ４ 半田層チップ ５ 金属薄板 ５ａ 貫通孔 1 Metal Substrate 2 Ceramics Insulation Layer 3a Solder Layer 3b Solder Layer 3c Solder Layer 4 Solder Layer Chip 5 Metal Thin Plate 5a Through Hole
Claims (4)
板と絶縁層を半田層を介して接合し、上記絶縁層上に半
導体チップを搭載した半導体装置において、上記半田層
を２層とし、この２層の半田層の間に０．５ｍｍ厚以下
の金属薄板を介在させたことを特徴とする半導体装置。1. In a semiconductor device in which a metal substrate made of a material having a different coefficient of thermal expansion is bonded to an insulating layer via a solder layer, and a semiconductor chip is mounted on the insulating layer, the solder layer has two layers. A semiconductor device, wherein a thin metal plate having a thickness of 0.5 mm or less is interposed between two solder layers.
ｍ厚以下の金属薄板に複数個の貫通孔を形成し、この貫
通孔中に半田を埋め込んだことを特徴とする請求項１記
載の半導体装置。2. 0.5 m interposed between two solder layers
2. The semiconductor device according to claim 1, wherein a plurality of through holes are formed in a metal thin plate having a thickness of m or less, and solder is embedded in the through holes.
である請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the metal substrate is copper, aluminum or iron.
ラミックスである請求項１記載の半導体装置。4. The semiconductor device according to claim 1, wherein the insulating layer is a ceramic of Al 2 O 3 or AlN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4109289A JP2558574B2 (en) | 1992-04-01 | 1992-04-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4109289A JP2558574B2 (en) | 1992-04-01 | 1992-04-01 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05283555A JPH05283555A (en) | 1993-10-29 |
| JP2558574B2 true JP2558574B2 (en) | 1996-11-27 |
Family
ID=14506405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4109289A Expired - Fee Related JP2558574B2 (en) | 1992-04-01 | 1992-04-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2558574B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07297560A (en) * | 1994-04-28 | 1995-11-10 | Hitachi Ltd | Multilayer printed wiring board and its mounting structure |
| US6087596A (en) * | 1997-12-04 | 2000-07-11 | Ford Motor Company | Solder joints for printed circuit boards having intermediate metallic member |
| DE10352670A1 (en) * | 2003-11-11 | 2005-06-16 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Electric component with equaliser of temperature caused mechanical stresses, connecting two part-elements with different length expansion coefficients, e.g. for optical components, i.e. glass plate connected to copper electrode etc |
-
1992
- 1992-04-01 JP JP4109289A patent/JP2558574B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05283555A (en) | 1993-10-29 |
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