JPS5952853A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5952853A
JPS5952853A JP57162361A JP16236182A JPS5952853A JP S5952853 A JPS5952853 A JP S5952853A JP 57162361 A JP57162361 A JP 57162361A JP 16236182 A JP16236182 A JP 16236182A JP S5952853 A JPS5952853 A JP S5952853A
Authority
JP
Japan
Prior art keywords
section
solder
sections
plate
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57162361A
Other languages
Japanese (ja)
Inventor
Yasutoshi Kurihara
保敏 栗原
Tadashi Minagawa
皆川 忠
Michio Ogami
大上 三千男
Takayuki Wakui
和久井 陽行
Komei Yatsuno
八野 耕明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57162361A priority Critical patent/JPS5952853A/en
Publication of JPS5952853A publication Critical patent/JPS5952853A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To reduce thermal strain applied to the end section of a solder layer, and to prevent the deformation and thermal fatigue breakdown of each member by forming a notch section or a recessed section to at least one of the fringe sections of the surfaces of a semiconductor base body and an insulating member and the surface section of a metallic member opposite to the fringe sections. CONSTITUTION:A metallic support member 11 is formed by a copper plate, and the recessed section 28 of 3mm. width X 0.5mm. depth is formed to a section opposite to the fringe section of the insulating member 12 placed in the upper surface of the member 11. The insulating members 12 consisting of two alumina plates are bonded by the solder layers 29 while being conformed to the positions of the recessed sections 28 of the metallic support member 11, and metallic plates 13 are bonded on each insulating member 12 by the solder layers 30. Sections opposite to the solder layers 29, 30 of the insulating members 12 are metallized. The metallic plate 13 is formed by a copper plate in 2mm. thickness, and the notch section 31 of 3mm. width X 0.5mm. depth is formed to the fringe section of the lower surface of the plate 13 and the recessed sections 28 of 1.5mm. width X0.5mm. depth to sections opposite to the fringe sections of semiconductor base bodies 14, 15, 16 placed on the upper surface of the plate 13 by a press.

Description

【発明の詳細な説明】 本発明は、半導体装置に係シ、特に半導体基体が絶縁部
材上に金属板を介して載1hされた構造を有する絶縁型
の半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to an insulated semiconductor device having a structure in which a semiconductor substrate is mounted on an insulating member via a metal plate.

従来、半導体装置は電極及び熱伝導路を兼ねた金属から
成る支持部材上に半導体基体を載置して形成されたもの
が多かったが、近年、半導体装置の回路適用上の自由度
を改善させるため、或いは、電気回路のv積比を図るた
めなどから、半導体基体或いは回路ごとなどに絶縁部材
を介して同一支持部材上に載置させた絶縁型半導体装置
が考案されている。
In the past, most semiconductor devices were formed by placing a semiconductor substrate on a support member made of metal that also served as electrodes and heat conduction paths, but in recent years, the degree of freedom in circuit application of semiconductor devices has been improved. For this reason, or to improve the v-product ratio of an electric circuit, an insulated semiconductor device has been devised in which each semiconductor substrate or circuit is mounted on the same support member via an insulating member.

例えば、絶縁型トライアックは双方向性3端子サイリス
タ基体をセラミック板上に載置し、このセラミック板を
金属からなるパッケージに封入したものであり、トライ
アックの全ての電極はセラミック板によりパッケージと
絶縁されて外部に引き出された構造を有している。この
ような絶縁型トライアックは、一対の主電極が回路上の
接地電位から電気的に絶縁されなければならない回路に
適用される場合であっても、パッケージを直接接地電位
部に固定できるので、回路適用上の自由度が改善される
For example, an insulated triac has a bidirectional three-terminal thyristor base mounted on a ceramic plate, and this ceramic plate is enclosed in a metal package, and all electrodes of the triac are insulated from the package by the ceramic plate. It has a structure that is drawn out to the outside. Such isolated triacs can be used in circuits where the pair of main electrodes must be electrically isolated from the ground potential on the circuit, since the package can be fixed directly to the ground potential. The freedom of application is improved.

また、混成集積回路装置或いは半導体モジュール装置(
以下、晶成ICと一括して略称する)では、一般に、複
数の半導体素子などからなるまとまった電気回路から形
成されている。それらの回路の少なくとも一部と支持部
材或いは放熱部拐等の金属部材とを電気的に絶縁しなけ
ればならないことがあり、通常、金属支持部材と混成I
C基体との間に有機質或いは無機質の絶縁層を設けるこ
とによシ絶縁がなされている。このように形成された混
成ICも絶縁型半導体装置である。
In addition, hybrid integrated circuit devices or semiconductor module devices (
A crystalline IC (hereinafter collectively referred to as a crystallized IC) is generally formed from a unified electric circuit made up of a plurality of semiconductor elements and the like. It may be necessary to electrically insulate at least a part of those circuits from metal members such as support members or heat dissipation parts.
Insulation is achieved by providing an organic or inorganic insulating layer between the C substrate and the substrate. The hybrid IC formed in this manner is also an insulated semiconductor device.

上述した絶縁型半導体装置にあって、半導体素子の動作
時に発生される熱は、半導体基体から接着材層及び絶縁
層を介して支持部材に伝導され、主としてこの支持部材
から気中々どへ放熱されることになる。この放熱が有効
になされなければ、半導体装置の動作が不安定になるな
どの障害が生じることから高い放熱性を備えていなけれ
ばならない。また、回路電圧の高電圧化或いは半導体装
置の経時的安定性及び耐湿性、耐熱性などの信頼性を向
上させるため高い絶縁性を備えていなければならない。
In the above-mentioned insulated semiconductor device, heat generated during operation of the semiconductor element is conducted from the semiconductor substrate to the support member via the adhesive layer and the insulating layer, and is mainly radiated from the support member to the air. That will happen. If this heat dissipation is not effective, problems such as unstable operation of the semiconductor device will occur, so it is necessary to have high heat dissipation performance. Furthermore, it must have high insulation properties in order to increase the circuit voltage or to improve reliability such as stability over time, moisture resistance, and heat resistance of the semiconductor device.

特に、半導体装置の発熱量が比較的大きく、且つ、高耐
電圧や高信頼性が要求されるものにあっては、十分前記
要求を満足させるものとして、例えば、絶縁層にはセラ
ミックスの如き無機質材料が、接着材ノーにはpb−s
n系はんだの如き金層ろうが適用される。
In particular, in semiconductor devices that generate a relatively large amount of heat and are required to have high withstand voltage and high reliability, it is necessary to use inorganic materials such as ceramics for the insulating layer to fully satisfy the above requirements. The material is PB-S without adhesive.
A gold layer solder such as n-based solder is applied.

また、一般に、絶縁型半導体装置では半導体基体は絶縁
層上に直接ではなく、半導体基体と外部の電源とを結ぶ
導電路及び半導体基体での発熱を絶縁層に効果的に伝え
る熱伝導路としての金属板を介して取り付けられる。こ
の金属板としては低抵抗で且つ高い熱伝導性を有する銅
等の材料が一般に適用されている。
Additionally, in general, in an insulated semiconductor device, the semiconductor substrate is not placed directly on the insulating layer, but rather as a conductive path connecting the semiconductor substrate to an external power source and a heat conduction path that effectively transfers heat generated in the semiconductor substrate to the insulating layer. Attached via metal plate. As this metal plate, a material such as copper, which has low resistance and high thermal conductivity, is generally used.

ところが、銅の熱膨張係数は18X10”’/Cておる
のに対し、例えば半導体基体のシリコンと絶縁層のアル
ミナセラミックの熱膨張係数は各々3.5X10″′6
7Cと6.3 X 10−’/Cであり、それらの熱膨
張係数の差が非常に大きいことから、次に述べるような
問題を生ずることがあった。
However, while the thermal expansion coefficient of copper is 18X10''/C, for example, the thermal expansion coefficients of silicon for the semiconductor substrate and alumina ceramic for the insulating layer are each 3.5X10'''6.
7C and 6.3 x 10-'/C, and since the difference in their thermal expansion coefficients is very large, the following problems may occur.

即ち、上述のような絶縁型半導体装置のはんだ付は工程
は、通常、絶縁層と金属板と半導体基体とを各々はんだ
層を介して積層させた後、はんだの融点以上に昇温さぜ
、次に室温まで冷却させて接着させている。この冷却過
程のはんだ凝固点温度付近にてそれらの各部材が互いに
固着される。
That is, the soldering process of the above-mentioned insulated semiconductor device usually involves laminating an insulating layer, a metal plate, and a semiconductor substrate through a solder layer, and then raising the temperature to a temperature higher than the melting point of the solder. Next, it is cooled to room temperature and bonded. During this cooling process, these members are fixed to each other near the solder freezing point temperature.

この固着された状態のまま更に室温まで冷却されると、
各部材は固有の熱膨張係数に応じて収縮されるので、は
んだ接着部に熱歪が残留されることになる。この熱歪が
小さい場合は比較約款かい部材のはんだ層の変形によっ
て吸収されるが、熱歪が大きい場合には吸収しきれずに
、半導体基体や絶縁層に収縮応力が作用して半導体基体
を変形させ、電気特性に障害を与えたシ、さらには、半
導体基体あるいはアルミナセラミック板を機械的に破損
させてしまうという虞れを有していた。
When this fixed state is further cooled to room temperature,
Since each member contracts according to its own coefficient of thermal expansion, thermal strain remains in the solder joint. If this thermal strain is small, it will be absorbed by the deformation of the solder layer of the component, but if the thermal strain is large, it will not be fully absorbed and shrinkage stress will act on the semiconductor substrate and insulating layer, deforming the semiconductor substrate. There is a risk that the electrical characteristics may be damaged, and furthermore, the semiconductor substrate or the alumina ceramic plate may be mechanically damaged.

また、上述のような絶縁型半導体装置の各部材は、通電
、休止の動作に伴って、繰り返し高温(約100〜15
0C)と低温(周囲温度)の温度状態変化を受ける。こ
のようなヒートサイクルごとに、各部材は膨張、収縮さ
れ、前述したように各部材の熱膨張係数の差によって主
としてはんだ層に熱応力による歪が印加される。したが
って、はんだ層はこの歪により周期的に圧縮、引張され
、ついには熱疲労現象によりもろくなってクラックを生
じ、はんだ層の接層力及び導電性、熱伝導性の低下が引
起されるという虞れがあった。特にこの現象ははんだ層
の露出端面部において顕著である。
In addition, each member of the insulated semiconductor device described above is repeatedly exposed to high temperatures (approximately 100 to 15
0C) and low temperature (ambient temperature). During each such heat cycle, each member is expanded and contracted, and as described above, distortion due to thermal stress is mainly applied to the solder layer due to the difference in the coefficient of thermal expansion of each member. Therefore, the solder layer is periodically compressed and stretched by this strain, and eventually becomes brittle and cracks due to thermal fatigue phenomenon, which may cause a decrease in the contact strength, electrical conductivity, and thermal conductivity of the solder layer. There was that. This phenomenon is particularly noticeable at the exposed end face portions of the solder layer.

上記した問題は各部材の熱膨張係数の差に起因して生起
されるものであるから、金属板の熱膨張係数が半導体基
体や絶縁部材のそれと比較的近似な値の材料(例えばモ
リブデンやタングステンなど〕を適用することにより解
決しようとすることが提案されている。例えば、銅など
の低抵抗で良熱伝導性を有する廉価な材料の金属板と、
半導体基体との間にモリブデン片を介装させたものが知
られている。これによれば、半導体基体と銅板との熱膨
張差に起因して半導体基体に作用する熱応力を緩和させ
、半導体基体の劣化防止を図ることができる。しかし、
アルミナセラミック板などの絶縁部材と銅板との熱膨張
差による熱応力を吸収させることはできないので、はん
だ付は時の変形防止やヒートサイクルによる熱疲労現象
の防止には全く効果がなかった。しかも、熱伝導性に劣
るモリブデン片及びはんだ層などが余分に介装されるこ
とKなシ、特に半導体基体の過渡的な放熱効果が低下さ
れるという欠点を有するものであシ、且つ、製造面から
みても、部品数の増加やろう何部の増加を招くことから
コストアップになるという欠点を有するものであった。
The above-mentioned problem is caused by the difference in the coefficient of thermal expansion of each member, so the metal plate is made of a material whose coefficient of thermal expansion is relatively similar to that of the semiconductor substrate or insulating member (for example, molybdenum or tungsten). For example, it has been proposed to solve the problem by applying a metal plate made of an inexpensive material such as copper that has low resistance and good thermal conductivity.
A device in which a molybdenum piece is interposed between the semiconductor substrate and the semiconductor substrate is known. According to this, thermal stress acting on the semiconductor substrate due to the difference in thermal expansion between the semiconductor substrate and the copper plate can be alleviated, and deterioration of the semiconductor substrate can be prevented. but,
Since it is not possible to absorb thermal stress due to the difference in thermal expansion between an insulating member such as an alumina ceramic plate and a copper plate, soldering has no effect on preventing deformation over time or thermal fatigue caused by heat cycles. Moreover, it has the drawback that molybdenum pieces and solder layers, which have poor thermal conductivity, are extra interposed, and the transient heat dissipation effect of the semiconductor substrate is particularly deteriorated. From a point of view, this method has the drawback of increasing the number of parts and the number of wax parts, leading to an increase in cost.

本発明の目的は、製造時及び作動時の熱歪を低減し、各
部材の変形及び熱疲労破損を防止できる絶縁型の半導体
装置を提供することにある。
An object of the present invention is to provide an insulated semiconductor device that can reduce thermal strain during manufacturing and operation, and prevent deformation and thermal fatigue damage of each member.

本発明は、金属ろう等から成るはんだ層の熱疲労破壊は
、そのはんだ層周端部から発生し成長するという現象に
鑑みなされたもので、金属板や支持部材としての金属部
材に対向する半導体基体と絶縁部材との面の周縁部と、
該周縁部に対向する前記金属部材の表面部との少なくと
も一方に、はんだ層の端部層厚を増大形成させる如く切
欠き部又は凹部を形成することにより、はんだ層の端部
に加わる熱歪を低減し、各部材の変形及び熱疲労破壊を
防止しようとするものである。
The present invention was developed in view of the phenomenon that thermal fatigue failure of a solder layer made of metal solder etc. occurs and grows from the peripheral edge of the solder layer. a peripheral edge of the surface of the base and the insulating member;
By forming a notch or a recess on at least one side of the surface of the metal member facing the peripheral edge so as to increase the thickness of the end of the solder layer, thermal strain applied to the end of the solder layer can be reduced. This aims to reduce deformation and thermal fatigue failure of each member.

以下、本発明の図示実施例を用いて、更に詳細に説明す
る。
Hereinafter, the present invention will be explained in more detail using illustrated embodiments.

第1図に本発明の適用されだ一実施例の、1,5KVA
級電流制御用混成ICの要部斜視図が示されており、第
2図には第1図図示実施例の回路構成図が示されている
FIG. 1 shows a 1.5 KVA of an embodiment to which the present invention is applied.
2 is a perspective view of a main part of the hybrid IC for class current control, and FIG. 2 shows a circuit configuration diagram of the embodiment shown in FIG. 1.

第1図に示されたように、金属部材からなる支持部材1
1の上面にアルミナ板からなる2枚の絶縁部材12がは
んだにより固着されている。前記絶縁部材12上に略同
−形状の金属板13が各々金属ろうにニジ固着されてい
る。この金属板13上に、第2図に示された回路が形成
されており、ダーリントン接続されたトランジスタ14
及び15、フライホイル用ダイオード16が夫々金属板
13上に直接ろう付けされている。また、スナバ用チッ
プコンデンサ17及びこれと直列に接続されたチップ抵
抗18が載置されている。
As shown in FIG. 1, a support member 1 made of a metal member
Two insulating members 12 made of alumina plates are fixed to the upper surface of the insulating member 1 by solder. On the insulating member 12, metal plates 13 having substantially the same shape are fixed to each other with metal solder. The circuit shown in FIG. 2 is formed on this metal plate 13, and Darlington-connected transistors 14
and 15, flywheel diodes 16 are directly brazed onto the metal plate 13, respectively. Further, a snubber chip capacitor 17 and a chip resistor 18 connected in series with the snubber chip capacitor 17 are mounted.

上記の各回路素子間は配線用ワイヤ19或いは条片20
、配線用金属片21によって第2図に示された回路構成
図のように接続されている。外部端子22は金属板13
上に直接、外部端子23は配線用金属片21を介して、
外部端子24は絶縁用有機樹脂膜25及びその上に接続
された配線用金属片21を介して、各々接続されている
。これら外部端子と反対側の金属板13の端部には、ド
ライバ回路26に接続される端子27が、絶縁用有機樹
脂膜25上に接着された配線用金属片21上に設けられ
ている。
Wiring wires 19 or strips 20 are connected between each of the above circuit elements.
, are connected by a wiring metal piece 21 as shown in the circuit configuration diagram shown in FIG. The external terminal 22 is a metal plate 13
The external terminal 23 is connected directly to the top via the wiring metal piece 21.
The external terminals 24 are connected to each other via an insulating organic resin film 25 and a wiring metal piece 21 connected thereon. At the end of the metal plate 13 opposite to these external terminals, a terminal 27 connected to the driver circuit 26 is provided on the wiring metal piece 21 bonded onto the insulating organic resin film 25.

このように、複数の半導体基体(トランジスタ14.1
5及びダイオード16)を含む回路素子が、同一の金属
板13上に直接はんだ付けされて混成ICが形成されて
いる。このように形成された実施例の金属板13と、絶
縁部材12と、支持部材11との接着部の断面図が、第
3図に示されている。
In this way, a plurality of semiconductor bodies (transistors 14.1
5 and a diode 16) are directly soldered onto the same metal plate 13 to form a hybrid IC. A cross-sectional view of the bonded portion between the metal plate 13, the insulating member 12, and the supporting member 11 of the embodiment formed in this way is shown in FIG.

第3図において、金属支持部材11は、厚さ3、2 r
trm X幅61謔×長さ105mmの銅板から形成さ
れておシ、その上表面には、載置される絶縁部材12の
周縁部に対向する部分に、幅31IIII+×深さ0、
5 ranの凹部28が形成されている。
In FIG. 3, the metal support member 11 has a thickness of 3.2 r
It is formed from a copper plate with a width of 61mm x a length of 105mm, and on the upper surface thereof, a width of 31III+ x a depth of 0 is provided on the part facing the peripheral edge of the insulating member 12 to be placed.
A concave portion 28 of 5 ran is formed.

この金属支持部材11の凹部28の位置に一致させて、
2枚のアルミナ板の絶縁部材12が鉛−60%錫はんだ
層29にょシ接庸されている。はんだ層29の中央部厚
さは約0.1 mmであシ、凹部28の形成された端部
厚さは約0.6t+mとなっている。絶縁部材12の接
着面には周知のメタライズ処理が施され、はんだに対す
るぬれ性が付与されている。絶縁部材12は幅28關×
長さ33mX厚さ0.6mmに形成されたアルミナ板で
ある。
Matching the position of the recess 28 of this metal support member 11,
Two alumina plate insulating members 12 are bonded to a lead-60% tin solder layer 29. The thickness of the center portion of the solder layer 29 is approximately 0.1 mm, and the thickness of the end portion where the recessed portion 28 is formed is approximately 0.6 t+m. The bonding surface of the insulating member 12 is subjected to a well-known metallization process to impart wettability to solder. The insulating member 12 has a width of 28 mm.
It is an alumina plate formed with a length of 33 m and a thickness of 0.6 mm.

各絶縁部材12の上には、金属板13が、はんだ層30
によシ接着されている。このはんだ層30は前記はんだ
層29と同一組成、同一厚さのものである。絶縁部材1
2のはんだ層3oと対向する部分には上述と同様、メタ
ライズ処理が施されている。
A metal plate 13 is placed on each insulating member 12, and a solder layer 30 is placed on top of each insulating member 12.
It is glued well. This solder layer 30 has the same composition and the same thickness as the solder layer 29. Insulating member 1
The portion facing the solder layer 3o of No. 2 is subjected to metallization treatment as described above.

金属板13は厚さ2咽の銅板から形成されておシ、その
下面の周縁部には幅3咽×深さ0.5 mmの切欠き部
31が、また上面には載置される半導体基体14,15
.16の周縁部に対向する部分に、幅1.5 rtrm
 X深さ0.5mmの四部28がプレスによって形成さ
れている。各金属板13の上には半導体基体14,15
.16 (面積8mX8mm、厚さ0.25 rran
 )が、はんだ層32の中央部厚さは約0.1mであシ
、四部28の形成された端部厚さは約0,6咽となって
いる。なお、はんだ層32の組成は前記はんだ層29.
30と同一のものである。
The metal plate 13 is formed from a copper plate with a thickness of 2 mm, and has a notch 31 with a width of 3 mm and a depth of 0.5 mm on the peripheral edge of its lower surface, and a semiconductor to be placed on the upper surface. Base 14, 15
.. 1.5 rtrm width in the part opposite to the peripheral edge of 16
Four portions 28 having an X depth of 0.5 mm are formed by pressing. On each metal plate 13 are semiconductor substrates 14 and 15.
.. 16 (area 8m x 8mm, thickness 0.25 rran
), but the thickness of the center part of the solder layer 32 is about 0.1 m, and the thickness of the end part where the four parts 28 are formed is about 0.6 m. Note that the composition of the solder layer 32 is the same as that of the solder layer 29.
It is the same as 30.

このように構成されていることから、つまシ熱疲労の発
生起点となるはんだ層端部の厚みが、十分厚く形成され
ていることから、混成ICの製造時や動作時に、はんだ
層端部に生ずる熱応力を十分に緩和させることができ、
これによって熱歪の発生及び熱疲労を効果的に防止させ
ることができる。
Because of this structure, the thickness of the solder layer end, which is the starting point for the occurrence of tab thermal fatigue, is formed sufficiently thick, so during the manufacture and operation of hybrid ICs, the solder layer end has a sufficient thickness. The thermal stress that occurs can be sufficiently alleviated,
This can effectively prevent the occurrence of thermal strain and thermal fatigue.

従って、従来構造の絶縁型半導体装置、即ち絶縁部材上
に銅などの金属板とモリブデン片を各々はんだにより接
着し、このモリブデン片上に半導体基体がはんだによシ
接着された構造のものにあっては、絶縁部材に作用され
る熱応力を緩オロさせることができないうえ、放熱効果
が低下されるという欠点を有していたが、本実施例によ
れば、放熱効果を損うことなく各部材にがかる熱歪をは
んだ層によって吸収するとともに、はんだM端部の熱応
力を緩和させて熱疲労破壊を防止させることができると
いう効果がある。
Therefore, in an insulated semiconductor device with a conventional structure, that is, a metal plate such as copper and a piece of molybdenum are bonded to an insulating member by solder, and a semiconductor substrate is bonded to the molybdenum piece by solder. However, according to this example, each member can be easily removed without impairing the heat dissipation effect. This has the effect of absorbing the thermal strain caused by the solder layer by the solder layer, and alleviating the thermal stress at the end of the solder M, thereby preventing thermal fatigue fracture.

特に、大型の混成IC半導体装置において上述の効果は
著しいものとなる。即ち、大型混成ICにあっては発熱
量が犬きく、シかも大面積の半導体基体が大数載置され
ることから、熱拡散板として機能する金属板が必然的に
大面積のものとなるので、熱膨張差による影響は極めて
大きな障害となっていたのである。このことについて、
第4図及び第5図に示されたヒートサイクル試験は、−
55tl:’4−Jp1500を1ザイクルとして、連
続150ザイクルの条件にて行ったものである。
In particular, the above-mentioned effect becomes remarkable in large-sized hybrid IC semiconductor devices. In other words, in large hybrid ICs, the amount of heat generated is high, and a large number of large-area semiconductor substrates are mounted, so the metal plate that functions as a heat diffusion plate must necessarily have a large area. Therefore, the influence of the difference in thermal expansion was an extremely large obstacle. Regarding this,
The heat cycle test shown in FIGS. 4 and 5 is -
55tl: '4-Jp1500 was used as one cycle, and the test was carried out under the conditions of 150 consecutive cycles.

図中、曲線Bは上述の従来例の混成ICを示すものであ
る。図示されたように、絶縁部側(アルミナ板〕の面積
Srが約500mm”までは、A。
In the figure, curve B shows the above-mentioned conventional hybrid IC. As shown in the figure, A is applied until the area Sr on the insulating part side (alumina plate) is approximately 500 mm''.

Bともに故障発生率Fは0%であった。しかし、約50
0mm2を超えると、Bは加速度的に故障発生率が増加
するのに対して、Aでは依然として0%である。なお、
ここで1つ故に;++とは生としてはんだ層のクラック
発生、或いは部分的剥離を生じたものである。
The failure rate F for both B was 0%. However, about 50
When it exceeds 0 mm2, the failure rate increases at an accelerating rate in B, while it is still 0% in A. In addition,
Here, for one reason; ++ means that cracks or partial peeling occurred in the raw solder layer.

また、第4図において、8!が500m’以下の場合、
上記の故障こそ発生しなかったが、金属支持部材の変形
を測定してみたところ、本実施例のものの長手方向のそ
りの高さは約20μmであったのに対し、従来例のもの
は約0,33〜1.5順にもなっていた。このことは、
金属支持部材とエポキシ樹脂製等の枠或いは蓄との間に
すきを生じさせる原因となるので、半導体装置の密封性
の障害となり、ひいては耐湿性の点で支障をきだす原因
となるものである。しかるに、本実施例のものは変形が
小さいことから上記の虞れは全くないという効果を有し
ている。
Also, in Figure 4, 8! is less than 500m',
Although the above failure did not occur, when we measured the deformation of the metal support member, we found that the height of warpage in the longitudinal direction of this example was approximately 20 μm, while that of the conventional example was approximately 20 μm. It was also in the order of 0.33 to 1.5. This means that
It causes a gap between the metal support member and the frame or storage made of epoxy resin, etc., which impedes the sealing performance of the semiconductor device and, in turn, causes a problem in terms of moisture resistance. . However, since the deformation of the present embodiment is small, the above-mentioned risk does not occur at all.

第5図の横軸には1枚の半導体基体の面積Ssが、縦軸
には混成ICの故障発生率F2が示されている。ヒート
サイクル試験の条件と、図中曲線に付された符号A、B
は第4図と同様である。ただし、実験に用いた従来構造
の混成ICには、モリブデン片を介装させないものが適
用されている。
The horizontal axis of FIG. 5 shows the area Ss of one semiconductor substrate, and the vertical axis shows the failure rate F2 of the hybrid IC. Heat cycle test conditions and symbols A and B attached to the curves in the figure
is the same as in FIG. However, the hybrid IC with the conventional structure used in the experiment does not include a molybdenum piece.

図示されたように、面積S@が約25咽2まではA、B
ともに故障発生率F2は0%であったが、約25H2を
越えると、Bでは加速的に故障発生率が増加するのに対
して、Aでは依然として0%に近い水準であった。ここ
で言う故障とは半導体基体と金属板(熱拡散板)間のは
んだ層のクラック発生、あるいは部分的剥離を生じたも
のである。
As shown in the diagram, A, B until the area S@ is about 25mm2
The failure rate F2 was 0% in both cases, but when it exceeded about 25H2, the failure rate increased rapidly in case B, whereas it was still at a level close to 0% in case A. The failure here refers to cracking or partial peeling of the solder layer between the semiconductor substrate and the metal plate (thermal diffusion plate).

なお、上記実施例においては、各はんだ層29゜30.
320熱歪を吸収させる手段として、金属支持部材11
に四部28を、金属板13に切欠き部31と四部28と
を設けている。これらの熱歪吸収手段を全て具えること
が、信頼性を向上させるという点で好ましいのであるが
、設計的には条件に応じて、必要とする熱歪吸収手段の
みを設ければよいことは言うまでもない。例えば、はん
だj@30と32との信頼性にのみ主眼をおいた場合に
は、金属支持部材11の凹部28を省略することも可能
であり、この場合にはそりを十分低減できる厚みの金属
支持部材とすることが望捷しい。
In the above embodiment, each solder layer is 29° 30°.
320 Metal support member 11 as a means for absorbing thermal strain
A notch 31 and a four part 28 are provided in the metal plate 13. It is preferable to provide all of these thermal strain absorbing means from the standpoint of improving reliability, but from a design perspective, it is only necessary to provide the necessary thermal strain absorbing means depending on the conditions. Needless to say. For example, if the main focus is only on the reliability of the solders J@30 and 32, it is possible to omit the recess 28 of the metal support member 11, and in this case, the metal is thick enough to sufficiently reduce warpage. It is desirable to use it as a support member.

また、金属支持部材11又は金属板13の金属部材に形
成する熱歪吸収手段は、上記実施例で述べたプレス法の
他に、サンドブラスト法、切削加工法、エツチング法、
研磨法等によって設けてもよいが、量産性の観点からは
プレス法によるものが最も有利である。この熱歪吸収手
段は金属部材に限らず、対応する絶縁部材12又は半導
体基体14.15.16に形成しても、同様の効果が得
られることは汀うまでもない。
Further, the thermal strain absorbing means formed on the metal member of the metal support member 11 or the metal plate 13 can be formed by a sandblasting method, a cutting method, an etching method, in addition to the pressing method described in the above embodiment.
Although it may be provided by a polishing method or the like, a pressing method is most advantageous from the viewpoint of mass productivity. It goes without saying that this thermal strain absorbing means is not limited to a metal member, and the same effect can be obtained even if it is formed on the corresponding insulating member 12 or semiconductor substrate 14, 15, 16.

第6図に本発明の適用された他の実姉例の主要部断面図
が示されている。
FIG. 6 shows a sectional view of the main parts of another practical example to which the present invention is applied.

第6図において、支持部材34はアルミナセラミックか
ら形成されており、その下面には放熱フィン34aが、
上面には例えばニッケル又は銅等の4膜から成る金属層
35が設けられている。この金属層35の上面に、はん
だ1−30によって金属板13が接着されている。この
金属板13の上面には第3図実施例と同様に、混成IC
回路等が組み立てられるのであるが、本図では説明を簡
単にするため省略されている。なお、支持部材34は幅
25酎×長さ30喘のアルミナ板、はんだ層30は鉛−
5%錫−1,5%銀はんだ、金属板13は幅22岨×長
さ27mの銅板であり、この金属板13にはプレスによ
って切欠き部31が形成されている。まだ、はんだ層3
0の中央部厚みは0.1咽であり、切欠き部38の厚み
は0,6間となっている。
In FIG. 6, the support member 34 is made of alumina ceramic, and a heat radiation fin 34a is provided on the lower surface of the support member 34.
A metal layer 35 made of four films, such as nickel or copper, is provided on the upper surface. The metal plate 13 is bonded to the upper surface of this metal layer 35 with solder 1-30. On the upper surface of this metal plate 13, there is a hybrid IC, similar to the embodiment shown in FIG.
Although circuits and the like are assembled, they are omitted in this figure to simplify the explanation. The support member 34 is an alumina plate with a width of 25 mm and a length of 30 mm, and the solder layer 30 is made of lead.
The metal plate 13 made of 5% tin-1.5% silver solder is a copper plate with a width of 22 m and a length of 27 m, and a notch 31 is formed in the metal plate 13 by pressing. Still solder layer 3
The thickness of the center portion of the 0.0 mm is 0.1 mm, and the thickness of the cutout portion 38 is between 0.6 mm.

このように構成すれば、支持部材34が絶縁部材として
の機能をも兼ね具えていることから、前記第3図図示実
施例の効果に加えて、構成が簡単になるという効果があ
る。
With this structure, since the support member 34 also has the function of an insulating member, in addition to the effect of the embodiment shown in FIG. 3, the structure can be simplified.

以上、2つの実施例に基づいて本発明を説明したが、本
発明はこれらの実施例に限られるものではなく、例えば
次に述べるようなものも含まれる。
Although the present invention has been described above based on two embodiments, the present invention is not limited to these embodiments, and includes, for example, the following embodiments.

まず、金属板の材質は銅板に代えて、ニッケル、亜鉛、
アルミニウム、金、銀、パラジウム等の如く、導電性や
熱伝導性に優れた金属、あるいはそれらを主成分とする
合金を適用できる。また、金属板等に形成する四部や切
欠き部の形状は、それぞれ第7図(a)〜(d)、第8
図(a)〜(d)に示された形状凹部28や切欠き部3
1等から、選択的に適用可能である。
First, the material of the metal plate is nickel, zinc, etc. instead of copper plate.
Metals with excellent electrical conductivity and thermal conductivity, such as aluminum, gold, silver, palladium, etc., or alloys containing these as main components can be used. In addition, the shapes of the four parts and notches formed in the metal plate etc. are shown in Figures 7(a) to (d) and 8, respectively.
Recesses 28 and cutouts 3 shown in figures (a) to (d)
It can be applied selectively from the 1st class.

無機絶縁部材としては、アルミナの他、窒化アルミニウ
ム(AtN)、窒化シリコン(Si3N4)、酸化ベリ
リウム(Bed)、炭化シリコン(S iC)等、ある
いはこれらを成分とする混合物又は焼結体が適用可能で
ある。
As the inorganic insulating material, in addition to alumina, aluminum nitride (AtN), silicon nitride (Si3N4), beryllium oxide (Bed), silicon carbide (SiC), etc., or mixtures or sintered bodies containing these components can be used. It is.

はんだとしては、鉛−60%錫の組成の他、例えば鉛−
5%錫のもの、あるいはこれらに第3成分として銀、イ
ンジウム等を含むものが使用できる。その厚さも0.1
 mmに限られず、それよシ厚くても薄くてもよい。一
般にはんだ層が厚いと熱歪を良く吸収するが、はんだそ
のものの熱伝導率はさほど高くないことから、混成IC
の放熱性が低下する。上述したように、本発明によれば
熱歪の発生を抑制し得るから、はんだ層の厚さを効果的
に減少し混成ICの放熱性を高めることができるという
効果がある。
In addition to the composition of lead-60% tin, for example, lead-60% tin can be used as the solder.
Those containing 5% tin or those containing silver, indium, etc. as a third component can be used. Its thickness is also 0.1
It is not limited to mm, and may be thicker or thinner. In general, thicker solder layers absorb thermal strain better, but since the thermal conductivity of the solder itself is not very high, hybrid IC
heat dissipation is reduced. As described above, according to the present invention, the occurrence of thermal strain can be suppressed, so that the thickness of the solder layer can be effectively reduced and the heat dissipation performance of the hybrid IC can be improved.

金属板上に載置される半導体基体の種類又は回路構成に
関しても、任意の半導体素子(シリコン以外の半導体を
用いたものを含む〕及び回路について適用できることは
言うまでもない。
It goes without saying that the present invention can be applied to any semiconductor element (including those using semiconductors other than silicon) and circuits with respect to the type of semiconductor substrate placed on the metal plate or the circuit configuration.

以上説明したように、本発明によれば、製造時や作動時
の熱歪を低減させることができ、各部材の変形及び熱疲
労破壊を防止させることができるという効果がある。
As explained above, according to the present invention, it is possible to reduce thermal strain during manufacturing and operation, and there is an effect that deformation and thermal fatigue failure of each member can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の適用された一実施例の絶縁型混成IC
の斜視図、第2図は第1図図示実施例の回路図、第3図
は第1図図示実施例の要部断面図、第4図及び第5図は
本発明の詳細な説明するだめの故障発生率の実験値を示
す線図、第6図は本発明の他の実施例の要部断面図、第
7図(a)〜(d)及び第8図(a)〜(d)はそれぞ
れ凹部及び切欠き部の変形例を示す断面図である。 11・・・支持部材、12・・・絶縁部材、13・・・
金属板、14.15.16・・・半導体基体、28・・
・四部、31・・・切欠き部、29,30.32・・・
はんだ層、代理人 弁理士 高橋明、米、 L) ・什、、1 茅 1 目 // 第2 区 ヒー    、−−」〜26 $3 目 // 第4図 βz(QfX摺2) 茅5目 βS(酢惧り 茅  乙   図 第7目 8 !46目 (α)研刑し、。 /3 (cl)  二mmし31
FIG. 1 shows an insulated hybrid IC according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of the embodiment shown in FIG. 1, FIG. 3 is a cross-sectional view of the main part of the embodiment shown in FIG. Fig. 6 is a sectional view of main parts of another embodiment of the present invention, Fig. 7 (a) to (d) and Fig. 8 (a) to (d). 2A and 2B are cross-sectional views showing modified examples of a recessed portion and a notched portion, respectively. 11... Supporting member, 12... Insulating member, 13...
Metal plate, 14.15.16...Semiconductor substrate, 28...
・Four parts, 31... Notch parts, 29, 30.32...
Solder layer, agent Patent attorney Akira Takahashi, USA, L) ・Yu,, 1 Chi 1st // 2nd Ward He, --'' ~ 26 $3 Eyes// Fig. 4 βz (QfX Print 2) Chi 5 Eye βS (Vinegar Kaya Otsu Figure 7th eye 8! 46th eye (α) sharpened. /3 (cl) 2mm and 31

Claims (1)

【特許請求の範囲】[Claims] 1、金属部材に半導体基体と無機絶縁部材の少なくとも
一方が金属ろうからなるはんだ層により接合された構造
を有する半導体装置において、前記半導体基体と前記絶
縁部材との前記金属部材に対向する面の周縁部と1、該
周縁部に対向する前記金属部材の表面部との少なくとも
一方に、前記はんだ層の端部層厚を増大形成させる如く
切欠き部又は凹部が形成されてなることを特徴とする半
導体装置。
1. In a semiconductor device having a structure in which at least one of a semiconductor substrate and an inorganic insulating member is bonded to a metal member by a solder layer made of a metal solder, the periphery of the surface of the semiconductor substrate and the insulating member that faces the metal member. 1. A notch or a recess is formed in at least one of part 1 and the surface part of the metal member facing the peripheral part, so as to increase the thickness of the end part of the solder layer. Semiconductor equipment.
JP57162361A 1982-09-20 1982-09-20 Semiconductor device Pending JPS5952853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57162361A JPS5952853A (en) 1982-09-20 1982-09-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57162361A JPS5952853A (en) 1982-09-20 1982-09-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5952853A true JPS5952853A (en) 1984-03-27

Family

ID=15753101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57162361A Pending JPS5952853A (en) 1982-09-20 1982-09-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5952853A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1107310A2 (en) * 1999-12-08 2001-06-13 DaimlerChrysler Rail Systems GmbH Isolation improvement of high power semiconductor modules
EP0921565A3 (en) * 1997-12-08 2005-07-27 Kabushiki Kaisha Toshiba Package for semiconductor power device and method for assembling the same
EP1523037A3 (en) * 2003-10-10 2010-03-31 Dowa Metaltech Co., Ltd. Metal/ceramic bonding substrate and method for producing same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662343A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Electronic device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662343A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Electronic device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0921565A3 (en) * 1997-12-08 2005-07-27 Kabushiki Kaisha Toshiba Package for semiconductor power device and method for assembling the same
EP1107310A2 (en) * 1999-12-08 2001-06-13 DaimlerChrysler Rail Systems GmbH Isolation improvement of high power semiconductor modules
EP1107310A3 (en) * 1999-12-08 2005-04-27 DaimlerChrysler Rail Systems GmbH Isolation improvement of high power semiconductor modules
EP1523037A3 (en) * 2003-10-10 2010-03-31 Dowa Metaltech Co., Ltd. Metal/ceramic bonding substrate and method for producing same

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