JPH0583186B2 - - Google Patents
Info
- Publication number
- JPH0583186B2 JPH0583186B2 JP63290779A JP29077988A JPH0583186B2 JP H0583186 B2 JPH0583186 B2 JP H0583186B2 JP 63290779 A JP63290779 A JP 63290779A JP 29077988 A JP29077988 A JP 29077988A JP H0583186 B2 JPH0583186 B2 JP H0583186B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- bumps
- cap
- sealing cap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 30
- 238000007789 sealing Methods 0.000 claims description 20
- 239000000853 adhesive Substances 0.000 claims description 13
- 230000001070 adhesive effect Effects 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 11
- 230000017525 heat dissipation Effects 0.000 description 11
- 238000001723 curing Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000004519 grease Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000016 photochemical curing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、ギヤングボンデイング法により実装
される半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that is mounted by a Guyang bonding method.
［従来の技術］
バンプを介して半導体素子と基板を接合するギ
ヤングボンデグ法は、半導体素子からの放熱がバ
ンプを介して行われるため、放熱性が従来のワイ
ヤーボンデイング法による実装法に比べ劣るとい
う欠点がある。この為、ギヤングボンデイング
後、素子の裏面に放熱板を接着したり、バネによ
り封止用キヤツプを圧接し、放熱性の向上を図つ
ている。[Prior Art] The Guyang bonding method, which connects a semiconductor element and a substrate through bumps, has the disadvantage that heat radiation from the semiconductor element is performed through the bumps, so the heat radiation performance is inferior to that of the conventional wire bonding method. There is. For this reason, after gigantic bonding, a heat dissipation plate is adhered to the back surface of the element, or a sealing cap is pressed against the element using a spring to improve heat dissipation.
第２図及び第３図はかかる従来の封止構造を示
すもので、第２図はキヤツプ封止の場合、第３図
は樹脂封止の場合を示す。第２図において、１は
基板、２は基板１上に形成された導体パターン、
３は半導体素子、４はバンプ、５は放熱用ヒート
シンク、６は封止用キヤツプで、キヤツプ６は接
着剤７により基板１に接着されている。また、第
３図において、８は封止樹脂である。 2 and 3 show such conventional sealing structures, with FIG. 2 showing the case of cap sealing and FIG. 3 showing the case of resin sealing. In FIG. 2, 1 is a substrate, 2 is a conductive pattern formed on the substrate 1,
3 is a semiconductor element, 4 is a bump, 5 is a heat sink for heat dissipation, and 6 is a sealing cap. The cap 6 is bonded to the substrate 1 with an adhesive 7. Moreover, in FIG. 3, 8 is a sealing resin.
［発明が解決しようとする課題］
しかしながら、上記の如き従来例においては、
バンプ４と半導体素子３及びバンプ４と導体パタ
ーン２はそれぞれ金属的に結合されているため、
基板１と半導体素子３の膨張差による応力を吸収
できず、従つて、ヒートサイクルのような熱スト
レスによりクラツク等が入り信頼性に欠けるとい
う欠点があつた。[Problem to be solved by the invention] However, in the conventional example as described above,
Since the bumps 4 and the semiconductor element 3 and the bumps 4 and the conductor pattern 2 are respectively coupled metallically,
It is not possible to absorb the stress caused by the difference in expansion between the substrate 1 and the semiconductor element 3, and as a result, there is a drawback that cracks occur due to thermal stress such as a heat cycle, resulting in a lack of reliability.
本発明は上記欠点に鑑みなされたもので、その
目的とするところは、放熱板等の装着を必要とす
ることなく、ギヤングボンデイングされた半導体
素子の放熱の向上が図れ、しかも、信頼性の高い
半導体装置を提供するにある。 The present invention was made in view of the above-mentioned drawbacks, and its purpose is to improve the heat dissipation of a gigantically bonded semiconductor element without requiring the installation of a heat sink, etc., and to improve reliability. Our goal is to provide high quality semiconductor devices.
［課題を解決するための手段］
本発明は上記課題を解決するため、表面に導体
パターンが形成された基板と半導体素子とをバン
プを介して接合して成る半導体装置において、前
記バンプを前記導体パターンの所定位置若しくは
半導体素子の所定位置に当接すると共に、前記半
導体素子上に封止用キヤツプを被せ、該封止用キ
ヤツプの開口端を前記基板に収縮性の高い接着剤
で接着したことを特徴とする。[Means for Solving the Problems] In order to solve the above problems, the present invention provides a semiconductor device in which a substrate on which a conductor pattern is formed and a semiconductor element are bonded via bumps, in which the bumps are connected to the conductor. A sealing cap is brought into contact with a predetermined position of the pattern or a predetermined position of the semiconductor element, and a sealing cap is placed over the semiconductor element, and the open end of the sealing cap is adhered to the substrate with a highly shrinkable adhesive. Features.
［作用］
上記構成により、接着剤の硬化時の収縮力によ
り半導体素子は基板に圧接され、半導体素子−バ
ンプ−導体パターン間の電気的コンタクトが得ら
れると共に、半導体素子は封止用ギヤツプに圧接
され、半導体素子の放熱の向上が図れる。また、
基板と半導体素子とはバンプを介して圧接結合さ
れているため、基板と半導体素子の膨張差による
応力の影響を受けない。[Function] With the above configuration, the semiconductor element is pressed against the substrate by the shrinkage force when the adhesive hardens, and electrical contact is obtained between the semiconductor element, the bump, and the conductor pattern, and the semiconductor element is pressed against the sealing gap. As a result, heat dissipation of the semiconductor element can be improved. Also,
Since the substrate and the semiconductor element are pressure bonded via the bumps, they are not affected by stress due to the difference in expansion between the substrate and the semiconductor element.
［実施例］
第１図は本発明の一実施例を示すもので、１は
表面に導体パターン２が形成された基板、３はバ
ンプ４を有する半導体素子で、前記導体パターン
２の所定位置にバンプ４が位置するように載置さ
れている。６は金属製（放熱性に優れ、気密性を
有するものであれば金属に限定されない）の封止
用キヤツプで、その開口端は収縮性の高い接着剤
９により基板１に接着されている。１０は半導体
素子３と封止用キヤツプ６の間に介在された放熱
用グリスである。[Embodiment] FIG. 1 shows an embodiment of the present invention, in which 1 is a substrate having a conductive pattern 2 formed on its surface, 3 is a semiconductor element having bumps 4, and a semiconductor element is provided at a predetermined position of the conductive pattern 2. It is placed so that the bumps 4 are located. Reference numeral 6 denotes a sealing cap made of metal (not limited to metal as long as it has excellent heat dissipation properties and airtightness), and its open end is bonded to the substrate 1 with adhesive 9 having high shrinkage properties. Reference numeral 10 denotes heat dissipation grease interposed between the semiconductor element 3 and the sealing cap 6.
次に、本実施例の実装方法を説明する。まず、
パターンニングされた基板１上に、バンプ４を有
する半導体素子３を位置決めして搭載し、この上
から封止用キヤツプ６を被せる。そして、このキ
ヤツプ６を収縮性の高い接着剤９により基板１に
接着する。接着剤９は収縮性の高いものが選択さ
れているので、硬化時の収縮力により半導体素子
３は基板１に圧接され、半導体素子３とバンプ４
と導体パターン２とは電気的に接続される。 Next, the implementation method of this embodiment will be explained. first,
A semiconductor element 3 having bumps 4 is positioned and mounted on a patterned substrate 1, and a sealing cap 6 is placed over it. Then, this cap 6 is bonded to the substrate 1 using a highly shrinkable adhesive 9. Since the adhesive 9 is selected to have a high shrinkage property, the semiconductor element 3 is pressed against the substrate 1 by the shrinkage force during curing, and the semiconductor element 3 and the bumps 4 are bonded together.
and conductor pattern 2 are electrically connected.
ここで、キヤツプ６の凹部の凹み寸法Ｈを半導
体素子３の厚みｔとほぼ同じになるようにしてお
く。このようにして半導体素子３の上にキヤツプ
６を被せると、バンプ４の高さ分だけキヤツプ６
は基板１より浮くことになり、この浮いた部分に
前述の硬化時に収縮する接着剤９を塗布し、半導
体素子３に硬化時に荷重が加わるようにする。 Here, the concave dimension H of the concave portion of the cap 6 is made to be approximately the same as the thickness t of the semiconductor element 3. When the cap 6 is placed over the semiconductor element 3 in this way, the cap 6 is covered by the height of the bump 4.
will float above the substrate 1, and the above-described adhesive 9, which shrinks during curing, is applied to this floating portion so that a load is applied to the semiconductor element 3 during curing.
このように構成することにより、半導体素子３
の放熱がキヤツプ６を通して行われ、前述のギヤ
ツプボンデイングの欠点が解放される。また、半
導体素子３の基板１への接合と封止が同時に行な
え、工程の合理化が図れる。さらに、通常、半導
体素子３を基板１に接合する際、金バンプの場合
は500℃程度、半田バンプの場合でも250〜300℃
の加熱工程を必要とするが、本実施例では接着剤
９の硬化温度（150〜200℃）でよく、熱によるダ
メージを素子３及び基板１に与えずに実装できる
（接着剤９が光硬化樹脂の場合、加熱も不要）。さ
らにまた、バンプ４と基板１との間は圧接されて
いる為、ヒートサイクルのような熱ストレスによ
る半導体素子３と基板１の膨張差により、バンプ
４が基板１上の導体パターン２上を摺動し、基板
１や素子３に応力がかからない構造となり、信頼
性の向上が図れる。 With this configuration, the semiconductor element 3
The heat dissipation is carried out through the cap 6, and the above-mentioned drawbacks of gap bonding are overcome. Furthermore, bonding and sealing of the semiconductor element 3 to the substrate 1 can be performed at the same time, thereby streamlining the process. Furthermore, when bonding the semiconductor element 3 to the substrate 1, the temperature is usually about 500°C in the case of gold bumps, and 250 to 300°C in the case of solder bumps.
However, in this example, the curing temperature of the adhesive 9 (150 to 200°C) is sufficient, and it can be mounted without causing heat damage to the element 3 and the substrate 1 (the adhesive 9 is photocured). In the case of resin, heating is not required). Furthermore, since the bumps 4 and the substrate 1 are in pressure contact, the bumps 4 may slide on the conductor pattern 2 on the substrate 1 due to the difference in expansion between the semiconductor element 3 and the substrate 1 due to thermal stress such as a heat cycle. The structure is such that no stress is applied to the substrate 1 or the element 3, and reliability can be improved.
なお、上記実施例では、バンプ４は半導体素子
３に形成されているが、基板１の導体パターン２
上に形成してもよい。また、バンプ４の材料は、
酸化しない金が適当であるが、バンプ全体が金で
ある必要はなく、中心が銅で表面がニツケルメツ
キまたは金メツキというように、多層のバンプで
もよい。さらに、半導体素子３と封止用キヤツプ
６の間に放熱用グリス１０を介在させて熱的結合
を良くしているが、この放熱用グリス１０は無く
てもよい。また、キヤツプ６と基板１の接合用の
接着剤９は収縮性が高く、半導体素子３とバンプ
４に硬化時に荷重が加わるようなものであればよ
く、例えば、エポキシ樹脂やアクリル樹脂が適当
である。硬化方法も熱硬化性でもよいし、光硬化
性のものでもよい。 In the above embodiment, the bumps 4 are formed on the semiconductor element 3, but the bumps 4 are formed on the conductor pattern 2 of the substrate 1.
It may be formed on top. In addition, the material of the bump 4 is
Gold that does not oxidize is suitable, but it is not necessary that the entire bump be made of gold; it may be a multilayered bump, such as a copper center and a nickel or gold plated surface. Furthermore, although heat dissipation grease 10 is interposed between the semiconductor element 3 and the sealing cap 6 to improve thermal coupling, this heat dissipation grease 10 may be omitted. Further, the adhesive 9 for bonding the cap 6 and the substrate 1 may be one that has a high shrinkage property and can apply a load to the semiconductor element 3 and bumps 4 during curing. For example, epoxy resin or acrylic resin is suitable. be. The curing method may be thermosetting or photocuring.
［発明の効果］
本発明は上記のように、表面に導体パターンが
形成された基板と半導体素子とをバンプを介して
接合して成る半導体装置において、前記バンプを
前記導体パターンの所定位置若しくは半導体素子
の所定位置に当接すると共に、前記半導体素子上
に封止用キヤツプを被せ、該封止用キヤツプの開
口端を前記基板に収縮性の高い接着剤で接着した
ことを特徴とするので、放熱板等の装着を必要と
することなく、ギヤングボンデイングされた半導
体素子の放熱の向上が図れ、しかも、信頼性の高
い半導体装置を提供することができる。[Effects of the Invention] As described above, the present invention provides a semiconductor device in which a substrate on which a conductor pattern is formed and a semiconductor element are bonded via bumps, in which the bumps are connected to predetermined positions of the conductor pattern or the semiconductor element. The semiconductor element is brought into contact with a predetermined position of the element, and a sealing cap is placed over the semiconductor element, and the open end of the sealing cap is bonded to the substrate with a highly shrinkable adhesive, thereby dissipating heat. It is possible to improve the heat dissipation of the giant bonded semiconductor element without requiring the attachment of a plate or the like, and to provide a highly reliable semiconductor device.
第１図は本発明の一実施例を示す断面図、第２
図及び第３図はそれぞれ従来例を示す断面図であ
る。
１……基板、２……導体パターン、３……半導
体素子、４……バンプ、６……封止用キヤツプ、
９……接着剤。
FIG. 1 is a cross-sectional view showing one embodiment of the present invention, and FIG.
3 and 3 are sectional views each showing a conventional example. 1...Substrate, 2...Conductor pattern, 3...Semiconductor element, 4...Bump, 6...Sealing cap,
9...Adhesive.
Claims (1)
体素子とをバンプを介して接合して成る半導体装
置において、前記バンプを前記導体パターンの所
定位置若しくは半導体素子の所定位置に当接する
と共に、前記半導体素子上に封止用キヤツプを被
せ、該封止用キヤツプの開口端を前記基板に収縮
性の高い接着剤で接着したことを特徴とする半導
体装置。1. In a semiconductor device in which a substrate having a conductive pattern formed on its surface and a semiconductor element are bonded via bumps, the bump is brought into contact with a predetermined position of the conductor pattern or a predetermined position of the semiconductor element, and the semiconductor element is A semiconductor device characterized in that a sealing cap is placed thereon, and an open end of the sealing cap is adhered to the substrate with a highly shrinkable adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63290779A JPH02135762A (en) | 1988-11-16 | 1988-11-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63290779A JPH02135762A (en) | 1988-11-16 | 1988-11-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02135762A JPH02135762A (en) | 1990-05-24 |
| JPH0583186B2 true JPH0583186B2 (en) | 1993-11-25 |
Family
ID=17760404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63290779A Granted JPH02135762A (en) | 1988-11-16 | 1988-11-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02135762A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3097644B2 (en) | 1998-01-06 | 2000-10-10 | 日本電気株式会社 | Semiconductor device connection structure and connection method |
| US6218730B1 (en) * | 1999-01-06 | 2001-04-17 | International Business Machines Corporation | Apparatus for controlling thermal interface gap distance |
| JP4659257B2 (en) * | 2001-04-18 | 2011-03-30 | パナソニック株式会社 | Manufacturing method of electronic component assembly |
| JP6330241B2 (en) * | 2014-12-25 | 2018-05-30 | セイコーＮｐｃ株式会社 | Vacuum-sealed module and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63118185A (en) * | 1986-11-06 | 1988-05-23 | 松下電器産業株式会社 | Electrode connection structural body for flat type display device |
| JPS63133554A (en) * | 1986-11-25 | 1988-06-06 | Nec Corp | Semiconductor device |
| JPS63261841A (en) * | 1987-04-20 | 1988-10-28 | Fuji Electric Co Ltd | Structure of burying and packaging semiconductor device in multilayered interconnection substrate |
-
1988
- 1988-11-16 JP JP63290779A patent/JPH02135762A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63118185A (en) * | 1986-11-06 | 1988-05-23 | 松下電器産業株式会社 | Electrode connection structural body for flat type display device |
| JPS63133554A (en) * | 1986-11-25 | 1988-06-06 | Nec Corp | Semiconductor device |
| JPS63261841A (en) * | 1987-04-20 | 1988-10-28 | Fuji Electric Co Ltd | Structure of burying and packaging semiconductor device in multilayered interconnection substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02135762A (en) | 1990-05-24 |
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| JPH0436115Y2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |