JPS6360533B2 - - Google Patents
Info
- Publication number
- JPS6360533B2 JPS6360533B2 JP56152632A JP15263281A JPS6360533B2 JP S6360533 B2 JPS6360533 B2 JP S6360533B2 JP 56152632 A JP56152632 A JP 56152632A JP 15263281 A JP15263281 A JP 15263281A JP S6360533 B2 JPS6360533 B2 JP S6360533B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- supporter
- semiconductor
- convex electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
この発明は多数の凸起電極を有する半導体素子
をセラミツク等からなる基板に固着する半導体装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a semiconductor element having a large number of convex electrodes is fixed to a substrate made of ceramic or the like.
従来この種のフエースダウンボンデイング方式
半導体装置においては、凸起電極に熱応力がかか
ることによる機械的損傷を避けるため凸起電極を
半導体素子の中央部にもつてきたりして、かなり
無理なプロセスを採つていた。また、電極を半導
体素子の周辺部に設ける場合においては素子の大
きさに制限があり、このフエースダウンボンデイ
ング方式は大きな素子には適用できなかつた。 Conventionally, in this type of face-down bonding type semiconductor device, in order to avoid mechanical damage due to thermal stress applied to the protruding electrode, the protruding electrode was placed in the center of the semiconductor element, which required a rather difficult process. I was picking. Furthermore, when electrodes are provided on the periphery of a semiconductor element, there is a limit to the size of the element, and this face-down bonding method cannot be applied to large elements.
本発明は上記欠点を除くためになされたもの
で、熱応力が凸起電極にかかるのを防止でき、高
信頼度な素子と基板との接続部を得ることのでき
る半導体装置を提供することを目的とする。 The present invention has been made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a semiconductor device that can prevent thermal stress from being applied to the convex electrode and provide a highly reliable connection between the element and the substrate. purpose.
本発明に係る半導体装置は、半導体素子の凸起
電極を有する面と反対の面部に、基板と同一の材
質からなるサポータを固着したものである。 In the semiconductor device according to the present invention, a supporter made of the same material as the substrate is fixed to the surface of the semiconductor element opposite to the surface having the convex electrode.
以下、この発明の一実施例を図について説明す
る。 An embodiment of the present invention will be described below with reference to the drawings.
第1図は本実施例の構成を示し、1は半導体素
子2を1個あるいは複数個搭載するための基板
で、通常はセラミツク、あるいはガラスエポキシ
材からなる。3は半導体素子2と基板1とを電気
的、機械的に接続するための凸起電極を示し、半
導体素子2、及び基板1の両方、あるいは一方に
凸起を設けた、いわゆる“バンプ”である。ま
た、4は基板1と同一材質からなるサポータ、5
は接着層である。 FIG. 1 shows the structure of this embodiment. Reference numeral 1 denotes a substrate on which one or more semiconductor elements 2 are mounted, and is usually made of ceramic or glass epoxy material. 3 indicates a protruding electrode for electrically and mechanically connecting the semiconductor element 2 and the substrate 1, and is a so-called "bump" in which a protrusion is provided on both or one of the semiconductor element 2 and the substrate 1. be. Further, 4 is a supporter made of the same material as the substrate 1;
is the adhesive layer.
また、第2図は半導体装置が温度サイクルを受
けた場合にバンプが変位するときの変位量を説明
するための模式図であり、aは従来の装置、bは
本実施例による装置について示している。 Further, FIG. 2 is a schematic diagram for explaining the amount of displacement when a bump is displaced when a semiconductor device is subjected to a temperature cycle, in which a shows a conventional device and b shows a device according to this embodiment. There is.
以下、これらの図を用いて本実施例におけるサ
ポータ4の機能について詳細に説明する。 Hereinafter, the functions of the supporter 4 in this embodiment will be explained in detail using these figures.
通常、バンプは半田等の軟材質からなり、比較
的機械的には弱い、従来の半導体装置では、温度
サイクルを受けるとシリコンと基板との熱膨張差
によりこの弱いバンプ部に熱応力が加わり、第2
図aに示すようにバンプ3に歪が生じ破壊が生じ
て、装置が不良となつていた。 Bumps are usually made of a soft material such as solder, and are relatively mechanically weak. In conventional semiconductor devices, when subjected to temperature cycles, thermal stress is applied to the weak bumps due to the difference in thermal expansion between silicon and the substrate. Second
As shown in Figure a, the bumps 3 were distorted and destroyed, resulting in a defective device.
本実施例では、凸起電極3を有する面と反対の
面に、基板1と同一の材質からなり、かつ、半導
体素子2を拘束するに十分な厚さを有するサポー
タ4を設け、接着層5により固着させている。 In this embodiment, a supporter 4 made of the same material as the substrate 1 and having a thickness sufficient to restrain the semiconductor element 2 is provided on the surface opposite to the surface having the convex electrode 3, and an adhesive layer 5 is provided. It is fixed by
これにより、装置が熱サイクルを受けた場合
に、基板1とサポータ4とが同じように伸縮し、
第2図bに示すように半導体素子2もサポータ4
に拘束されてほぼ同じように伸縮するため、バン
プ3の変位を従来に比して小さくすることができ
る。従つて、本実施例の如くサポータを有する場
合には、従来の如くサポータのない場合のような
低サイクルでのバンプ破壊を防止することがで
き、フエースダウンボンデイング方式の実装の最
大の欠陥を軽減し、温度サイクルによる装置の寿
命を伸ばすことができる。 As a result, when the device undergoes a thermal cycle, the substrate 1 and the supporter 4 expand and contract in the same way,
As shown in FIG. 2b, the semiconductor element 2 is also supported by the supporter 4.
Since the bump 3 expands and contracts in substantially the same way, the displacement of the bump 3 can be made smaller than in the past. Therefore, when a supporter is provided as in this embodiment, it is possible to prevent bump destruction at a low cycle as in the conventional case without a supporter, and the biggest defect in mounting the face-down bonding method is alleviated. However, the life of the device can be extended by temperature cycling.
なお、上記サポータ4は単に板状のものでもよ
いが、放熱特性向上のための手段や、さらに外部
への電極取り出し等のためのスルーホールを設け
ることも可能である。 Note that the supporter 4 may be simply plate-shaped, but it is also possible to provide means for improving heat dissipation characteristics and through-holes for taking out electrodes to the outside.
また、図示はしていないが、本発明は、基板1
へ半導体素子2を多数搭載するいわゆるモジユー
ルの場合にも適用できるし、その場合には、サポ
ータ4は多数の半導体素子2に共通的な構造にも
できるのは言うまでもない。 Further, although not shown in the drawings, the present invention provides a substrate 1
It goes without saying that the present invention can also be applied to a so-called module in which a large number of semiconductor elements 2 are mounted, and in that case, the supporter 4 can have a structure common to a large number of semiconductor elements 2.
以上のようにこの発明に係る半導体装置によれ
ば、半導体素子の凸起電極を有する面と反対の面
に基板と同一材質からなるサポータを設けたの
で、半導体素子と基板が同じように伸縮し、最も
弱い凸起電極部への熱応力の緩和が可能であり、
大きな半導体素子においてもフエースダウンボン
デイング方式の適用を可能になし得る効果があ
る。 As described above, according to the semiconductor device of the present invention, since the supporter made of the same material as the substrate is provided on the surface of the semiconductor element opposite to the surface having the convex electrode, the semiconductor element and the substrate can expand and contract in the same manner. , it is possible to relax the thermal stress on the weakest convex electrode part,
This has the effect of making it possible to apply the face-down bonding method even to large semiconductor devices.
第1図は本発明の一実施例を示す構成図で、第
2図は温度サイクルによるバンプの変位を示す摸
式図である。
1は基板、2は半導体素子、3は凸起電極、4
はサポータである。なお図中同一符号は同一又は
相当部分を示す。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a schematic diagram showing the displacement of bumps due to temperature cycles. 1 is a substrate, 2 is a semiconductor element, 3 is a convex electrode, 4
is a supporter. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
起電極により該半導体素子と接続される基板とを
有する半導体装置において、 上記半導体素子の上記凸起電極を有する面と反
対の面に上記基板と同一材質からなるサポータを
設けたことを特徴とする半導体装置。 2 上記基板はセラミツクからなるものであるこ
とを特徴とする特許請求の範囲第1項記載の半導
体装置。[Scope of Claims] 1. A semiconductor device having a semiconductor element having a convex electrode on one surface, and a substrate connected to the semiconductor element by the convex electrode, the surface of the semiconductor element having the convex electrode and the substrate connected to the semiconductor element by the convex electrode. A semiconductor device characterized in that a supporter made of the same material as the substrate is provided on the opposite surface. 2. The semiconductor device according to claim 1, wherein the substrate is made of ceramic.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56152632A JPS5853838A (en) | 1981-09-26 | 1981-09-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56152632A JPS5853838A (en) | 1981-09-26 | 1981-09-26 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5853838A JPS5853838A (en) | 1983-03-30 |
JPS6360533B2 true JPS6360533B2 (en) | 1988-11-24 |
Family
ID=15544626
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56152632A Granted JPS5853838A (en) | 1981-09-26 | 1981-09-26 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5853838A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04122460U (en) * | 1991-04-15 | 1992-11-04 | 三菱自動車工業株式会社 | Workpiece fixing device |
JP2002270634A (en) * | 2001-03-08 | 2002-09-20 | Rohm Co Ltd | Semiconductor device |
JP2007318182A (en) * | 2007-09-03 | 2007-12-06 | Rohm Co Ltd | Semiconductor device |
JP2011044755A (en) * | 2010-12-03 | 2011-03-03 | Rohm Co Ltd | Semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS48101085A (en) * | 1972-03-31 | 1973-12-20 |
-
1981
- 1981-09-26 JP JP56152632A patent/JPS5853838A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS48101085A (en) * | 1972-03-31 | 1973-12-20 |
Also Published As
Publication number | Publication date |
---|---|
JPS5853838A (en) | 1983-03-30 |
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