JPS62265734A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS62265734A JPS62265734A JP10982286A JP10982286A JPS62265734A JP S62265734 A JPS62265734 A JP S62265734A JP 10982286 A JP10982286 A JP 10982286A JP 10982286 A JP10982286 A JP 10982286A JP S62265734 A JPS62265734 A JP S62265734A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- substrate
- integrated circuit
- semiconductor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000008188 pellet Substances 0.000 claims abstract description 24
- 239000004020 conductor Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 239000010408 film Substances 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 101000852483 Homo sapiens Interleukin-1 receptor-associated kinase 1 Proteins 0.000 description 1
- 102100036342 Interleukin-1 receptor-associated kinase 1 Human genes 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路装置に関し、特に薄膜集積回路素
子と半導体素子とを有する混成集積回路装置の構造に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and more particularly to the structure of a hybrid integrated circuit device having a thin film integrated circuit element and a semiconductor element.
従来、薄膜集積回路素子と半導体素子を有する混成集積
回路装置には以下に示される構造のものがあった。Conventionally, hybrid integrated circuit devices having a thin film integrated circuit element and a semiconductor element have the structure shown below.
第３図に示されるように、リードフレーム１上に導体回
路パターン１４を有する樹脂基板あるいはセラミックス
基板１３を搭載し、この基板表面に個別の半導体素子ペ
レット６および薄膜回路素子ペレッＩ−７をマウント剤
１５を用いて搭載し、しかる後これらの素子ペレット電
極と基板上電極とをワイヤーボンディングにより接続し
回路形成を行なったものがある。As shown in FIG. 3, a resin substrate or ceramic substrate 13 having a conductor circuit pattern 14 is mounted on a lead frame 1, and individual semiconductor element pellets 6 and thin film circuit element pellets I-7 are mounted on the surface of this substrate. There is a device in which the element pellet electrodes are mounted using the agent 15, and then the element pellet electrodes and the electrodes on the substrate are connected by wire bonding to form a circuit.
また、絶縁基板上に形成された薄膜回路素子を用いた例
は、従来より薄膜混成集積回路として広く知られている
が、主な構成例としては第４図に示されるように、セラ
ミックス基板１６上に薄膜回路素子および薄膜回路パタ
ーン４を形成し、この基板上に半導体素子ペレット６お
よび薄膜回路素子ペレット７をペレットマウント剤１５
を用いて搭載しワイヤーボンディングを行なったものが
ある。Examples using thin film circuit elements formed on an insulating substrate have been widely known as thin film hybrid integrated circuits, but as shown in FIG. A thin film circuit element and a thin film circuit pattern 4 are formed on the substrate, and a semiconductor element pellet 6 and a thin film circuit element pellet 7 are placed on this substrate using a pellet mounting agent 15.
There are some that are mounted using wire bonding.
あるいは、第５図に示されるようにバンプ付き半導体素
子ベレット６（以後これをフリップチップと称す）また
はビームリード付き半導体素子をフェイスダウンして搭
載したものがあげられる６〔発明が解決しようとする問
題点：１
しかし、個別の薄膜回路素子ベレットおよび半導体素子
ベレットを用いた例においては、回路基板上に個々の素
子ベレットをマウントする工程とそれらをワイヤーボン
ディングにより接続を行なう工程を含み、従って基板上
素子周辺部にワイヤーボンディング用の余白部を−２・
要とし、実装効率が低下するという欠点があった。Alternatively, as shown in FIG. 5, a bump-equipped semiconductor element pellet 6 (hereinafter referred to as a flip chip) or a beam lead-equipped semiconductor element mounted face-down may be used. Problem: 1 However, in the case of using individual thin film circuit element pellets and semiconductor element pellets, the process includes the process of mounting the individual element pellets on the circuit board and the process of connecting them by wire bonding. Add a margin of -2 for wire bonding around the upper element.
However, it has the drawback of reducing implementation efficiency.
また、一般の薄膜混成集積回路に半導体素子ペレ・ソト
をフェイスダウンして搭載する方法においては次のよう
な問題点があった。フリップチップを用いる方法では、
接合部となるバンブ電極がフレキシビリティに乏しいた
め、主として基板と素子の熱膨張係数の相異による機織
的ストレスに起因するクラ・ツクの発生等の不良が懸念
されている。Further, there are the following problems in the method of mounting a semiconductor element face-down on a general thin film hybrid integrated circuit. In the method using flip chips,
Since the bump electrode, which serves as the joint, has poor flexibility, there are concerns about defects such as cracks caused mainly by mechanical stress due to the difference in coefficient of thermal expansion between the substrate and the element.
また、フェイスダウンによる搭載方法は、半導体素子と
、基板とがフラットに接する部分が少なく放熱性に乏し
いため、一層熱放散性の高い基板の使用が求められてい
る。In addition, in the face-down mounting method, there is a small portion where the semiconductor element and the substrate are in flat contact with each other, and heat dissipation is poor, so there is a need to use a substrate with even higher heat dissipation.
また、ビームリードを用いた方法は、高い信頼性が得ら
れるもののコストが高くつき応用範囲も限られたものに
なっている。・
本発明の目的は、搭載素子と基板とのワイヤボンディン
グによる接続をなくし、それによりワイヤボンディング
用の余白部をなくし、高集積化を可能とし、また、接合
電極部に生じるクラツクの発生を防ぎ、かつ放熱性の優
れた混成集積回路装置を提供することにある。Furthermore, although a method using a beam lead can provide high reliability, it is expensive and has a limited range of applications. - The purpose of the present invention is to eliminate the connection between the mounted element and the substrate by wire bonding, thereby eliminating the blank space for wire bonding, enabling high integration, and also preventing the occurrence of cracks that occur in the bonding electrode part. The object of the present invention is to provide a hybrid integrated circuit device which has excellent heat dissipation properties.
本発明の混成集積回路装置は、絶縁層を施した半導体基
板上に薄膜コンデンサ素子、薄膜抵抗素子、薄膜インダ
クタ素子のうち必要とされる薄膜回路素子を形成し、さ
らに導体回路パターンを形成することにより薄膜集積回
路基板を構成し、その薄膜集積回路基板上に単数もしく
は複数の半導体素子ベレットおよび又は薄膜回路素子ベ
レットをバンブ電極を介して搭載することにより構成さ
れる構造を有している。The hybrid integrated circuit device of the present invention includes forming necessary thin film circuit elements among thin film capacitor elements, thin film resistance elements, and thin film inductor elements on a semiconductor substrate provided with an insulating layer, and further forming a conductive circuit pattern. It has a structure in which a thin film integrated circuit board is constructed, and one or more semiconductor element pellets and/or thin film circuit element pellets are mounted on the thin film integrated circuit board via bump electrodes.
次に、本発明の実施例について図面を参照して説明する
。第１図は本発明の一実施例の混成集積回路装置の断面
図であり、第２図は本発明の一実施例の部分拡大断面図
である。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a hybrid integrated circuit device according to an embodiment of the invention, and FIG. 2 is a partially enlarged sectional view of an embodiment of the invention.
まず、第１図に示すように、薄膜回路素子および薄膜回
路パターン４を有する半導体基板２上に、半導体ベレッ
ト６、薄膜回路素子ベレット７をバンブ電極５を介して
接合する。このようにして得られた混成集積回路装置は
、リードフレーム１上に搭載され、ワイヤーボンディン
グにより外部リード端子と接続され本実施例は完成する
。ここで、ベース基板として用いられる半導体基板は素
子ベレットの材質と整合させるためシリコン基板が用い
られ、その表面にはＳ＋Ｏｚもしくは５１３Ｎ４から成
る薄い絶縁層３が形成される。First, as shown in FIG. 1, a semiconductor pellet 6 and a thin film circuit element pellet 7 are bonded via bump electrodes 5 onto a semiconductor substrate 2 having a thin film circuit element and a thin film circuit pattern 4. As shown in FIG. The hybrid integrated circuit device thus obtained is mounted on a lead frame 1 and connected to external lead terminals by wire bonding to complete the present embodiment. Here, a silicon substrate is used as the semiconductor substrate used as the base substrate in order to match the material of the element pellet, and a thin insulating layer 3 made of S+Oz or 513N4 is formed on its surface.
また、第２図は薄膜回路素子を基板上に形成した部分の
拡大断面図であり、シリコン基板上に、通常の薄膜素子
工程、薄膜パターン工程を用いて抵抗体層９．導体Ｊｔ
Ｊｉｏ、ｉ膜Ｔａ層１１ 、 Ｔ ａ化成膜１２等によ
り導体回路パターン、薄膜抵抗体、ＦＪ膜コンデンサあ
るいは薄膜インダクタを形成する。このようにして得ら
れたシリコン藩膜喚積回路基板上に、単数あるいは複数
個の半導体素子ペレ・ント６および薄膜コンデンサ素子
・ｙｌ・、１膜抵抗ペレ・ソト等の薄膜手子ペレット７
をバンブ電極により接合する。FIG. 2 is an enlarged sectional view of a portion where a thin film circuit element is formed on a substrate, and a resistor layer 9 is formed on a silicon substrate using a normal thin film element process and a thin film pattern process. Conductor Jt
A conductive circuit pattern, a thin film resistor, an FJ film capacitor, or a thin film inductor is formed using Jio, an i-film Ta layer 11, a Ta chemical film 12, and the like. On the thus obtained silicon film integrated circuit board, one or more semiconductor elements pellets 6, thin film capacitor elements, one film resistor pellets 7, etc. are placed.
are joined by bump electrodes.
〔発明の効果′１
以上説明したように本発明は、シリコン等の半導体基板
上に形成したｉ４膜集積回路上に半導体素子ペレ・ソト
および薄膜素子ベレットをバンプを介して接合搭載する
ことにより次のような効果が生じる。[Effects of the Invention'1 As explained above, the present invention achieves the following effects by bonding and mounting a semiconductor element Pere-Soto and a thin film element Beret via bumps on an i4 film integrated circuit formed on a semiconductor substrate such as silicon. The following effect occurs.
（１）半導体素子周辺部に・ピ・要とされていたワイヤ
ーボンディング用余白部分が不必要となり、且つ薄膜回
路素子を基板と導体１ヒすると同時に覆膜素子ベレ・ソ
トとして基板上にら招↓にするため回路の高集積１ヒが
可能となる。(1) The blank area for wire bonding, which was considered necessary around the semiconductor element, is no longer necessary, and the thin film circuit element can be connected to the substrate and the conductor at the same time as the cover film element is exposed on the substrate. ↓, it becomes possible to have a highly integrated circuit.
（２）基板に半導体素子と同一の素材を用いろことによ
り、熱膨張係数の相異による機械的ストレスを大幅に低
減し、バンブあるいは接合電極部に生じるクラ・ツクの
発生率をおさえ回路の信頼性を向上することが可能とな
る。(2) By using the same material as the semiconductor element for the substrate, mechanical stress due to differences in thermal expansion coefficients can be significantly reduced, and the incidence of cracks that occur in bumps or bonding electrodes can be suppressed. It becomes possible to improve reliability.
く３）基板として主に用いられるシリコンは比較的熱放
散性が良好であることから、この点からも回路の高集積
化に好都合となる。3) Since silicon, which is mainly used as a substrate, has relatively good heat dissipation properties, it is also advantageous for high integration of circuits.
（４）本発明に用いられている半導体薄Ｍ集積回路基板
は、回路パターンおよび素子が薄膜により形成されてい
ることから、接続する半導体素子の下部となる基板素面
にも素子部および配線部を配置することが可能であり、
回路集精度を向上せしめ且つ回路設計を容易なものとす
ることができる。(4) Since the semiconductor thin M integrated circuit board used in the present invention has circuit patterns and elements formed of thin films, the element part and the wiring part are also formed on the bare surface of the substrate which is the lower part of the semiconductor element to be connected. It is possible to place
The accuracy of circuit assembly can be improved and circuit design can be made easier.
第１図は本発明の一実施例の混成集積回路の断面図、第
２図は本発明の一実施例の部分拡大断面図、第３図は従
来の混成集積回路の一例の断面図、第４図、第５図は何
れも従来の池の一例の部分断面図である。
１・・、リードフレーム、２・・・半導体（シリコン）
基板、３・・・絶縁層、４・・・薄膜回路素子および薄
膜回路パターン、５・・・バンプ電極、６・・・半導体
素子べし・・７１〜．７・・・Ｊ膜回路素子ベレ・ソト
、８・・・ポンディングワイヤ、９・・抵抗体層、１０
・・・導体層、１１・・・薄膜Ｔａ層、１２・・・Ｔ
ａ ４ヒ成膜、１３・・回路基板、１４・・・導＃Ｃ回
路バターシ、１５・・・ペレ・・１１・マウント剤、１
６・・セラミックス基板。
＼、′・〜−゛
す４−ブ
茅夕閏FIG. 1 is a cross-sectional view of a hybrid integrated circuit according to an embodiment of the present invention, FIG. 2 is a partially enlarged cross-sectional view of an embodiment of the present invention, and FIG. 3 is a cross-sectional view of an example of a conventional hybrid integrated circuit. 4 and 5 are both partial sectional views of an example of a conventional pond. 1..., lead frame, 2... semiconductor (silicon)
Substrate, 3... Insulating layer, 4... Thin film circuit element and thin film circuit pattern, 5... Bump electrode, 6... Semiconductor element... 71~. 7...J membrane circuit element beret/soto, 8...Ponding wire, 9...Resistor layer, 10
...Conductor layer, 11...Thin film Ta layer, 12...T
a 4 Film formation, 13... Circuit board, 14... Conductive #C circuit base, 15... Pelle... 11. Mounting agent, 1
6. Ceramic substrate. ＼、′・～゛Su4-bu Kaya Yuen
Claims (1)
受動素子及び導体回路パターン又は導体回路パターンを
形成してなる薄膜集積回路基板表面にバンプ電極を介し
て半導体素子及び又は薄膜受動素子ペレットを搭載した
ことを特徴とする混成集積回路装置。An insulating layer is provided on the surface of a semiconductor substrate, and a semiconductor element and/or a thin film passive element pellet is attached to the surface of a thin film integrated circuit board formed by forming a thin film passive element and a conductor circuit pattern or a conductor circuit pattern on the surface of the insulating layer via a bump electrode. A hybrid integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10982286A JPS62265734A (en) | 1986-05-13 | 1986-05-13 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10982286A JPS62265734A (en) | 1986-05-13 | 1986-05-13 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62265734A true JPS62265734A (en) | 1987-11-18 |
Family
ID=14520086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10982286A Pending JPS62265734A (en) | 1986-05-13 | 1986-05-13 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62265734A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09232500A (en) * | 1996-02-23 | 1997-09-05 | Nec Corp | Multichip semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50147292A (en) * | 1974-05-15 | 1975-11-26 |
-
1986
- 1986-05-13 JP JP10982286A patent/JPS62265734A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50147292A (en) * | 1974-05-15 | 1975-11-26 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09232500A (en) * | 1996-02-23 | 1997-09-05 | Nec Corp | Multichip semiconductor device |
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